Add fpu support.
This commit is contained in:
zhongan
Gregory Nutt
parent
957c14d95e
commit
0d3691a460
@ -132,11 +132,63 @@
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#ifdef CONFIG_ARCH_CHIP_GAP8
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/* 31 registers, ePC, plus 6 loop registers */
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# define XCPTCONTEXT_REGS (32 + 6)
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# define INT_XCPT_REGS (32 + 6)
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#else
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# define XCPTCONTEXT_REGS 33
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# define INT_XCPT_REGS 33
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#endif
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#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
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#ifdef CONFIG_ARCH_FPU
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#if defined(CONFIG_ARCH_DPFPU)
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# define FPU_REG_SIZE 2
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#elif defined(CONFIG_ARCH_QPFPU)
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# define FPU_REG_SIZE 4
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#else
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# define FPU_REG_SIZE 1
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#endif
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# define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0)
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# define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1)
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# define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2)
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# define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3)
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# define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4)
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# define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5)
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# define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6)
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# define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7)
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# define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8)
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# define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9)
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# define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10)
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# define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11)
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# define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12)
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# define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13)
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# define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14)
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# define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15)
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# define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16)
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# define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17)
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# define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18)
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# define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19)
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# define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20)
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# define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21)
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# define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22)
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# define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23)
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# define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24)
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# define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25)
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# define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26)
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# define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27)
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# define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28)
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# define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29)
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# define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30)
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# define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31)
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# define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
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# define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
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#else
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# define FPU_XCPT_REGS 0
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#endif
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#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/* In assembly language, values have to be referenced as byte address
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@ -178,6 +230,42 @@
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# define REG_X30 (4*REG_X30_NDX)
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# define REG_X31 (4*REG_X31_NDX)
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# define REG_INT_CTX (4*REG_INT_CTX_NDX)
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#ifdef CONFIG_ARCH_FPU
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# define REG_F0 (4*REG_F0_NDX)
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# define REG_F1 (4*REG_F1_NDX)
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# define REG_F2 (4*REG_F2_NDX)
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# define REG_F3 (4*REG_F3_NDX)
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# define REG_F4 (4*REG_F4_NDX)
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# define REG_F5 (4*REG_F5_NDX)
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# define REG_F6 (4*REG_F6_NDX)
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# define REG_F7 (4*REG_F7_NDX)
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# define REG_F8 (4*REG_F8_NDX)
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# define REG_F9 (4*REG_F9_NDX)
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# define REG_F10 (4*REG_F10_NDX)
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# define REG_F11 (4*REG_F11_NDX)
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# define REG_F12 (4*REG_F12_NDX)
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# define REG_F13 (4*REG_F13_NDX)
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# define REG_F14 (4*REG_F14_NDX)
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# define REG_F15 (4*REG_F15_NDX)
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# define REG_F16 (4*REG_F16_NDX)
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# define REG_F17 (4*REG_F17_NDX)
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# define REG_F18 (4*REG_F18_NDX)
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# define REG_F19 (4*REG_F19_NDX)
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# define REG_F20 (4*REG_F20_NDX)
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# define REG_F21 (4*REG_F21_NDX)
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# define REG_F22 (4*REG_F22_NDX)
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# define REG_F23 (4*REG_F23_NDX)
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# define REG_F24 (4*REG_F24_NDX)
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# define REG_F25 (4*REG_F25_NDX)
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# define REG_F26 (4*REG_F26_NDX)
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# define REG_F27 (4*REG_F27_NDX)
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# define REG_F28 (4*REG_F28_NDX)
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# define REG_F29 (4*REG_F29_NDX)
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# define REG_F30 (4*REG_F30_NDX)
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# define REG_F31 (4*REG_F31_NDX)
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# define REG_FCSR (4*REG_FCSR_NDX)
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#endif
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#else
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# define REG_EPC REG_EPC_NDX
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# define REG_X1 REG_X1_NDX
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@ -212,6 +300,43 @@
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# define REG_X30 REG_X30_NDX
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# define REG_X31 REG_X31_NDX
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# define REG_INT_CTX REG_INT_CTX_NDX
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#ifdef CONFIG_ARCH_FPU
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# define REG_F0 REG_F0_NDX
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# define REG_F1 REG_F1_NDX
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# define REG_F2 REG_F2_NDX
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# define REG_F3 REG_F3_NDX
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# define REG_F4 REG_F4_NDX
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# define REG_F5 REG_F5_NDX
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# define REG_F6 REG_F6_NDX
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# define REG_F7 REG_F7_NDX
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# define REG_F8 REG_F8_NDX
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# define REG_F9 REG_F9_NDX
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# define REG_F10 REG_F10_NDX
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# define REG_F11 REG_F11_NDX
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# define REG_F12 REG_F12_NDX
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# define REG_F13 REG_F13_NDX
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# define REG_F14 REG_F14_NDX
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# define REG_F15 REG_F15_NDX
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# define REG_F16 REG_F16_NDX
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# define REG_F17 REG_F17_NDX
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# define REG_F18 REG_F18_NDX
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# define REG_F19 REG_F19_NDX
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# define REG_F20 REG_F20_NDX
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# define REG_F21 REG_F21_NDX
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# define REG_F22 REG_F22_NDX
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# define REG_F23 REG_F23_NDX
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# define REG_F24 REG_F24_NDX
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# define REG_F25 REG_F25_NDX
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# define REG_F26 REG_F26_NDX
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# define REG_F27 REG_F27_NDX
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# define REG_F28 REG_F28_NDX
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# define REG_F29 REG_F29_NDX
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# define REG_F30 REG_F30_NDX
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# define REG_F31 REG_F31_NDX
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# define REG_FCSR REG_FCSR_NDX
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#endif
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#endif
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/* Now define more user friendly alternative name that can be used either
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@ -193,6 +193,14 @@ void up_sigdeliver(void);
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int up_swint(int irq, FAR void *context, FAR void *arg);
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uint32_t up_get_newintctx(void);
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#ifdef CONFIG_ARCH_FPU
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void up_savefpu(uint32_t *regs);
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void up_restorefpu(const uint32_t *regs);
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#else
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# define up_savefpu(regs)
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# define up_restorefpu(regs)
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#endif
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/* Low level serial output **************************************************/
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void up_lowputc(char ch);
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236
arch/risc-v/src/rv32im/up_fpu.S
Normal file
236
arch/risc-v/src/rv32im/up_fpu.S
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@ -0,0 +1,236 @@
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/************************************************************************************
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* arch/risc-v/src/rv32im/up_fpu.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/rv32im/irq.h>
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#ifdef CONFIG_ARCH_FPU
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Public Symbols
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************************************************************************************/
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.globl up_fpuconfig
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.globl up_savefpu
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.globl up_restorefpu
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.file "up_fpu.S"
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#define FS_MASK 0x6000
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#define FS_OFF 0x0000
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#define FS_INITIAL 0x2000
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#define FS_CLEAN 0x4000
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#define FS_DIRTY 0x6000
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#if defined(CONFIG_ARCH_DPFPU)
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# define FLOAD fld
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# define FSTORE fsd
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#elif defined(CONFIG_ARCH_QPFPU)
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# define FLOAD flq
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# define FSTORE fsq
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#else
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# define FLOAD flw
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# define FSTORE fsw
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: up_fpuconfig
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*
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* Description:
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* init fpu
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*
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* C Function Prototype:
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* void up_fpuconfig(void);
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* This function does not return anything explicitly.
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*
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************************************************************************************/
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.type up_fpuconfig, function
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up_fpuconfig:
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li a0, FS_INITIAL
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csrs mstatus, a0
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csrwi fcsr, 0
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ret
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/************************************************************************************
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* Name: up_savefpu
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*
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* Description:
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* Given the pointer to a register save area (in A0), save the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void up_savefpu(uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area in which to save the floating point
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* registers
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.type up_savefpu, function
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up_savefpu:
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lw t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_DIRTY
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bne t2, t1, 1f
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li t1, ~FS_MASK
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and t0, t0, t1
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li t1, FS_CLEAN
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or t0, t0, t1
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sw t0, REG_INT_CTX(a0)
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/* Store all floating point registers */
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FSTORE f0, REG_F0(a0)
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FSTORE f1, REG_F1(a0)
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FSTORE f2, REG_F2(a0)
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FSTORE f3, REG_F3(a0)
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FSTORE f4, REG_F4(a0)
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FSTORE f5, REG_F5(a0)
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FSTORE f6, REG_F6(a0)
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FSTORE f7, REG_F7(a0)
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FSTORE f8, REG_F8(a0)
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FSTORE f9, REG_F9(a0)
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FSTORE f10, REG_F10(a0)
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FSTORE f11, REG_F11(a0)
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FSTORE f12, REG_F12(a0)
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FSTORE f13, REG_F13(a0)
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FSTORE f14, REG_F14(a0)
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FSTORE f15, REG_F15(a0)
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FSTORE f16, REG_F16(a0)
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FSTORE f17, REG_F17(a0)
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FSTORE f18, REG_F18(a0)
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FSTORE f19, REG_F19(a0)
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FSTORE f20, REG_F20(a0)
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FSTORE f21, REG_F21(a0)
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FSTORE f22, REG_F22(a0)
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FSTORE f23, REG_F23(a0)
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FSTORE f24, REG_F24(a0)
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FSTORE f25, REG_F25(a0)
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FSTORE f26, REG_F26(a0)
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FSTORE f27, REG_F27(a0)
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FSTORE f28, REG_F28(a0)
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FSTORE f29, REG_F29(a0)
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FSTORE f30, REG_F30(a0)
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FSTORE f31, REG_F31(a0)
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frcsr t0
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sw t0, REG_FCSR(a0)
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1:
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ret
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/************************************************************************************
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* Name: up_restorefpu
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*
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* Description:
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* Given the pointer to a register save area (in A0), restore the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void up_restorefpu(const uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area containing the floating point
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* registers.
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*
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* Returned Value:
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* This function does not return anything explicitly. However, it is called from
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* interrupt level assembly logic that assumes that r0 is preserved.
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*
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************************************************************************************/
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.type up_restorefpu, function
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up_restorefpu:
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lw t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_INITIAL
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ble t2, t1, 1f
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/* Load all floating point registers */
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FLOAD f0, REG_F0(a0)
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FLOAD f1, REG_F1(a0)
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FLOAD f2, REG_F2(a0)
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FLOAD f3, REG_F3(a0)
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FLOAD f4, REG_F4(a0)
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FLOAD f5, REG_F5(a0)
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FLOAD f6, REG_F6(a0)
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FLOAD f7, REG_F7(a0)
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FLOAD f8, REG_F8(a0)
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FLOAD f9, REG_F9(a0)
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FLOAD f10, REG_F10(a0)
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FLOAD f11, REG_F11(a0)
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FLOAD f12, REG_F12(a0)
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FLOAD f13, REG_F13(a0)
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FLOAD f14, REG_F14(a0)
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FLOAD f15, REG_F15(a0)
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FLOAD f16, REG_F16(a0)
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FLOAD f17, REG_F17(a0)
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FLOAD f18, REG_F18(a0)
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FLOAD f19, REG_F19(a0)
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FLOAD f20, REG_F20(a0)
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FLOAD f21, REG_F21(a0)
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FLOAD f22, REG_F22(a0)
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FLOAD f23, REG_F23(a0)
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FLOAD f24, REG_F24(a0)
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FLOAD f25, REG_F25(a0)
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FLOAD f26, REG_F26(a0)
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FLOAD f27, REG_F27(a0)
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FLOAD f28, REG_F28(a0)
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FLOAD f29, REG_F29(a0)
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FLOAD f30, REG_F30(a0)
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FLOAD f31, REG_F31(a0)
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/* Store the floating point control and status register */
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lw t0, REG_FCSR(a0)
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fscsr t0
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1:
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ret
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#endif /* CONFIG_ARCH_FPU */
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