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arm/armv8-m: indicating no low-overhead-loop predication by default

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Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2022-04-12 15:34:49 +08:00 committed by Xiang Xiao
parent ff210e1c2d
commit 0d7ea348d5
2 changed files with 7 additions and 6 deletions
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2
arch/arm/src/armv8-m/arm_initialstate.c
View File

@ -155,7 +155,7 @@ void up_initial_state(struct tcb_s *tcb)
#if !defined(CONFIG_ARMV8M_LAZYFPU) && defined(CONFIG_ARCH_FPU)
xcp->regs[REG_FPSCR] = 0; /* REVISIT: Initial FPSCR should be configurable */
xcp->regs[REG_FPSCR] |= ARMV8M_FPSCR_LTPSIZE_NONE;
xcp->regs[REG_FP_RESERVED] = 0;
#endif /* !CONFIG_ARMV8M_LAZYFPU && CONFIG_ARCH_FPU */

11
arch/arm/src/armv8-m/psr.h
View File

@ -89,11 +89,12 @@
#define ARMV8M_FPSCR_IDC (1 << 7) /* Bit 7: Input Denormal */
#define ARMV8M_FPSCR_LTPSIZE_SHIFT 16 /* Bits 16-18: Vector element size */
#define ARMV8M_FPSCR_LTPSIZE_8BIT (0x0 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_16BIT (0x1 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_32BIT (0x2 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_DONE (0x3 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_MASK (0x7 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_8BIT (0x0 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_16BIT (0x1 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_32BIT (0x2 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_64BIT (0x3 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_NONE (0x4 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_MASK (0x7 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
#define ARMV8M_FPSCR_FZ16 (1 << 19) /* Bit 19: Flush-to-zero mode(half-precision) */