i.MX6: Add CCM header file
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Gregory Nutt
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3b1812b50f
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0d7edfd370
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arch/arm/src/imx6/chip/imx_ccm.h
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arch/arm/src/imx6/chip/imx_ccm.h
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/************************************************************************************
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* arch/arm/src/imx6/imx_ccm.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference:
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* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
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* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H
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#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <chip/imx_memorymap.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* CCM Register Offsets *************************************************************/
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#define IMX_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */
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#define IMX_CCM_CCDR_OFFSET 0x0004 /* CCM Control Divider Register */
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#define IMX_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */
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#define IMX_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */
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#define IMX_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */
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#define IMX_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */
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#define IMX_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */
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#define IMX_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */
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#define IMX_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */
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#define IMX_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */
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#define IMX_CCM_CS1CDR_OFFSET 0x0028 /* CCM SSI1 Clock Divider Register */
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#define IMX_CCM_CS2CDR_OFFSET 0x002c /* CCM SSI2 Clock Divider Register */
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#define IMX_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */
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#define IMX_CCM_CHSCCDR_OFFSET 0x0034 /* CCM HSC Clock Divider Register */
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#define IMX_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */
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#define IMX_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */
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#define IMX_CCM_CWDR_OFFSET 0x0044 /* CCM Wakeup Detector Register */
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#define IMX_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */
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#define IMX_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */
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#define IMX_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */
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#define IMX_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */
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#define IMX_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */
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#define IMX_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */
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#define IMX_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */
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#define IMX_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */
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#define IMX_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */
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#define IMX_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */
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#define IMX_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */
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#define IMX_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */
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#define IMX_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */
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#define IMX_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */
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/* CCM Register Addresses ***********************************************************/
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#define IMX_CCM_CCR (IMX_CCM_VBASE+IMX_CCM_CCR_OFFSET)
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#define IMX_CCM_CCDR (IMX_CCM_VBASE+IMX_CCM_CCDR_OFFSET)
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#define IMX_CCM_CSR (IMX_CCM_VBASE+IMX_CCM_CSR_OFFSET)
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#define IMX_CCM_CCSR (IMX_CCM_VBASE+IMX_CCM_CCSR_OFFSET)
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#define IMX_CCM_CACRR (IMX_CCM_VBASE+IMX_CCM_CACRR_OFFSET)
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#define IMX_CCM_CBCDR (IMX_CCM_VBASE+IMX_CCM_CBCDR_OFFSET)
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#define IMX_CCM_CBCMR (IMX_CCM_VBASE+IMX_CCM_CBCMR_OFFSET)
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#define IMX_CCM_CSCMR1 (IMX_CCM_VBASE+IMX_CCM_CSCMR1_OFFSET)
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#define IMX_CCM_CSCMR2 (IMX_CCM_VBASE+IMX_CCM_CSCMR2_OFFSET)
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#define IMX_CCM_CSCDR1 (IMX_CCM_VBASE+IMX_CCM_CSCDR1_OFFSET)
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#define IMX_CCM_CS1CDR (IMX_CCM_VBASE+IMX_CCM_CS1CDR_OFFSET)
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#define IMX_CCM_CS2CDR (IMX_CCM_VBASE+IMX_CCM_CS2CDR_OFFSET)
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#define IMX_CCM_CDCDR (IMX_CCM_VBASE+IMX_CCM_CDCDR_OFFSET)
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#define IMX_CCM_CHSCCDR (IMX_CCM_VBASE+IMX_CCM_CHSCCDR_OFFSET)
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#define IMX_CCM_CSCDR2 (IMX_CCM_VBASE+IMX_CCM_CSCDR2_OFFSET)
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#define IMX_CCM_CSCDR3 (IMX_CCM_VBASE+IMX_CCM_CSCDR3_OFFSET)
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#define IMX_CCM_CWDR (IMX_CCM_VBASE+IMX_CCM_CWDR_OFFSET)
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#define IMX_CCM_CDHIPR (IMX_CCM_VBASE+IMX_CCM_CDHIPR_OFFSET)
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#define IMX_CCM_CLPCR (IMX_CCM_VBASE+IMX_CCM_CLPCR_OFFSET)
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#define IMX_CCM_CISR (IMX_CCM_VBASE+IMX_CCM_CISR_OFFSET)
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#define IMX_CCM_CIMR (IMX_CCM_VBASE+IMX_CCM_CIMR_OFFSET)
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#define IMX_CCM_CCOSR (IMX_CCM_VBASE+IMX_CCM_CCOSR_OFFSET)
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#define IMX_CCM_CGPR (IMX_CCM_VBASE+IMX_CCM_CGPR_OFFSET)
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#define IMX_CCM_CCGR0 (IMX_CCM_VBASE+IMX_CCM_CCGR0_OFFSET)
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#define IMX_CCM_CCGR1 (IMX_CCM_VBASE+IMX_CCM_CCGR1_OFFSET)
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#define IMX_CCM_CCGR2 (IMX_CCM_VBASE+IMX_CCM_CCGR2_OFFSET)
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#define IMX_CCM_CCGR3 (IMX_CCM_VBASE+IMX_CCM_CCGR3_OFFSET)
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#define IMX_CCM_CCGR4 (IMX_CCM_VBASE+IMX_CCM_CCGR4_OFFSET)
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#define IMX_CCM_CCGR5 (IMX_CCM_VBASE+IMX_CCM_CCGR5_OFFSET)
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#define IMX_CCM_CCGR6 (IMX_CCM_VBASE+IMX_CCM_CCGR6_OFFSET)
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#define IMX_CCM_CMEOR (IMX_CCM_VBASE+IMX_CCM_CMEOR_OFFSET)
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/* CCM Register Bit Definitions *****************************************************/
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/* CCM Control Register */
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#define CCM_CCR_
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/* CCM Control Divider Register */
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#define CCM_CCDR_
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/* CCM Status Register */
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#define CCM_CSR_
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/* CCM Clock Switcher Register */
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#define CCM_CCSR_
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/* CCM Arm Clock Root Register */
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#define CCM_CACRR_
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/* CCM Bus Clock Divider Register */
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#define CCM_CBCDR_
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/* CCM Bus Clock Multiplexer Register */
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#define CCM_CBCMR_
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/* CCM Serial Clock Multiplexer Register 1 */
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#define CCM_CSCMR1_
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/* CCM Serial Clock Multiplexer Register 2 */
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#define CCM_CSCMR2_
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/* CCM Serial Clock Divider Register 1 */
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#define CCM_CSCDR1_
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/* CCM SSI1 Clock Divider Register */
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#define CCM_CS1CDR_
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/* CCM SSI2 Clock Divider Register */
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#define CCM_CS2CDR_
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/* CCM D1 Clock Divider Register */
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#define CCM_CDCDR_
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/* CCM HSC Clock Divider Register */
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#define CCM_CHSCCDR_
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/* CCM Serial Clock Divider Register 2 */
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#define CCM_CSCDR2_
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/* CCM Serial Clock Divider Register 3 */
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#define CCM_CSCDR3_
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/* CCM Wakeup Detector Register */
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#define CCM_CWDR_
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/* CCM Divider Handshake In-Process Register */
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#define CCM_CDHIPR_
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/* CCM Low Power Control Register */
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#define CCM_CLPCR_
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/* CCM Interrupt Status Register */
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#define CCM_CISR_
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/* CCM Interrupt Mask Register */
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#define CCM_CIMR_
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/* CCM Clock Output Source Register */
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#define CCM_CCOSR_
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/* CCM General Purpose Register */
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#define CCM_CGPR_
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/* CCM Clock Gating Register 0 */
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#define CCM_CCGR0_
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/* CCM Clock Gating Register 1 */
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#define CCM_CCGR1_
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/* CCM Clock Gating Register 2 */
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#define CCM_CCGR2_
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/* CCM Clock Gating Register 3 */
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#define CCM_CCGR3_
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/* CCM Clock Gating Register 4 */
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#define CCM_CCGR4_
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/* CCM Clock Gating Register 5 */
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#define CCM_CCGR5_
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/* CCM Clock Gating Register 6 */
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#define CCM_CCGR6_
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/* CCM Module Enable Overide Register */
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#define CCM_CMEOR_
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#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H */
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