Evolving STM32 USB host support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5031 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/stm32/chip/stm32_otgfs.h

@@ -46,6 +46,12 @@
 /****************************************************************************************************
  * Pre-processor Definitions
  ****************************************************************************************************/
+/* General definitions */
+
+#define OTGFS_EPTYPE_CTRL               (0) /* Control */
+#define OTGFS_EPTYPE_ISOC               (1) /* Isochronous */
+#define OTGFS_EPTYPE_BULK               (2) /* Bulk */
+#define OTGFS_EPTYPE_INTR               (3) /* Interrupt */
 
 /* Register Offsets *********************************************************************************/
 /* Core global control and status registers */
@@ -125,8 +131,8 @@
 #define STM32_OTGFS_HCTSIZ3_OFFSET      0x0570 /* Host channel-3 interrupt register */
 #define STM32_OTGFS_HCTSIZ4_OFFSET      0x0590 /* Host channel-4 interrupt register */
 #define STM32_OTGFS_HCTSIZ5_OFFSET      0x05b0 /* Host channel-5 interrupt register */
-#define STM32_OTGFS_HCTSIZ6_OFFSET      0x05d9 /* Host channel-6 interrupt register */
-#define STM32_OTGFS_HCTSIZ7_OFFSET      0x05f9 /* Host channel-7 interrupt register */
+#define STM32_OTGFS_HCTSIZ6_OFFSET      0x05d0 /* Host channel-6 interrupt register */
+#define STM32_OTGFS_HCTSIZ7_OFFSET      0x05f0 /* Host channel-7 interrupt register */
 
 /* Device-mode control and status registers */
 
@@ -559,7 +565,7 @@
 #  define OTGFS_HNPTXSTS_EPNUM_SHIFT    (27)      /* Bits 27-30: Endpoint number */
 #  define OTGFS_HNPTXSTS_EPNUM_MASK     (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
                                                   /* Bit 31 Reserved, must be kept at reset value */
-/* general core configuration register */
+/* General core configuration register */
                                                   /* Bits 15:0 Reserved, must be kept at reset value */
 #define OTGFS_GCCFG_PWRDWN              (1 << 16) /* Bit 16: Power down */
                                                   /* Bit 17 Reserved, must be kept at reset value */
@@ -695,7 +701,7 @@
 #define OTGFS_HCINT_STALL               (1 << 3)  /* Bit 3:  STALL response received interrupt */
 #define OTGFS_HCINT_NAK                 (1 << 4)  /* Bit 4:  NAK response received interrupt */
 #define OTGFS_HCINT_ACK                 (1 << 5)  /* Bit 5:  ACK response received/transmitted interrupt */
-#define OTGFS_HCINTMSK_NYET             (1 << 6)  /* Bit 6:  response received interrupt mask */
+#define OTGFS_HCINT_NYET                (1 << 6)  /* Bit 6:  Response received interrupt */
 #define OTGFS_HCINT_TXERR               (1 << 7)  /* Bit 7:  Transaction error */
 #define OTGFS_HCINT_BBERR               (1 << 8)  /* Bit 8:  Babble error */
 #define OTGFS_HCINT_FRMOR               (1 << 9)  /* Bit 9:  Frame overrun */

arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h

@@ -365,7 +365,7 @@
 #define GPIO_JTMS_SWDIO       (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
 #define GPIO_JTRST            (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
 
-/* OTG FS/HS */
+/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */
 
 #define GPIO_OTGFS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
 #define GPIO_OTGFS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)

arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h

@@ -365,7 +365,7 @@
 #define GPIO_JTMS_SWDIO       (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
 #define GPIO_JTRST            (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
 
-/* OTG FS/HS */
+/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */
 
 #define GPIO_OTGFS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
 #define GPIO_OTGFS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)

arch/arm/src/stm32/stm32_otgfsdev.c

@@ -4086,7 +4086,7 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
  *
  *******************************************************************************/
 
-#ifdef CONFIG_LPC313x_USBDEV_DMA
+#ifdef CONFIG_STM32_USBDEV_DMA
 static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
 {
   usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
@@ -4645,7 +4645,6 @@ static int stm32_wakeup(struct usbdev_s *dev)
           regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK);
           stm32_putreg(regval, STM32_OTGFS_PCGCCTL);
 #endif
-
           /* Activate Remote wakeup signaling */
 
           regval  = stm32_getreg(STM32_OTGFS_DCTL);
@@ -4971,7 +4970,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
 #ifndef CONFIG_USBDEV_VBUSSENSING
   regval |= OTGFS_GCCFG_NOVBUSSENS;
 #endif
-#ifdef CONFIG_USBDEV_SOFOUTPUT
+#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT
   regval |= OTGFS_GCCFG_SOFOUTEN;
 #endif
   stm32_putreg(regval, STM32_OTGFS_GCCFG);
@@ -5173,12 +5172,29 @@ void up_usbinitialize(void)
    *    current detection.
    */
 
-  /* Configure OTG FS alternate function pins */
+  /* Configure OTG FS alternate function pins
+   *
+   * PIN* SIGNAL      DIRECTION
+   * ---- ----------- ----------
+   * PA8  OTG_FS_SOF  SOF clock output
+   * PA9  OTG_FS_VBUS VBUS input for device, Driven by external regulator by
+   *                  host (not an alternate function)
+   * PA10 OTG_FS_ID   OTG ID pin (only needed in Dual mode)
+   * PA11 OTG_FS_DM   D- I/O
+   * PA12 OTG_FS_DP   D+ I/O
+   *
+   * *Pins may vary from device-to-device.
+   */
 
   stm32_configgpio(GPIO_OTGFS_DM);
   stm32_configgpio(GPIO_OTGFS_DP);
-  stm32_configgpio(GPIO_OTGFS_ID);
+  stm32_configgpio(GPIO_OTGFS_ID);    /* Only needed for OTG */
+
+  /* SOF output pin configuration is configurable. */
+
+#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT
   stm32_configgpio(GPIO_OTGFS_SOF);
+#endif
 
   /* Uninitialize the hardware so that we know that we are starting from a
    * known state. */