From 0ddcbe62ec08e2f93b13753074ac19421c464423 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 16 Jul 2024 16:38:41 +0800 Subject: [PATCH] arch/risc-v: does not clear IPI address in S mode According to the riscv-aclint doc, writing 0 to SSWI address has no effect. Remove this unnecessary write for S mode. Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Inochi Amaoto --- arch/risc-v/src/common/riscv_ipi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_ipi.h b/arch/risc-v/src/common/riscv_ipi.h index 1b2b649f3b..8c3989d7ee 100644 --- a/arch/risc-v/src/common/riscv_ipi.h +++ b/arch/risc-v/src/common/riscv_ipi.h @@ -45,7 +45,7 @@ static inline void riscv_ipi_send(int cpu) static inline void riscv_ipi_clear(int cpu) { -#if defined(RISCV_IPI) +#if defined(RISCV_IPI) && !defined(CONFIG_ARCH_USE_S_MODE) putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu)); #endif CLEAR_CSR(CSR_IP, IP_SIP);