sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #77)

Browse Source 
Upstream_nucleo 144
This commit is contained in:
Gregory Nutt 2016-06-28 09:07:03 -06:00
commit 0de3514af7
19 changed files with 4649 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/src/common/up_checkstack.c
View File

@ -84,6 +84,10 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
FAR uint32_t *ptr;
size_t mark;
if (size == 0)
{
return 0;
}
/* Get aligned addresses of the top and bottom of the stack */
#ifdef CONFIG_TLS
/* Skip over the TLS data structure at the bottom of the stack */

61
arch/arm/src/stm32f7/Kconfig
View File

@ -1195,6 +1195,10 @@ config STM32F7_QUADSPI
bool "QuadSPI"
default n
config STM32F7_PWR
bool "PWR"
default n
config STM32F7_RNG
bool "RNG"
default n
@ -1794,6 +1798,63 @@ config SDMMC2_WIDTH_D1_ONLY
endmenu # "SDMMC2 Configuration"
if STM32F7_BKPSRAM
config STM32F7_BBSRAM
bool "BBSRAM File Support"
default n
config STM32F7_BBSRAM_FILES
int "Max Files to support in BBSRAM"
default 4
config STM32F7_SAVE_CRASHDUMP
bool "Enable Saving Panic to BBSRAM"
default n
endif # STM32F7_BKPSRAM
config STM32F7_HAVE_RTC_COUNTER
bool
default n
config STM32F7_HAVE_RTC_SUBSECONDS
bool
default n
config RTC_MAGIC_REG
int "The BKP register used to store/check the Magic value to determine if RTC is set already"
default 0
range 0 31
depends on RTC && !STM32F7_HAVE_RTC_COUNTER
config RTC_MAGIC
hex "Value used as Magic to determine if RTC is set already"
default 0xfacefeee
depends on RTC && !STM32F7_HAVE_RTC_COUNTER
choice
prompt "RTC clock source"
default STM32F7_RTC_LSECLOCK
depends on RTC
config STM32F7_RTC_HSECLOCK
bool "HSE clock"
---help---
Drive the RTC with the HSE clock, divided down to 1MHz.
config STM32F7_RTC_LSECLOCK
bool "LSE clock"
---help---
Drive the RTC with the LSE clock
config STM32F7_RTC_LSICLOCK
bool "LSI clock"
---help---
Drive the RTC with the LSI clock
endchoice #"RTC clock source"
config STM32F7_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration"
default n

18
arch/arm/src/stm32f7/Make.defs
View File

@ -135,8 +135,18 @@ ifeq ($(CONFIG_STM32F7_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_exti_pwr.c
ifeq ($(CONFIG_STM32F7_PWR),y)
CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c
endif
ifeq ($(CONFIG_RTC),y)
CHIP_CSRCS += stm32_rtc.c
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
endif
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += stm32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_STM32F7_I2C),y)
@ -180,3 +190,7 @@ endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif
ifeq ($(CONFIG_STM32F7_BBSRAM),y)
CHIP_CSRCS += stm32_bbsram.c
endif

405
arch/arm/src/stm32f7/chip/stm32_rtcc.h Normal file
View File

@ -0,0 +1,405 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_rtcc.h.h
*
* Copyright (C) 2011-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */
#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
/* Register Addresses ***************************************************************/
#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET)
#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET)
#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET)
#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET)
#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET)
#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET)
#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET)
#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET)
#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET)
#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET)
#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n))
#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET)
#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET)
#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET)
#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET)
#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET)
#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET)
#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET)
#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET)
#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET)
#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET)
#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET)
#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET)
#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET)
#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET)
#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET)
#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET)
#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET)
#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET)
#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
#define STM32_RTC_BKCOUNT 32
/* Register Bitfield Definitions ****************************************************/
/* RTC time register */
#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT)
#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT)
#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
#define RTC_TR_RESERVED_BITS (0xff808080)
/* RTC date register */
#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT)
#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT)
#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
#define RTC_DR_RESERVED_BITS (0xff0000c0)
/* RTC control register */
#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT)
# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
#define RTC_CR_COSEL (1 << 19) /* Bit 19 : Calibration output selection */
#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT)
# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
/* RTC initialization and status register */
#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */
#define RTC_ISR_ITSF (1 << 17) /* Bit 17:Internal tTime-stamp flagg */
#define RTC_ISR_ALLFLAGS (0x0003ffff)
/* RTC prescaler register */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
/* RTC wakeup timer register */
#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */
/* RTC alarm A/B registers */
#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT)
#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT)
#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */
#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT)
#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT)
#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */
#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT)
#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */
#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */
#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT)
#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT)
#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */
/* RTC write protection register */
#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */
/* RTC sub second register */
#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC shift control register */
#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
#define RTC_SHIFTR_SUBFS_MASK (0x7ffff << RTC_SHIFTR_SUBFS_SHIFT)
#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
/* RTC time stamp time register */
#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT)
#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT)
#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT)
#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT)
#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT)
#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT)
#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
/* RTC time stamp date register */
#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */
#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT)
#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT)
#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT)
/* RTC timestamp sub second register */
#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC calibration register */
#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
/* RTC tamper configuration register */
#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */
#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */
#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: RTC_TAMP2 input detection enable */
#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for RTC_TAMP2 input */
#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV8192 (2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV4096 (3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV2048 (4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT)
#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
#define RTC_TAMPCR_TAMPPRCH_MASK (3 << RTC_TAMPCR_TAMPPRCH_SHIFT)
# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */
#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */
#define RTC_TAMPCR_TAMP1MF (1 << 18) /* Bit 18: Tamper 1 mask flag */
#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: Tamper 2 interrupt enable */
#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: Tamper 2 no erase */
#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: Tamper 2 mask flag */
#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: Tamper 3 interrupt enable */
#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: Tamper 3 no erase */
#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: Tamper 3 mask flag */
/* RTC alarm A/B sub second register */
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
/* RTC option register */
#define RTC_OR_TSINSEL_SHIFT (1) /* Bits 1-2: TIMESTAMP mapping */
#define RTC_OR_TSINSEL_MASK (3 << RTC_OR_TSINSEL_SHIFT)
# define RTC_OR_PC13 (0 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC13*/
# define RTC_OR_PI8 (1 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PI8 */
# define RTC_OR_PC1 (2 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
# define RTC_OR_PC1_1 (3 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
#define RTC_OR_RTC_ALARM_TYPE (1 << 3) /* RTC_ALARM on PC13 output type */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H */

112
arch/arm/src/stm32f7/stm32_alarm.h Normal file
View File

@ -0,0 +1,112 @@
/****************************************************************************
* arch/arm/src/include/stm32f7/stm32_alarm.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Neil hancock - delegated to Gregory Nutt Mar 30, 2016
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H
#define __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <time.h>
#ifdef CONFIG_RTC_ALARM
/****************************************************************************
* Public Types
****************************************************************************/
typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid);
/* These features map to STM32 RTC from stm32F7xx
*/
enum alm_id_e
{
RTC_ALARMA = 0, /* RTC ALARM A */
RTC_ALARMB, /* RTC ALARM B */
RTC_ALARM_LAST
};
/* Structure used to pass parameters to set an alarm */
struct alm_setalarm_s
{
int as_id; /* enum alm_id_e */
struct tm as_time; /* Alarm expiration time */
alm_callback_t as_cb; /* Callback (if non-NULL) */
FAR void *as_arg; /* Argument for callback */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_setalarm
*
* Description:
* Set an alarm to an absolute time using associated hardware.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo);
/****************************************************************************
* Name: stm32_rtc_cancelalarm
*
* Description:
* Cancel an alarm.
*
* Input Parameters:
* alarmid - Identifies the alarm to be cancelled
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_cancelalarm(enum alm_id_e alarmid);
#endif /* CONFIG_RTC_ALARM */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H */

884
arch/arm/src/stm32f7/stm32_bbsram.c Normal file
View File

@ -0,0 +1,884 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_bbsram.c
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This will driver create a set of files in the STM32's Battery backed up
* SRAM. That can be used to store data retained across power cycles.
*
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <poll.h>
#include <errno.h>
#include <unistd.h>
#include <time.h>
#include <nuttx/fs/fs.h>
#include <crc32.h>
#include "stm32_bbsram.h"
#include "chip.h"
#include "stm32_pwr.h"
#include "stm32_rtc.h"
#ifdef CONFIG_STM32F7_BBSRAM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32F7_BKPSRAM)
#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled
#endif
#define MAX_OPENCNT (255) /* Limit of uint8_t */
#ifndef CONFIG_DEBUG_INFO
# undef CONFIG_BBSRAM_DEBUG
#endif
#if defined(CONFIG_BBSRAM_DEBUG)
# define BBSRAM_DEBUG_READ() stm32_bbsram_rd()
# define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s)
#else
# define BBSRAM_DEBUG_READ()
# define BBSRAM_DUMP(p,s)
#endif
#define BBSRAM_HEADER_SIZE (sizeof(struct bbsramfh_s))
#define BBSRAM_CRCED_OFFSET (sizeof(((struct bbsramfh_s *)0)->crc))
#define BBSRAM_CRCED_SIZE(l) (BBSRAM_HEADER_SIZE-(BBSRAM_CRCED_OFFSET)+(l))
#define BBSRAM_ALIGNMENT (sizeof(((struct bbsramfh_s *)0)->crc))
#define BBSRAM_ALIGNMENT_MASK (BBSRAM_ALIGNMENT-1)
/****************************************************************************
* Private Types
****************************************************************************/
/* File Header */
struct bbsramfh_s
{
uint32_t crc; /* CRC calculated over data and this struct
* starting at fileno */
uint8_t fileno; /* The minor number */
uint8_t dirty; /* Data has been written to the file */
uint16_t len; /* Total Bytes in this file */
struct timespec lastwrite; /* Last write time */
uint8_t data[]; /* Data in the file */
};
struct stm32_bbsram_s
{
sem_t exclsem; /* For atomic accesses to this structure */
uint8_t refs; /* Number of references */
FAR struct bbsramfh_s *bbf; /* File in bbram */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int stm32_bbsram_open(FAR struct file *filep);
static int stm32_bbsram_close(FAR struct file *filep);
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset,
int whence);
static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer,
size_t len);
static ssize_t stm32_bbsram_write(FAR struct file *filep,
FAR const char *buffer, size_t len);
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
unsigned long arg);
#ifndef CONFIG_DISABLE_POLL
static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup);
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
static int stm32_bbsram_unlink(FAR struct inode *inode);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_BBSRAM_DEBUG)
static uint8_t debug[STM32F7_BBSRAM_SIZE];
#endif
static const struct file_operations stm32_bbsram_fops =
{
.open = stm32_bbsram_open,
.close = stm32_bbsram_close,
.read = stm32_bbsram_read,
.write = stm32_bbsram_write,
.seek = stm32_bbsram_seek,
.ioctl = stm32_bbsram_ioctl,
#ifndef CONFIG_DISABLE_POLL
.poll = stm32_bbsram_poll,
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
.unlink = stm32_bbsram_unlink,
#endif
};
static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bbsram_rd
****************************************************************************/
#if defined(CONFIG_BBSRAM_DEBUG)
static void stm32_bbsram_rd(void)
{
memcpy(&debug, (uint8_t *)STM32_BKPSRAM_BASE, sizeof debug);
}
#endif
/****************************************************************************
* Name: stm32_bbsram_rd
****************************************************************************/
#if defined(CONFIG_BBSRAM_DEBUG)
static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op)
{
BBSRAM_DEBUG_READ();
_info("%s:\n", op);
_info(" File Address:0x%8x\n", bbf);
_info(" crc:0x%8x\n", bbf->crc);
_info(" fileno:%d\n", (int) bbf->fileno);
_info(" dirty:%d\n", (int) bbf->dirty);
_info(" length:%d\n", (int) bbf->len);
_info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec);
_info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n",
bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]);
}
#endif
/************************************************************************************
* Name: stm32_bbsram_semgive
************************************************************************************/
static void stm32_bbsram_semgive(FAR struct stm32_bbsram_s *priv)
{
sem_post(&priv->exclsem);
}
/************************************************************************************
* Name: stm32_bbsram_semtake
*
* Description:
* Take a semaphore handling any exceptional conditions
*
* Input Parameters:
* priv - A reference to the CAN peripheral state
*
* Returned Value:
* None
*
****************************************************************************/
static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
{
int ret;
/* Wait until we successfully get the semaphore. EINTR is the only
* expected 'failure' (meaning that the wait for the semaphore was
* interrupted by a signal.
*/
do
{
ret = sem_wait(&priv->exclsem);
DEBUGASSERT(ret == 0 || errno == EINTR);
}
while (ret < 0);
}
/****************************************************************************
* Name: stm32_bbsram_ulock
*
* Description:
* Unprotects RTC registers, RTC backup data registers and backup SRAM
* against parasitic write access
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void stm32_bbsram_unlock(void)
{
(void)stm32_pwr_enablebkp(true);
}
/****************************************************************************
* Name: stm32_bbsram_lock
*
* Description:
* Protects RTC registers, RTC backup data registers and backup SRAM
* against parasitic write access
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void stm32_bbsram_lock(void)
{
(void)stm32_pwr_enablebkp(false);
}
/****************************************************************************
* Name: stm32_bbsram_crc
*
* Description:
* Calculates the CRC of the block
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static uint32_t stm32_bbsram_crc(FAR struct bbsramfh_s *pf)
{
return crc32((uint8_t *)pf + BBSRAM_CRCED_OFFSET, BBSRAM_CRCED_SIZE(pf->len));
}
/****************************************************************************
* Name: stm32_bbsram_open
*
* Description: Open the device
*
****************************************************************************/
static int stm32_bbsram_open(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
/* Increment the reference count */
stm32_bbsram_semtake(bbr);
if (bbr->refs == MAX_OPENCNT)
{
return -EMFILE;
}
else
{
bbr->refs++;
}
stm32_bbsram_semgive(bbr);
return OK;
}
/****************************************************************************
* Name: stm32_bbsram_internal_close
*
* Description:
* Close BBSRAM entry; Recalculate the time and crc
*
****************************************************************************/
static int stm32_bbsram_internal_close(FAR struct bbsramfh_s *bbf)
{
bbf->dirty = 0;
(void)clock_gettime(CLOCK_REALTIME, &bbf->lastwrite);
bbf->crc = stm32_bbsram_crc(bbf);
BBSRAM_DUMP(bbf, "close done");
return bbf->len;
}
/****************************************************************************
* Name: stm32_bbsram_close
*
* Description: close the device
*
****************************************************************************/
static int stm32_bbsram_close(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
int ret = OK;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
stm32_bbsram_semtake(bbr);
BBSRAM_DUMP(bbr->bbf, "close");
if (bbr->refs == 0)
{
ret = -EIO;
}
else
{
bbr->refs--;
if (bbr->refs == 0)
{
if (bbr->bbf->dirty)
{
/* Recalculate the time and crc */
stm32_bbsram_unlock();
stm32_bbsram_internal_close(bbr->bbf);
stm32_bbsram_lock();
}
}
}
stm32_bbsram_semgive(bbr);
return ret;
}
/****************************************************************************
* Name: stm32_bbsram_seek
****************************************************************************/
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset,
int whence)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
off_t newpos;
int ret;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
stm32_bbsram_semtake(bbr);
/* Determine the new, requested file position */
switch (whence)
{
case SEEK_CUR:
newpos = filep->f_pos + offset;
break;
case SEEK_SET:
newpos = offset;
break;
case SEEK_END:
newpos = bbr->bbf->len + offset;
break;
default:
/* Return EINVAL if the whence argument is invalid */
stm32_bbsram_semgive(bbr);
return -EINVAL;
}
/* Opengroup.org:
*
* "The lseek() function shall allow the file offset to be set beyond the end
* of the existing data in the file. If data is later written at this point,
* subsequent reads of data in the gap shall return bytes with the value 0
* until data is actually written into the gap."
*
* We can conform to the first part, but not the second. But return EINVAL if
*
* "...the resulting file offset would be negative for a regular file, block
* special file, or directory."
*/
if (newpos >= 0)
{
filep->f_pos = newpos;
ret = newpos;
}
else
{
ret = -EINVAL;
}
stm32_bbsram_semgive(bbr);
return ret;
}
/****************************************************************************
* Name: stm32_bbsram_read
****************************************************************************/
static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer,
size_t len)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
stm32_bbsram_semtake(bbr);
/* Trim len if read would go beyond end of device */
if ((filep->f_pos + len) > bbr->bbf->len)
{
len = bbr->bbf->len - filep->f_pos;
}
memcpy(buffer, &bbr->bbf->data[filep->f_pos], len);
filep->f_pos += len;
stm32_bbsram_semgive(bbr);
return len;
}
/****************************************************************************
* Name: stm32_bbsram_internal_write
****************************************************************************/
static ssize_t stm32_bbsram_internal_write(FAR struct bbsramfh_s *bbf,
FAR const char *buffer,
off_t offset, size_t len)
{
bbf->dirty = 1;
memcpy(&bbf->data[offset], buffer, len);
return len;
}
/****************************************************************************
* Name: stm32_bbsram_write
****************************************************************************/
static ssize_t stm32_bbsram_write(FAR struct file *filep, FAR const char *buffer,
size_t len)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
int ret = -EFBIG;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
/* Forbid writes past the end of the device */
if (filep->f_pos < bbr->bbf->len)
{
/* Clamp len to avoid crossing the end of the memory */
if ((filep->f_pos + len) > bbr->bbf->len)
{
len = bbr->bbf->len - filep->f_pos;
}
ret = len; /* save number of bytes written */
stm32_bbsram_semtake(bbr);
BBSRAM_DUMP(bbr->bbf, "write");
stm32_bbsram_unlock();
stm32_bbsram_internal_write(bbr->bbf, buffer, filep->f_pos, len);
stm32_bbsram_lock();
filep->f_pos += len;
BBSRAM_DUMP(bbr->bbf, "write done");
stm32_bbsram_semgive(bbr);
}
BBSRAM_DEBUG_READ();
return ret;
}
/****************************************************************************
* Name: stm32_bbsram_poll
****************************************************************************/
#ifndef CONFIG_DISABLE_POLL
static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup)
{
if (setup)
{
fds->revents |= (fds->events & (POLLIN | POLLOUT));
if (fds->revents != 0)
{
sem_post(fds->sem);
}
}
return OK;
}
#endif
/****************************************************************************
* Name: stm32_bbsram_ioctl
*
* Description: Return device geometry
*
****************************************************************************/
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR struct stm32_bbsram_s *bbr;
int ret = -ENOTTY;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL)
{
FAR struct bbsramd_s *bbrr = (FAR struct bbsramd_s *)((uintptr_t)arg);
stm32_bbsram_semtake(bbr);
if (!bbrr)
{
ret = -EINVAL;
}
else
{
bbrr->fileno = bbr->bbf->fileno;
bbrr->lastwrite = bbr->bbf->lastwrite;
bbrr->len = bbr->bbf->len;
bbrr->flags = (bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) ? eCRCValid : 0;
bbrr->flags = (bbr->bbf->dirty) ? eDirty : 0;
ret = OK;
}
stm32_bbsram_semgive(bbr);
}
return ret;
}
/****************************************************************************
* Name: stm32_bbsram_unlink
*
* Description:
* This function will remove the remove the file from the file system
* it will zero the contents and time stamp. It will leave the fileno
* and pointer to the BBSRAM intact.
* It should be called called on the the file used for the crash dump
* to remove it from visibility in the file system after it is created or
* read thus arming it.
*
****************************************************************************/
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
static int stm32_bbsram_unlink(FAR struct inode *inode)
{
FAR struct stm32_bbsram_s *bbr;
DEBUGASSERT(inode && inode->i_private);
bbr = (FAR struct stm32_bbsram_s *)inode->i_private;
stm32_bbsram_semtake(bbr);
stm32_bbsram_unlock();
memset(bbr->bbf->data, 0, bbr->bbf->len);
bbr->bbf->lastwrite.tv_nsec = 0;
bbr->bbf->lastwrite.tv_sec = 0;
bbr->bbf->crc = stm32_bbsram_crc(bbr->bbf);
stm32_bbsram_lock();
bbr->refs = 0;
stm32_bbsram_semgive(bbr);
sem_destroy(&bbr->exclsem);
return 0;
}
#endif
/****************************************************************************
* Name: stm32_bbsram_probe
*
* Description: Based on the number of files defined and their sizes
* Initializes the base pointers to the file entries.
*
****************************************************************************/
static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
{
int i;
int avail = STM32F7_BBSRAM_SIZE;
int alloc;
int size;
int ret = -EFBIG;
struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE;
for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); i++)
{
/* Validate the actual allocations against what is in the BBSRAM */
size = ent[i];
/* Use all that is left */
if (size == -1)
{
size = avail - (BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK);
}
/* Add in header size and keep aligned */
alloc = size + BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK;
alloc &= ~(BBSRAM_ALIGNMENT_MASK);
/* Does it fit? */
if (alloc <= avail)
{
ret = i + 1;
BBSRAM_DUMP(pf, "probe");
if (pf->len != size ||
pf->fileno != i ||
pf->crc != stm32_bbsram_crc(pf))
{
/* Not Valid so wipe the file in BBSRAM */
memset((uint8_t *)pf, 0, alloc);
pf->fileno = i;
pf->len = size;
pf->crc = stm32_bbsram_crc(pf);
BBSRAM_DUMP(pf, "probe reset");
}
pdev[i].bbf = pf;
pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc);
sem_init(&g_bbsram[i].exclsem, 0, 1);
}
avail -= alloc;
}
BBSRAM_DEBUG_READ();
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_bbsraminitialize
*
* Description:
* Initialize the Battery Backed up SRAM driver.
*
* Parameters:
* devpath - the path to instantiate the files.
* sizes - Pointer to a any array of file sizes to create
* the last entry should be 0
* A size of -1 will use all the remaining spaces
*
* If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES
* CONFIG_STM32_BBSRAM_FILES will be returned.
*
* Returned Value:
* Number of files created on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
int stm32_bbsraminitialize(char *devpath, int *sizes)
{
int i;
int fcnt;
char path[32];
char devname[32];
int ret = OK;
if (devpath == NULL)
{
return -EINVAL;
}
i = strlen(devpath);
if (i == 0 || i > sizeof(path) + 3)
{
return -EINVAL;
}
memset(g_bbsram, 0, sizeof(g_bbsram));
/* Clocking for the PWR block must be provided. However, this is done
* unconditionally in stm32f40xxx_rcc.c on power up. This done
* unconditionally because the PWR block is also needed to set the
* internal voltage regulator for maximum performance.
*/
/* Enable backup SRAM clock is done in rcc_enableahb1() when
* CONFIG_STM32_BKPSRAM is defined.
*/
/* Allow Access */
stm32_bbsram_unlock();
/* Enable backup regulator so that the data is retained in Standby and
* VBAT modes
*/
stm32_pwr_enablebreg(true);
fcnt = stm32_bbsram_probe(sizes, g_bbsram);
strncpy(path, devpath, sizeof(path));
strcat(path, "%d");
for (i = 0; i < fcnt && ret >= OK; i++)
{
snprintf(devname, sizeof(devname), path, i);
ret = register_driver(devname, &stm32_bbsram_fops, 0666, &g_bbsram[i]);
}
/* Disallow Access */
stm32_bbsram_lock();
return ret < OK ? ret : fcnt;
}
/****************************************************************************
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)
{
FAR struct bbsramfh_s *bbf;
int fill;
int ret = -ENOSPC;
/* On a bad day we could panic while panicking, (and we debug assert)
* this is a potential feeble attempt at only writing the first
* panic's context to the file
*/
static bool once = false;
if (!once)
{
once = true;
DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES);
bbf = g_bbsram[fileno].bbf;
DEBUGASSERT(bbf);
/* If the g_bbsram has been nulled out we return ENXIO.
*
* As once ensures we will keep the first dump. Checking the time for
* 0 protects from over writing a previous crash dump that has not
* been saved to long term storage and erased. The dreaded reboot
* loop.
*/
if (!bbf)
{
ret = -ENXIO;
}
else if ((bbf->lastwrite.tv_sec == 0 && bbf->lastwrite.tv_nsec == 0))
{
/* Clamp length if too big */
if (length > bbf->len)
{
length = bbf->len;
}
stm32_bbsram_unlock();
stm32_bbsram_internal_write(bbf, (char *) context, 0, length);
/* Fill with 0 if data is less then file size */
fill = (int) bbf->len - length;
if (fill > 0)
{
memset(&bbf->data[length], 0, fill);
}
/* Seal the file */
stm32_bbsram_internal_close(bbf);
stm32_bbsram_lock();
ret = length;
}
}
return ret;
}
#endif
#endif /* CONFIG_BBSRAM_DRIVER */

166
arch/arm/src/stm32f7/stm32_bbsram.h Normal file
View File

@ -0,0 +1,166 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_bbsram.h
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H
#define __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H
/****************************************************************************
* The purpose of this driver is to add battery backup file to the file
* system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined.
* These files are of fixed size up to the maximum of the backing 4K SRAM.
*
* If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature
* to save the context of a PANIC in one of these files.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/fs/ioctl.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
# define STM32F7_BBSRAM_SIZE 4096
#else
# error "No backup SRAM on this STM32 Device"
#endif
#if !defined(CONFIG_STM32F7_BBSRAM_FILES)
# define CONFIG_STM32F7_BBSRAM_FILES 4
#endif
/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique
* value among all over _DIOC() values?
*/
#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
enum bbsramdf_e
{
eCRCValid = 1, /* The crc is valid */
eDirty = 2, /* The file was closed */
};
struct bbsramd_s
{
uint8_t flags; /* The crc is valid and the file was closed */
uint8_t fileno; /* The minor number */
uint16_t len; /* Total Bytes in this file*/
struct timespec lastwrite; /* Last write time */
};
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
# define EXTERN extern "C"
extern "C"
{
#else
# define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Function: stm32_bbsraminitialize
*
* Description:
* Initialize the Battery Backed up SRAM driver.
*
* Parameters:
* devpath - the path to instantiate the files.
* sizes - Pointer to a any array of file sizes to create
* the last entry should be 0
* A size of -1 will use all the remaining spaces
*
* If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES
* CONFIG_STM32F7_BBSRAM_FILES will be returned.
*
* Returned Value:
* Number of files created on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
int stm32_bbsraminitialize(char *devpath, int *sizes);
/****************************************************************************
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H */

72
arch/arm/src/stm32f7/stm32_exti_pwr.h Normal file
View File

@ -0,0 +1,72 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_exti_pwr.h
*
* Copyright (C) 2015 Haltian Ltd. All rights reserved.
* Authors: Dmitry Nikolaev <dmitry.nikolaev@haltian.com>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H
#define __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdbool.h>
#include <nuttx/irq.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_exti_pvd
*
* Description:
* Sets/clears EXTI PVD interrupt.
*
* Parameters:
* - rising/falling edge: enables interrupt on rising/falling edge
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returns:
* The previous value of the interrupt handler function pointer. This
* value may, for example, be used to restore the previous handler when
* multiple handlers are used.
*
****************************************************************************/
xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event,
xcpt_t func);
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H */

264
arch/arm/src/stm32f7/stm32_pwr.c Normal file
View File

@ -0,0 +1,264 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include "up_arch.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32F7_PWR)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
static inline uint16_t stm32_pwr_getreg(uint8_t offset)
{
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
{
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
{
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits);
}
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
************************************************************************************/
bool stm32_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
waswritable = ((regval & PWR_CR1_DBP) != 0);
/* Enable or disable the ability to write */
if (waswritable && !writable)
{
/* Disable backup domain access */
regval &= ~PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/************************************************************************************
* Name: stm32_pwr_enablebreg
*
* Description:
* Enables the Backup regulator, the Backup regulator (used to maintain backup
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
* regulator is switched off. The backup SRAM can still be used but its content will
* be lost in the Standby and VBAT modes. Once set, the application must wait that
* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
* into the RAM will be maintained in the Standby and VBAT modes.
*
* Input Parameters:
* regon - state to set it to
*
* Returned Values:
* None
*
************************************************************************************/
void stm32_pwr_enablebreg(bool regon)
{
uint16_t regval;
regval = stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET);
regval &= ~PWR_CSR1_BRE;
regval |= regon ? PWR_CSR1_BRE : 0;
stm32_pwr_putreg(STM32_PWR_CSR1_OFFSET, regval);
if (regon)
{
while ((stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET) & PWR_CSR1_BRR) == 0);
}
}
/************************************************************************************
* Name: stm32_pwr_setvos
*
* Description:
* Set voltage scaling.
*
* Input Parameters:
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
*
* Returned Values:
* None
*
* Assumptions:
* At present, this function is called only from initialization logic. If used
* for any other purpose that protection to assure that its operation is atomic
* will be required.
*
************************************************************************************/
void stm32_pwr_setvos(uint16_t vos)
{
uint16_t regval;
/* The following sequence is required to program the voltage regulator ranges:
* 1. Check VDD to identify which ranges are allowed...
* 2. Configure the voltage scaling range by setting the VOS bits in the PWR_CR1
* register.
*/
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
regval &= ~PWR_CR1_VOS_MASK;
regval |= (vos & PWR_CR1_VOS_MASK);
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
/************************************************************************************
* Name: stm32_pwr_setpvd
*
* Description:
* Sets power voltage detector
*
* Input Parameters:
* pls - PVD level
*
* Returned Values:
* None
*
* Assumptions:
* At present, this function is called only from initialization logic. If used
* for any other purpose that protection to assure that its operation is atomic
* will be required.
*
************************************************************************************/
void stm32_pwr_setpvd(uint16_t pls)
{
uint16_t regval;
/* Set PLS */
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
regval &= ~PWR_CR1_PLS_MASK;
regval |= (pls & PWR_CR1_PLS_MASK);
/* Write value to register */
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
/************************************************************************************
* Name: stm32_pwr_enablepvd
*
* Description:
* Enable the Programmable Voltage Detector
*
************************************************************************************/
void stm32_pwr_enablepvd(void)
{
/* Enable PVD by setting the PVDE bit in PWR_CR register. */
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, 0, PWR_CR1_PVDE);
}
/************************************************************************************
* Name: stm32_pwr_disablepvd
*
* Description:
* Disable the Programmable Voltage Detector
*
************************************************************************************/
void stm32_pwr_disablepvd(void)
{
/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, PWR_CR1_PVDE, 0);
}
#endif /* CONFIG_STM32_PWR */

5
arch/arm/src/stm32f7/stm32_pwr.h
View File

@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_pwr.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

1487
arch/arm/src/stm32f7/stm32_rtc.c Normal file
View File

File diff suppressed because it is too large Load Diff

178
arch/arm/src/stm32f7/stm32_rtc.h Normal file
View File

@ -0,0 +1,178 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rtc.h
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
* Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_RTC_H
#define __ARCH_ARM_SRC_STM32F7_STM32_RTC_H
#include <nuttx/config.h>
#include "chip.h"
/* The STMF7 family use a more traditional Realtime Clock/Calendar (RTCC) with
* broken-out data/time in BCD format. The backup registers are integrated into
* the RTCC in these families.
*/
#include "chip/stm32_rtcc.h"
#include "stm32_alarm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if !defined(CONFIG_RTC_MAGIC)
# define CONFIG_RTC_MAGIC (0xfacefeee)
#endif
#if !defined(CONFIG_RTC_MAGIC_REG)
# define CONFIG_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC CONFIG_RTC_MAGIC
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
* Thatsub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
#endif
/****************************************************************************
* Name: stm32_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int stm32_rtc_setdatetime(FAR const struct tm *tp);
#endif
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
struct rtc_lowerhalf_s;
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_RTC_H */

530
arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c Normal file
View File

@ -0,0 +1,530 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* REVISIT: This driver is *not* thread-safe! */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include <string.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/timers/rtc.h>
#include "chip.h"
#include "stm32_rtc.h"
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_NALARMS 2
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct stm32_cbinfo_s
{
volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */
volatile FAR void *priv; /* Private argurment to accompany callback */
uint8_t id; /* Identifies the alarm */
};
#endif
/* This is the private type for the RTC state. It must be cast compatible
* with struct rtc_lowerhalf_s.
*/
struct stm32_lowerhalf_s
{
/* This is the contained reference to the read-only, lower-half
* operations vtable (which may lie in FLASH or ROM)
*/
FAR const struct rtc_ops_s *ops;
/* Data following is private to this driver and not visible outside of
* this file.
*/
#ifdef CONFIG_RTC_ALARM
/* Alarm callback information */
struct stm32_cbinfo_s cbinfo[STM32_NALARMS];
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Prototypes for static methods in struct rtc_ops_s */
static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower,
FAR struct rtc_time *rtctime);
static int stm32_settime(FAR struct rtc_lowerhalf_s *lower,
FAR const struct rtc_time *rtctime);
#ifdef CONFIG_RTC_ALARM
static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setalarm_s *alarminfo);
static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setrelative_s *alarminfo);
static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower,
int alarmid);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* STM32 RTC driver operations */
static const struct rtc_ops_s g_rtc_ops =
{
.rdtime = stm32_rdtime,
.settime = stm32_settime,
#ifdef CONFIG_RTC_ALARM
.setalarm = stm32_setalarm,
.setrelative = stm32_setrelative,
.cancelalarm = stm32_cancelalarm,
#endif
#ifdef CONFIG_RTC_IOCTL
.ioctl = NULL,
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
.destroy = NULL,
#endif
};
/* STM32 RTC device state */
static struct stm32_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_alarm_callback
*
* Description:
* This is the function that is called from the RTC driver when the alarm
* goes off. It just invokes the upper half drivers callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
{
FAR struct stm32_lowerhalf_s *lower;
FAR struct stm32_cbinfo_s *cbinfo;
rtc_alarm_callback_t cb;
FAR void *priv;
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
lower = (struct stm32_lowerhalf_s *)arg;
cbinfo = &lower->cbinfo[alarmid];
/* Sample and clear the callback information to minimize the window in
* time in which race conditions can occur.
*/
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (FAR void *)cbinfo->priv;
DEBUGASSERT(priv != NULL);
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, alarmid);
}
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: stm32_rdtime
*
* Description:
* Implements the rdtime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The location in which to return the current RTC time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower,
FAR struct rtc_time *rtctime)
{
#if defined(CONFIG_RTC_DATETIME)
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
return up_rtc_getdatetime((FAR struct tm *)rtctime);
#elif defined(CONFIG_RTC_HIRES)
FAR struct timespec ts;
int ret;
/* Get the higher resolution time */
ret = up_rtc_gettime(&ts);
if (ret < 0)
{
goto errout_with_errno;
}
/* Convert the one second epoch time to a struct tm. This operation
* depends on the fact that struct rtc_time and struct tm are cast
* compatible.
*/
if (!gmtime_r(&ts.tv_sec, (FAR struct tm *)rtctime))
{
goto errout_with_errno;
}
return OK;
errout_with_errno:
ret = get_errno();
DEBUGASSERT(ret > 0);
return -ret;
#else
time_t timer;
/* The resolution of time is only 1 second */
timer = up_rtc_time();
/* Convert the one second epoch time to a struct tm */
if (!gmtime_r(&timer, (FAR struct tm *)rtctime))
{
int errcode = get_errno();
DEBUGASSERT(errcode > 0);
return -errcode;
}
return OK;
#endif
}
/****************************************************************************
* Name: stm32_settime
*
* Description:
* Implements the settime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The new time to set
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int stm32_settime(FAR struct rtc_lowerhalf_s *lower,
FAR const struct rtc_time *rtctime)
{
#ifdef CONFIG_RTC_DATETIME
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
return stm32_rtc_setdatetime((FAR const struct tm *)rtctime);
#else
struct timespec ts;
/* Convert the struct rtc_time to a time_t. Here we assume that struct
* rtc_time is cast compatible with struct tm.
*/
ts.tv_sec = mktime((FAR struct tm *)rtctime);
ts.tv_nsec = 0;
/* Now set the time (to one second accuracy) */
return up_rtc_settime(&ts);
#endif
}
/****************************************************************************
* Name: stm32_setalarm
*
* Description:
* Set a new alarm. This function implements the setalarm() method of the
* RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setalarm_s *alarminfo)
{
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
struct alm_setalarm_s lowerinfo;
int ret = -EINVAL;
/* ID0-> Alarm A; ID1 -> Alarm B */
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
priv = (FAR struct stm32_lowerhalf_s *)lower;
if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
{
/* Remember the callback information */
cbinfo = &priv->cbinfo[alarminfo->id];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
cbinfo->id = alarminfo->id;
/* Set the alarm */
lowerinfo.as_id = alarminfo->id;
lowerinfo.as_cb = stm32_alarm_callback;
lowerinfo.as_arg = priv;
memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm));
/* And set the alarm */
ret = stm32_rtc_setalarm(&lowerinfo);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
}
return ret;
}
#endif
/****************************************************************************
* Name: stm32_setrelative
*
* Description:
* Set a new alarm relative to the current time. This function implements
* the setrelative() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setrelative_s *alarminfo)
{
struct lower_setalarm_s setalarm;
struct tm time;
time_t seconds;
int ret = -EINVAL;
ASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) &&
alarminfo->reltime > 0)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
/* Get the current time in broken out format */
ret = up_rtc_getdatetime(&time);
if (ret >= 0)
{
/* Convert to seconds since the epoch */
seconds = mktime(&time);
/* Add the seconds offset. Add one to the number of seconds
* because we are unsure of the phase of the timer.
*/
seconds += (alarminfo->reltime + 1);
/* And convert the time back to broken out format */
(void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
setalarm.id = alarminfo->id;
setalarm.cb = alarminfo->cb;
setalarm.priv = alarminfo->priv;
ret = stm32_setalarm(lower, &setalarm);
}
sched_unlock();
}
return ret;
}
#endif
/****************************************************************************
* Name: stm32_cancelalarm
*
* Description:
* Cancel the current alarm. This function implements the cancelalarm()
* method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid)
{
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
priv = (FAR struct stm32_lowerhalf_s *)lower;
/* ID0-> Alarm A; ID1 -> Alarm B */
if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB)
{
/* Nullify callback information to reduce window for race conditions */
cbinfo = &priv->cbinfo[alarmid];
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Then cancel the alarm */
ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid);
}
return ret;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void)
{
return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}
#endif /* CONFIG_RTC_DRIVER */

6
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
View File

@ -746,7 +746,7 @@ static void stm32_stdclockconfig(void)
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_RTC_HSECLOCK
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
@ -936,13 +936,13 @@ static void stm32_stdclockconfig(void)
}
#endif
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
#if defined(CONFIG_STM32F7_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to

6
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
View File

@ -742,7 +742,7 @@ static void stm32_stdclockconfig(void)
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_RTC_HSECLOCK
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
@ -939,13 +939,13 @@ static void stm32_stdclockconfig(void)
}
#endif
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
#if defined(CONFIG_STM32F7_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to

4
configs/nucleo-144/src/Makefile
View File

@ -68,4 +68,8 @@ ifeq ($(CONFIG_STM32F7_OTGFS),y)
CSRCS += stm32_usb.c
endif
ifeq ($(CONFIG_STM32F7_BBSRAM),y)
CSRCS += stm32_bbsram.c
endif
include $(TOPDIR)/configs/Board.mk

6
configs/nucleo-144/src/nucleo-144.h
View File

@ -282,5 +282,11 @@ int stm32_sdio_initialize(void);
void stm32_usbinitialize(void);
#endif
/************************************************************************************
* Name: stm32_bbsram_int
************************************************************************************/
#ifdef CONFIG_STM32F7_BBSRAM
int stm32_bbsram_int(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */

3
configs/nucleo-144/src/stm32_appinitialize.c
View File

@ -101,6 +101,9 @@ int board_app_initialize(uintptr_t arg)
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
}
#endif
#ifdef CONFIG_STM32F7_BBSRAM
(void)stm32_bbsram_int();
#endif
#if defined(CONFIG_FAT_DMAMEMORY)
if (stm32_dma_alloc_init() < 0)

448
configs/nucleo-144/src/stm32_bbsram.c Normal file
View File

@ -0,0 +1,448 @@
/************************************************************************************
* configs/nucleo-144/src/stm32_bbsram.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/ioctl.h>
#include <stdio.h>
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <syslog.h>
#include <up_internal.h>
#include <stm32_bbsram.h>
#include "nucleo-144.h"
#ifdef CONFIG_STM32F7_BBSRAM
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* The path to the Battery Backed up SRAM */
#define BBSRAM_PATH "/bbr"
#define HARDFAULT_FILENO 3
#define HARDFAULT_PATH "/bbr3"
/* The sizes of the files to create (-1) use rest of BBSRAM memory */
#define BSRAM_FILE_SIZES { \
256, \
256, \
1024, \
-1, \
0 \
}
#define MAX_FILE_PATH_LENGTH 40
#define CONFIG_ISTACK_SIZE 800
#define CONFIG_USTACK_SIZE 800
#define arraySize(a) (sizeof((a))/sizeof(a[0]))
/************************************************************************************
* Private Data
************************************************************************************/
typedef uint32_t stack_word_t;
/* Used for stack frame storage */
typedef uint32_t stack_word_t;
/* Stack related data */
typedef struct {
uint32_t sp;
uint32_t top;
uint32_t size;
} _stack_s;
typedef struct {
_stack_s user;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
_stack_s interrupt;
#endif
} stack_t;
/* Not Used for reference only */
typedef struct {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t r12;
uint32_t sp;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
uint32_t d0;
uint32_t d1;
uint32_t d2;
uint32_t d3;
uint32_t d4;
uint32_t d5;
uint32_t d6;
uint32_t d7;
uint32_t d8;
uint32_t d9;
uint32_t d10;
uint32_t d11;
uint32_t d12;
uint32_t d13;
uint32_t d14;
uint32_t d15;
uint32_t fpscr;
uint32_t sp_main;
uint32_t sp_process;
uint32_t apsr;
uint32_t ipsr;
uint32_t epsr;
uint32_t primask;
uint32_t basepri;
uint32_t faultmask;
uint32_t control;
uint32_t s0;
uint32_t s1;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t s12;
uint32_t s13;
uint32_t s14;
uint32_t s15;
uint32_t s16;
uint32_t s17;
uint32_t s18;
uint32_t s19;
uint32_t s20;
uint32_t s21;
uint32_t s22;
uint32_t s23;
uint32_t s24;
uint32_t s25;
uint32_t s26;
uint32_t s27;
uint32_t s28;
uint32_t s29;
uint32_t s30;
uint32_t s31;
} proc_regs_s;
/* Flags to identify what is in the dump */
typedef enum {
eRegsPresent = 0x01,
eUserStackPresent = 0x02,
eIntStackPresent = 0x04,
eInvalidUserStackPtr = 0x20,
eInvalidIntStackPrt = 0x40,
} fault_flags_t;
typedef struct {
fault_flags_t flags; /* What is in the dump */
uintptr_t current_regs; /* Used to validate the dump */
int lineno; /* __LINE__ to up_assert */
int pid; /* Process ID */
uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save
* area */
stack_t stacks; /* Stack info */
#if CONFIG_TASK_NAME_SIZE > 0
char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL
* terminator) */
#endif
char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in
* __FILE__ to up_assert */
} info_s;
typedef struct {
info_s info; /* The info */
#if CONFIG_ARCH_INTERRUPTSTACK > 3 /* The amount of stack data is compile time
* sized backed on what is left after the
* other BBSRAM files are defined
* The order is such that only the
* ustack should be truncated
*/
stack_word_t istack[CONFIG_USTACK_SIZE];
#endif
stack_word_t ustack[CONFIG_ISTACK_SIZE];
} fullcontext_s;
/************************************************************************************
* Private Functions
************************************************************************************/
/****************************************************************************
* hardfault_get_desc
****************************************************************************/
static int hardfault_get_desc(struct bbsramd_s *desc)
{
int ret = -ENOENT;
int fd = open(HARDFAULT_PATH, O_RDONLY);
if (fd < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] (%d)\n", HARDFAULT_PATH, fd);
}
else
{
ret = -EIO;
int rv = ioctl(fd, STM32F7_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc));
if (rv >= 0)
{
ret = fd;
}
else
{
syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log descriptor (%d)\n", rv);
}
}
return ret;
}
/************************************************************************************
* Public Functions
************************************************************************************/
int stm32_bbsram_int(void)
{
/* Using Battery Backed Up SRAM */
int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
int rv;
struct bbsramd_s desc;
stm32_bbsraminitialize(BBSRAM_PATH, filesizes);
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
/* Panic Logging in Battery Backed Up Files */
/* Do we have an hard fault in BBSRAM?
*/
rv = hardfault_get_desc(&desc);
if (rv >= OK)
{
printf("There is a hard fault logged.\n");
rv = unlink(HARDFAULT_PATH);
if (rv < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file [%s] (%d)\n", HARDFAULT_PATH, rv);
}
}
#endif // CONFIG_STM32_SAVE_CRASHDUMP
return rv;
}
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
{
while (size--)
{
*dest++ = *src--;
}
}
uint8_t sdata[STM32F7_BBSRAM_SIZE];
void board_crashdump(uintptr_t currentsp, FAR void *tcb, FAR const uint8_t *filename, int lineno)
{
fullcontext_s *pdump = (fullcontext_s *)&sdata;
(void)enter_critical_section();
struct tcb_s *rtcb = (struct tcb_s *)tcb;
/* Zero out everything */
memset(pdump, 0, sizeof(fullcontext_s));
/* Save Info */
pdump->info.lineno = lineno;
if (filename) {
int offset = 0;
unsigned int len = strlen((char *)filename) + 1;
if (len > sizeof(pdump->info.filename)) {
offset = len - sizeof(pdump->info.filename) ;
}
strncpy(pdump->info.filename, (char *)&filename[offset], sizeof(pdump->info.filename));
}
/* Save the value of the pointer for current_regs as debugging info.
* It should be NULL in case of an ASSERT and will aid in cross
* checking the validity of system memory at the time of the
* fault.
*/
pdump->info.current_regs = (uintptr_t) CURRENT_REGS;
/* Save Context */
#if CONFIG_TASK_NAME_SIZE > 0
strncpy(pdump->info.name, rtcb->name, CONFIG_TASK_NAME_SIZE);
#endif
pdump->info.pid = rtcb->pid;
/* If current_regs is not NULL then we are in an interrupt context
* and the user context is in current_regs else we are running in
* the users context
*/
if (CURRENT_REGS) {
pdump->info.stacks.interrupt.sp = currentsp;
pdump->info.flags |= (eRegsPresent | eUserStackPresent | eIntStackPresent);
memcpy(pdump->info.regs, (void *)CURRENT_REGS, sizeof(pdump->info.regs));
pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
} else {
/* users context */
pdump->info.flags |= eUserStackPresent;
pdump->info.stacks.user.sp = currentsp;
}
if (pdump->info.pid == 0) {
pdump->info.stacks.user.top = g_idle_topstack - 4;
pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
} else {
pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;;
}
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
pdump->info.stacks.interrupt.top = (uint32_t)&g_intstackbase;
pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
/* If In interrupt Context save the interrupt stack data centered
* about the interrupt stack pointer
*/
if ((pdump->info.flags & eIntStackPresent) != 0) {
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp;
copy_reverse(pdump->istack, &ps[arraySize(pdump->istack) / 2], arraySize(pdump->istack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.interrupt.sp <= pdump->info.stacks.interrupt.top &&
pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - pdump->info.stacks.interrupt.size)) {
pdump->info.flags |= eInvalidIntStackPrt;
}
#endif
/* If In interrupt context or User save the user stack data centered
* about the user stack pointer
*/
if ((pdump->info.flags & eUserStackPresent) != 0) {
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp;
copy_reverse(pdump->ustack, &ps[arraySize(pdump->ustack) / 2], arraySize(pdump->ustack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top &&
pdump->info.stacks.user.sp > pdump->info.stacks.user.top - pdump->info.stacks.user.size)) {
pdump->info.flags |= eInvalidUserStackPtr;
}
int rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, sizeof(fullcontext_s));
/* Test if memory got wiped because of using _sdata */
if (rv == -ENXIO) {
char *dead = "Memory wiped - dump not saved!";
while (*dead) {
up_lowputc(*dead++);
}
} else if (rv == -ENOSPC) {
/* hard fault again */
up_lowputc('!');
}
#if defined(CONFIG_BOARD_RESET_ON_CRASH)
up_systemreset();
#endif
}
#endif // CONFIG_STM32_SAVE_CRASHDUMP
#endif /* CONFIG_STM32_BBSRAM */