Finishes Kinetis hardware header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3872 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************************************
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* arch/arm/src/kinetis/kinetis_flexcan.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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@ -31,24 +31,24 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
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/************************************************************************************
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/****************************************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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/****************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets *********************************************************************************/
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#define KINETIS_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */
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#define KINETIS_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */
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@ -86,7 +86,7 @@
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#define KINETIS_CAN_RXIMR14_OFFSET 0x08b8 /* R14 Individual Mask Registers */
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#define KINETIS_CAN_RXIMR15_OFFSET 0x08bc /* R15 Individual Mask Registers */
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/* Register Addresses ***************************************************************/
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/* Register Addresses *******************************************************************************/
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#define KINETIS_CAN0_MCR (KINETIS_CAN0_BASE+KINETIS_CAN_MCR_OFFSET)
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#define KINETIS_CAN0_CTRL1 (KINETIS_CAN0_BASE+KINETIS_CAN_CTRL1_OFFSET)
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@ -124,60 +124,195 @@
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#define KINETIS_CAN0_RXIMR14 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR14_OFFSET)
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#define KINETIS_CAN0_RXIMR15 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR15_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Register Bit Definitions *************************************************************************/
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/* Module Configuration Register */
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#define CAN_MCR_
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#define CAN_MCR_MAXMB_SHIFT (0) /* Bits 0-6: Number of the Last Message Buffer */
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#define CAN_MCR_MAXMB_MASK (0x7f << CAN_MCR_MAXMB_SHIFT)
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/* Bit 7: Reserved */
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#define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-9: ID Acceptance Mode */
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#define CAN_MCR_IDAM_MASK (3 << CAN_MCR_IDAM_SHIFT)
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# define CAN_MCR_IDAM_FMTA (0 << CAN_MCR_IDAM_SHIFT) /* Format A: One full ID */
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# define CAN_MCR_IDAM_FMTB (1 << CAN_MCR_IDAM_SHIFT) /* Format B: Two full (or partial) IDs */
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# define CAN_MCR_IDAM_FMTC (2 << CAN_MCR_IDAM_SHIFT) /* Format C: Four partial IDs */
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# define CAN_MCR_IDAM_FMTD (3 << CAN_MCR_IDAM_SHIFT) /* Format D: All frames rejected */
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/* Bits 10-11: Reserved */
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#define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */
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#define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */
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/* Bits 14-15: Reserved */
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#define CAN_MCR_IRMQ (1 << 16) /* Bit 16: Individual Rx Masking and Queue Enable */
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#define CAN_MCR_SRXDIS (1 << 17) /* Bit 17: Self Reception Disable */
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#define CAN_MCR_DOZE (1 << 18) /* Bit 18: Doze Mode Enable */
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/* Bit 19: Reserved */
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#define CAN_MCR_LPMACK (1 << 20) /* Bit 20: Low Power Mode Acknowledge */
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#define CAN_MCR_WRNEN (1 << 21) /* Bit 21: Warning Interrupt Enable */
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#define CAN_MCR_SLFWAK (1 << 22) /* Bit 22: Self Wake Up */
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#define CAN_MCR_SUPV (1 << 23) /* Bit 23: Supervisor Mode */
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#define CAN_MCR_FRZACK (1 << 24) /* Bit 24: Freeze Mode Acknowledge */
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#define CAN_MCR_SOFTRST (1 << 25) /* Bit 25: Soft Reset */
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#define CAN_MCR_WAKMSK (1 << 26) /* Bit 26: Wake Up Interrupt Mask */
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#define CAN_MCR_NOTRDY (1 << 27) /* Bit 27: FlexCAN Not Ready */
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#define CAN_MCR_HALT (1 << 28) /* Bit 28: Halt FlexCAN */
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#define CAN_MCR_RFEN (1 << 29) /* Bit 29: Rx FIFO Enable */
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#define CAN_MCR_FRZ (1 << 30) /* Bit 30: Freeze Enable */
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#define CAN_MCR_MDIS (1 << 31) /* Bit 31: Module Disable */
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/* Control 1 Register */
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#define CAN_CTRL1_
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#define CAN_CTRL1_ROPSEG_SHIFT (0) /* Bits 0-2: Propagation Segment */
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#define CAN_CTRL1_ROPSEG_MASK (7 << CAN_CTRL1_ROPSEG_SHIFT)
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#define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */
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#define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */
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#define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */
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#define CAN_CTRL1_BOFFREC (1 << 6) /* Bit 6: Bus Off Recovery */
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#define CAN_CTRL1_SMP (1 << 7) /* Bit 7: CAN Bit Sampling */
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/* Bits 8-9: Reserved */
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#define CAN_CTRL1_RWRNMSK (1 << 10) /* Bit 10: Rx Warning Interrupt Mask */
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#define CAN_CTRL1_TWRNMSK (1 << 11) /* Bit 11: Tx Warning Interrupt Mask */
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#define CAN_CTRL1_LPB (1 << 12) /* Bit 12: Loop Back Mode */
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#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */
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#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */
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#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */
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#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */
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#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT)
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#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-21: Phase Segment 1 */
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#define CAN_CTRL1_PSEG1_MASK (7 << CAN_CTRL1_PSEG1_SHIFT)
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#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-23: Resync Jump Width */
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#define CAN_CTRL1_RJW_MASK (3 << CAN_CTRL1_RJW_SHIFT)
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#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-31: Prescaler Division Factor */
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#define CAN_CTRL1_PRESDIV_MASK (0xff << CAN_CTRL1_PRESDIV_SHIFT)
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/* Free Running Timer */
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#define CAN_TIMER_
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/* Rx Mailboxes Global Mask Register */
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#define CAN_RXMGMASK_
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#define CAN_TIMER_SHIFT (0) /* Bits 0-15: Timer value */
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#define CAN_TIMER_MASK (0xffff << CAN_TIMER_SHIFT)
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/* Bits 16-31: Reserved */
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/* Rx Mailboxes Global Mask Register (32 Rx Mailboxes Global Mask Bits) */
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#define CAN_RXMGMASK(n) (1 << (n)) /* Bit n: Rx Mailboxe n Global Mask Bit */
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/* Rx 14 Mask Register */
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#define CAN_RX14MASK_
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#define CAN_RX14MASK(n) (1 << (n)) /* Bit n: Rx Buffer 14 Mask Bit n */
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/* Rx 15 Mask Register */
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#define CAN_RX15MASK_
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#define CAN_RX15MASK(n) (1 << (n)) /* Bit n: Rx Buffer 15 Mask Bit n */
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/* Error Counter */
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#define CAN_ECR_
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#define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-7: Transmit Error Counter */
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#define CAN_ECR_TXERRCNT_MASK (0xff << CAN_ECR_TXERRCNT_SHIFT)
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#define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-15: Receive Error Counter */
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#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT)
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/* Bits 16-31: Reserved */
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/* Error and Status 1 Register */
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#define CAN_ESR1_
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#define CAN_ESR1_WAKINT (1 << 0) /* Bit 0: Wake-Up Interrupt */
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#define CAN_ESR1_ERRINT (1 << 1) /* Bit 1: Error Interrupt */
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#define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: 'Bus Off' Interrupt */
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#define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception */
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#define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-5: Fault Confinement State */
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#define CAN_ESR1_FLTCONF_MASK (3 << CAN_ESR1_FLTCONF_SHIFT)
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# define CAN_ESR1_FLTCONF_ACTV (0 << CAN_ESR1_FLTCONF_SHIFT) /* Error Active */
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# define CAN_ESR1_FLTCONF_PASV (1 << CAN_ESR1_FLTCONF_SHIFT) /* Error Passive */
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# define CAN_ESR1_FLTCONF_OFF (2 << CAN_ESR1_FLTCONF_SHIFT) /* Bus Off */
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#define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN in Transmission */
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#define CAN_ESR1_IDLE (1 << 7) /* Bit 7: CAN bus is in IDLE state */
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#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */
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#define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning */
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#define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error */
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#define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error */
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#define CAN_ESR1_CRCERR (1 << 12) /* Bit 12: Cyclic Redundancy Check Error */
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#define CAN_ESR1_ACKERR (1 << 13) /* Bit 13: Acknowledge Error */
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#define CAN_ESR1_BIT0ERR (1 << 14) /* Bit 14: Bit0 Error */
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#define CAN_ESR1_BIT1ERR (1 << 15) /* Bit 15: Bit1 Error */
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#define CAN_ESR1_RWRNINT (1 << 16) /* Bit 16: Rx Warning Interrupt Flag */
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#define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */
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#define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */
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/* Bits 19-31: Reserved */
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/* Interrupt Masks 2 Register */
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#define CAN_IMASK2_
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#define CAN_IMASK2(n) (1 << (n)) /* Bit n: Buffer MBn Mask */
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/* Interrupt Masks 1 Register */
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#define CAN_IMASK1_
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#define CAN_IMASK1(n) (1 << (n)) /* Bit n: Buffer MBn Mask */
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/* Interrupt Flags 2 Register */
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#define CAN_IFLAG2_
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#define CAN_IFLAG2(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt */
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/* Interrupt Flags 1 Register */
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#define CAN_IFLAG1_
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#define CAN_IFLAG1(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt, n=0..4,8..31 */
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/* Control 2 Register */
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#define CAN_CTRL2_
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/* Bits 0-15: Reserved */
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#define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable (Rx) */
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#define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */
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#define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Mailboxes Reception Priority */
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#define CAN_CTRL2_TASD_SHIFT (19) /* Bits 19-23: Tx Arbitration Start Delay */
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#define CAN_CTRL2_TASD_MASK (31 << CAN_CTRL2_TASD_SHIFT)
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#define CAN_CTRL2_RFFN_SHIFT (24) /* Bits 24-27: Number of Rx FIFO Filters */
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#define CAN_CTRL2_RFFN_MASK (15 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_8MB (0 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_16MB (1 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_24MB (2 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_32MB (3 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_40MB (4 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_48MB (5 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_56MB (6 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_64MB (7 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_72MB (8 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_80MB (9 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_88MB (10 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_96MB (11 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_104MB (12 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_112MB (13 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_120MB (14 << CAN_CTRL2_RFFN_SHIFT)
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# define CAN_CTRL2_RFFN_128MB (15 << CAN_CTRL2_RFFN_SHIFT)
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#define CAN_CTRL2_WRMFRZ (1 << 28) /* Bit 28: Write-Access to Memory in Freeze mode */
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/* Bits 29-31: Reserved */
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/* Error and Status 2 Register */
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#define CAN_ESR2_
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/* Bits 0-12: Reserved */
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#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */
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#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
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/* Bit 15: Reserved */
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#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
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#define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */
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#define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT)
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/* Bits 23-31: Reserved */
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/* CRC Register */
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#define CAN_CRCR_
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/* Rx FIFO Global Mask Register */
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#define CAN_RXFGMASK_
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/* Bits 23-31: Reserved */
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#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */
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#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT)
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/* Bit 15: Reserved */
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#define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */
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#define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT)
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/* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */
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/* Rx FIFO Information Register */
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#define CAN_RXFIR_
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/* Bits 9-31: Reserved */
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#define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-8: Identifier Acceptance Filter Hit Indicator */
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#define CAN_RXFIR_IDHIT_MASK (0x1ff << CAN_RXFIR_IDHIT_SHIFT)
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/* Rn Individual Mask Registers */
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#define CAN_RXIMR_
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(1 << nn) /* Bit nn:
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_SHIFT (nn) /* Bits nn-nn:
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_MASK (nn << nn)
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#define CAN_RXIMR(n) (1 << (n)) /* Bit n: Individual Mask Bits */
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/************************************************************************************
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/****************************************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************************************/
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/************************************************************************************
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/****************************************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************************************/
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/************************************************************************************
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/****************************************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************************************
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* arch/arm/src/kinetis/kinetis_i2s.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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@ -31,24 +31,24 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
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/************************************************************************************
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/****************************************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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/****************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets *********************************************************************************/
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#define KINETIS_I2S_TX0_OFFSET 0x000 /* I2S Transmit Data Registers 0 */
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#define KINETIS_I2S_TX1_OFFSET 0x004 /* I2S Transmit Data Registers 1 */
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#define KINETIS_I2S_ACCEN_OFFSET 0x054 /* I2S AC97 Channel Enable Register */
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#define KINETIS_I2S_ACCDIS_OFFSET 0x058 /* I2S AC97 Channel Disable Register */
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/* Register Addresses ***************************************************************/
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/* Register Addresses *******************************************************************************/
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#define KINETIS_I2S0_TX0 (KINETIS_I2S0_BASE+KINETIS_I2S_TX0_OFFSET)
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#define KINETIS_I2S0_TX1 (KINETIS_I2S0_BASE+KINETIS_I2S_TX1_OFFSET)
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#define KINETIS_I2S0_ACCEN (KINETIS_I2S0_BASE+KINETIS_I2S_ACCEN_OFFSET)
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#define KINETIS_I2S0_ACCDIS (KINETIS_I2S0_BASE+KINETIS_I2S_ACCDIS_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Register Bit Definitions *************************************************************************/
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/* I2S Transmit Data Registers 0/1 and I2S Receive Data Registers 0/1: 32-bit I2S data */
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/* I2S Transmit Data Registers 0 */
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#define I2S_TX0_
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/* I2S Transmit Data Registers 1 */
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#define I2S_TX1_
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/* I2S Receive Data Registers 0 */
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#define I2S_RX0_
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/* I2S Receive Data Registers 1 */
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#define I2S_RX1_
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/* I2S Control Register */
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#define I2S_CR_
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/* I2S Interrupt Status Register */
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#define I2S_ISR_
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/* I2S Interrupt Enable Register */
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#define I2S_IER_
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#define I2S_CR_I2SEN (1 << 0) /* Bit 0: I2S Enable */
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#define I2S_CR_TE (1 << 1) /* Bit 1: Transmit Enable */
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#define I2S_CR_RE (1 << 2) /* Bit 2: Receive Enable */
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#define I2S_CR_NET (1 << 3) /* Bit 3: Network Mode */
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#define I2S_CR_SYN (1 << 4) /* Bit 4: Synchronous Mode */
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#define I2S_CR_I2SMODE_SHIFT (5) /* Bits 5-6: I2S Mode Select */
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#define I2S_CR_I2SMODE_MASK (3 << I2S_CR_I2SMODE_SHIFT)
|
||||
# define I2S_CR_I2SMODE_NORMAL (0 << I2S_CR_I2SMODE_SHIFT) /* Normal mode */
|
||||
# define I2S_CR_I2SMODE_MASTER (1 << I2S_CR_I2SMODE_SHIFT) /* I2S master mode */
|
||||
# define I2S_CR_I2SMODE_SLAVE (2 << I2S_CR_I2SMODE_SHIFT) /* I2S slave mode */
|
||||
#define I2S_CR_SYSCLKEN (1 << 7) /* Bit 7: System Clock (Oversampling Clock) Enable */
|
||||
#define I2S_CR_TCHEN (1 << 8) /* Bit 8: Two-Channel Operation Enable */
|
||||
#define I2S_CR_CLKIST (1 << 9) /* Bit 9: Clock Idle */
|
||||
#define I2S_CR_TFRCLKDIS (1 << 10) /* Bit 10: Transmit Frame Clock Disable */
|
||||
#define I2S_CR_RFRCLKDIS (1 << 11) /* Bit 11: Receive Frame Clock Disable */
|
||||
#define I2S_CR_SYNCTXFS (1 << 12) /* Bit 12: CR[TE] latched with FS occurrence */
|
||||
/* Bits 13-31: Reserved */
|
||||
/* I2S Interrupt Status Register and I2S Interrupt Enable Register common bit definitions */
|
||||
|
||||
#define I2S_INT_TFE0 (1 << 0) /* Bit 0: Transmit FIFO Empty 0 */
|
||||
#define I2S_INT_TFE1 (1 << 1) /* Bit 1: Transmit FIFO Empty 1 */
|
||||
#define I2S_INT_RFF0 (1 << 2) /* Bit 2: Receive FIFO Full 0 */
|
||||
#define I2S_INT_RFF1 (1 << 3) /* Bit 3: Receive FIFO Full 1 */
|
||||
#define I2S_INT_RLS (1 << 4) /* Bit 4: Receive Last Time Slot */
|
||||
#define I2S_INT_TLS (1 << 5) /* Bit 5: Transmit Last Time Slot */
|
||||
#define I2S_INT_RFS (1 << 6) /* Bit 6: Receive Frame Sync */
|
||||
#define I2S_INT_TFS (1 << 7) /* Bit 7: Transmit Frame Sync */
|
||||
#define I2S_INT_TUE0 (1 << 8) /* Bit 8: Transmitter Underrun Error 1 */
|
||||
#define I2S_INT_TUE1 (1 << 9) /* Bit 9: Transmitter Underrun Error 1 */
|
||||
#define I2S_INT_ROE0 (1 << 10) /* Bit 10: Receiver Overrun Error 0 */
|
||||
#define I2S_INT_ROE1 (1 << 11) /* Bit 11: Receiver Overrun Error 1 */
|
||||
#define I2S_INT_TDE0 (1 << 12) /* Bit 12: Transmit Data Register Empty 0 */
|
||||
#define I2S_INT_TDE1 (1 << 13) /* Bit 13: Transmit Data Register Empty 1 */
|
||||
#define I2S_INT_RDR0 (1 << 14) /* Bit 14: Receive Data Ready 0 */
|
||||
#define I2S_INT_RDR1 (1 << 15) /* Bit 15: Receive Data Ready 1 */
|
||||
#define I2S_INT_RXT (1 << 16) /* Bit 16: Receive Tag Updated */
|
||||
#define I2S_INT_CMDDU (1 << 17) /* Bit 17: Command Data Register Updated */
|
||||
#define I2S_INT_CMDAU (1 << 18) /* Bit 18: Command Address Register Updated */
|
||||
/* Bits 19-22: Reserved */
|
||||
#define I2S_INT_TRFC (1 << 23) /* Bit 23: Transmit Frame Complete */
|
||||
#define I2S_INT_RFRC (1 << 24) /* Bit 24: Receive Frame Complete */
|
||||
/* Bits 25-31: Reserved */
|
||||
/* I2S Interrupt Status Register (see common definitions above) */
|
||||
/* I2S Interrupt Enable Register (see common definitions above and unique definitions below)*/
|
||||
/* Bits 0-18: See common definitions above */
|
||||
#define I2S_IER_TIE (1 << 19) /* Bit 19: Transmit Interrupt Enable */
|
||||
#define I2S_IER_TDMAE (1 << 20) /* Bit 20: Transmit DMA Enable */
|
||||
#define I2S_IER_RIE (1 << 21) /* Bit 21: Receive Interrupt Enable */
|
||||
#define I2S_IER_RDMAE (1 << 22) /* Bit 22: Receive DMA Enable */
|
||||
/* Bits 23-24: See common definitions above */
|
||||
/* Bits 25-31: Reserved */
|
||||
/* I2S Transmit Configuration Register */
|
||||
#define I2S_TCR_
|
||||
|
||||
#define I2S_TCR_TEFS (1 << 0) /* Bit 0: Transmit Early Frame Sync */
|
||||
#define I2S_TCR_TFSL (1 << 1) /* Bit 1: Transmit Frame Sync Length */
|
||||
#define I2S_TCR_TFSI (1 << 2) /* Bit 2: Transmit Frame Sync Invert */
|
||||
#define I2S_TCR_TSCKP (1 << 3) /* Bit 3: Transmit Clock Polarity */
|
||||
#define I2S_TCR_TSHFD (1 << 4) /* Bit 4: Transmit Shift Direction */
|
||||
#define I2S_TCR_TXDIR (1 << 5) /* Bit 5: Transmit clock direction */
|
||||
#define I2S_TCR_TFDIR (1 << 6) /* Bit 6: Transmit Frame Direction */
|
||||
#define I2S_TCR_TFEN0 (1 << 7) /* Bit 7: Transmit FIFO Enable 0 */
|
||||
#define I2S_TCR_TFEN1 (1 << 8) /* Bit 8: Transmit FIFO Enable 1 */
|
||||
#define I2S_TCR_TXBIT0 (1 << 9) /* Bit 9: Transmit Bit 0 */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* I2S Receive Configuration Register */
|
||||
#define I2S_RCR_
|
||||
|
||||
#define I2S_RCR_REFS (1 << 0) /* Bit 0: Receive Early Frame Sync */
|
||||
#define I2S_RCR_RFSL (1 << 1) /* Bit 1: Receive Frame Sync Length */
|
||||
#define I2S_RCR_RFSI (1 << 2) /* Bit 2: Receive Frame Sync Invert */
|
||||
#define I2S_RCR_RSCKP (1 << 3) /* Bit 3: Receive Clock Polarity */
|
||||
#define I2S_RCR_RSHFD (1 << 4) /* Bit 4: Receive Shift Direction */
|
||||
#define I2S_RCR_RXDIR (1 << 5) /* Bit 5: Receive Clock Direction */
|
||||
#define I2S_RCR_RFDIR (1 << 6) /* Bit 6: Receive Frame Direction */
|
||||
#define I2S_RCR_RFEN0 (1 << 7) /* Bit 7: Receive FIFO Enable 0 */
|
||||
#define I2S_RCR_RFEN1 (1 << 8) /* Bit 8: Receive FIFO Enable 1 */
|
||||
#define I2S_RCR_RXBIT0 (1 << 9) /* Bit 9: Receive Bit 0 */
|
||||
#define I2S_RCR_RXEXT (1 << 10) /* Bit 10: Receive Data Extension */
|
||||
/* Bits 11-31: Reserved */
|
||||
/* I2S Transmit Clock Control Registers */
|
||||
#define I2S_TCCR_
|
||||
|
||||
#define I2S_TCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */
|
||||
#define I2S_TCCR_PM_MASK (0xff << I2S_TCCR_PM_SHIFT)
|
||||
#define I2S_TCCR_DC_SHIFT (8) /* Bits 8-12: Frame Rate Divider Control */
|
||||
#define I2S_TCCR_DC_MASK (31 << I2S_TCCR_DC_SHIFT)
|
||||
#define I2S_TCCR_WL_SHIFT (13) /* Bits 13-16: Word Length Control */
|
||||
#define I2S_TCCR_WL_MASK (15 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_8 (3 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_10 (4 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_12 (5 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_16 (7 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_18 (8 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_20 (9 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_22 (10 << I2S_TCCR_WL_SHIFT)
|
||||
# define I2S_TCCR_WL_24 (11 << I2S_TCCR_WL_SHIFT)
|
||||
#define I2S_TCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */
|
||||
#define I2S_TCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */
|
||||
/* Bits 19-31: Reserved */
|
||||
/* I2S Receive Clock Control Registers */
|
||||
#define I2S_RCCR_
|
||||
|
||||
#define I2S_RCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */
|
||||
#define I2S_RCCR_PM_MASK (0xff << I2S_RCCR_PM_SHIFT)
|
||||
#define I2S_RCCR_DC_SHIFT (8) /* Bits 8-12: Frame Rate Divider Control */
|
||||
#define I2S_RCCR_DC_MASK (31 << I2S_RCCR_DC_SHIFT)
|
||||
#define I2S_RCCR_WL_SHIFT (13) /* Bits 13-16: Word Length Control */
|
||||
#define I2S_RCCR_WL_MASK (15 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_8 (3 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_10 (4 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_12 (5 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_16 (7 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_18 (8 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_20 (9 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_22 (10 << I2S_RCCR_WL_SHIFT)
|
||||
# define I2S_RCCR_WL_24 (11 << I2S_RCCR_WL_SHIFT)
|
||||
#define I2S_RCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */
|
||||
#define I2S_RCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */
|
||||
/* Bits 19-31: Reserved */
|
||||
/* I2S FIFO Control/Status Register */
|
||||
#define I2S_FCSR_
|
||||
|
||||
#define I2S_FCSR_TFWM0_SHIFT (0) /* Bits 0-3: Transmit FIFO Empty WaterMark 0 */
|
||||
#define I2S_FCSR_TFWM0_MASK (15 << I2S_FCSR_TFWM0_SHIFT)
|
||||
#define I2S_FCSR_RFWM0_SHIFT (4) /* Bits 4-7: Receive FIFO Full WaterMark 0 */
|
||||
#define I2S_FCSR_RFWM0_MASK (15 << I2S_FCSR_RFWM0_SHIFT)
|
||||
#define I2S_FCSR_TFCNT0_SHIFT (8) /* Bits 8-11: Transmit FIFO Counter 0 */
|
||||
#define I2S_FCSR_TFCNT0_MASK (15 << I2S_FCSR_TFCNT0_SHIFT)
|
||||
#define I2S_FCSR_RFCNT0_SHIFT (12) /* Bits 12-15: Receive FIFO Counter 0 */
|
||||
#define I2S_FCSR_RFCNT0_MASK (15 << I2S_FCSR_RFCNT0_SHIFT)
|
||||
#define I2S_FCSR_TFWM1_SHIFT (16) /* Bits 16-19: Transmit FIFO Empty WaterMark 1 */
|
||||
#define I2S_FCSR_TFWM1_MASK (15 << I2S_FCSR_TFWM1_SHIFT)
|
||||
#define I2S_FCSR_RFWM1_SHIFT (20) /* Bits 20-23: Receive FIFO Full WaterMark 1 */
|
||||
#define I2S_FCSR_RFWM1_MASK (15 << I2S_FCSR_RFWM1_SHIFT)
|
||||
#define I2S_FCSR_TFCNT1_SHIFT (24) /* Bits 24-27: Transmit FIFO Counter 1 */
|
||||
#define I2S_FCSR_TFCNT1_MASK (15 << I2S_FCSR_TFCNT1_SHIFT)
|
||||
#define I2S_FCSR_RFCNT1_SHIFT (28) /* Bits 28-31: Receive FIFO Counter 1 */
|
||||
#define I2S_FCSR_RFCNT1_MASK (15 << I2S_FCSR_RFCNT1_SHIFT)
|
||||
|
||||
/* I2S AC97 Control Register */
|
||||
#define I2S_ACNT_
|
||||
|
||||
#define I2S_ACNT_AC97EN (1 << 0) /* Bit 0: AC97 Mode Enable */
|
||||
#define I2S_ACNT_FV (1 << 1) /* Bit 1: Fixed/Variable Operation */
|
||||
#define I2S_ACNT_TIF (1 << 2) /* Bit 2: Tag in FIFO */
|
||||
#define I2S_ACNT_RD (1 << 3) /* Bit 3: Read Command */
|
||||
#define I2S_ACNT_WR (1 << 4) /* Bit 4: Write Command */
|
||||
#define I2S_ACNT_FRDIV_SHIFT (5) /* Bits 5-10: Frame Rate Divider */
|
||||
#define I2S_ACNT_FRDIV_MASK (63 << I2S_ACNT_FRDIV_SHIFT)
|
||||
/* Bits 11-31: Reserved */
|
||||
/* I2S AC97 Command Address Register */
|
||||
#define I2S_ACADD_
|
||||
|
||||
#define I2S_ACADD_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Address */
|
||||
#define I2S_ACADD_ACADD_MASK (0x7ffff << I2S_ACADD_ACADD_SHIFT)
|
||||
/* Bits 19-31: Reserved */
|
||||
/* I2S AC97 Command Data Register */
|
||||
#define I2S_ACDAT_
|
||||
|
||||
#define I2S_ACDAT_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Data */
|
||||
#define I2S_ACDAT_ACADD_MASK (0x7ffff << I2S_ACDAT_ACADD_SHIFT)
|
||||
/* Bits 19-31: Reserved */
|
||||
/* I2S AC97 Tag Register */
|
||||
#define I2S_ATAG_
|
||||
/* I2S Transmit Time Slot Mask Register */
|
||||
#define I2S_TMSK_
|
||||
/* I2S Receive Time Slot Mask Register */
|
||||
#define I2S_RMSK_
|
||||
|
||||
#define I2S_ATAG_ACADD_SHIFT (0) /* Bits 0-15: AC97 Tag Value */
|
||||
#define I2S_ATAG_ACADD_MASK (0xffff << I2S_ACDAT_ACADD_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* I2S Transmit Time Slot Mask Register (32-bit Transmit Mask) */
|
||||
/* I2S Receive Time Slot Mask Register (32-bit Receive Mask) */
|
||||
|
||||
/* I2S AC97 Channel Status Register */
|
||||
#define I2S_ACCST_
|
||||
|
||||
#define I2S_ACCST_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Status */
|
||||
#define I2S_ACCST_ACCST_MASK (0x3ff << I2S_ACCST_ACCST_SHIFT)
|
||||
/* Bits 10-31: Reserved */
|
||||
/* I2S AC97 Channel Enable Register */
|
||||
#define I2S_ACCEN_
|
||||
|
||||
#define I2S_ACCEN_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Enable */
|
||||
#define I2S_ACCEN_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT)
|
||||
/* Bits 10-31: Reserved */
|
||||
/* I2S AC97 Channel Disable Register */
|
||||
#define I2S_ACCDIS_
|
||||
#define I2S__
|
||||
|
||||
(1 << nn) /* Bit nn:
|
||||
_SHIFT (nn) /* Bits nn-nn:
|
||||
_MASK (nn << nn)
|
||||
#define I2S_ACCDIS_ACCST_SHIFT (0) /* Bits 0-9: AC97 AC97 Channel Disable */
|
||||
#define I2S_ACCDIS_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT)
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
****************************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
****************************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H */
|
||||
|
||||
@ -105,57 +105,305 @@
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* LCD general control register */
|
||||
#define LCD_GCR_
|
||||
/* LCD auxiliary register */
|
||||
#define LCD_AR_
|
||||
/* LCD fault detect control register */
|
||||
#define LCD_FDCR_
|
||||
/* LCD fault detect status register */
|
||||
#define LCD_FDSR_
|
||||
/* LCD pin enable register */
|
||||
#define LCD_PENL_
|
||||
/* LCD pin enable register */
|
||||
#define LCD_PENH_
|
||||
/* LCD backplane enable register */
|
||||
#define LCD_BPENL_
|
||||
/* LCD backplane enable register */
|
||||
#define LCD_BPENH_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF3TO0_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF7TO4_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF11TO8_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF15TO12_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF19TO16_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF23TO20_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF27TO24_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF31TO28_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF35TO32_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF39TO36_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF43TO40_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF47TO44_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF51TO48_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF55TO52_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF59TO56_
|
||||
/* LCD waveform register */
|
||||
#define LCD_WF63TO60_
|
||||
|
||||
(1 << nn) /* Bit nn:
|
||||
_SHIFT (nn) /* Bits nn-nn:
|
||||
_MASK (nn << nn)
|
||||
#define LCD_GCR_DUTYSHIFT (0) /* Bits 0-2: LCD duty select */
|
||||
#define LCD_GCR_DUTY_MASK (7 << LCD_GCR_DUTYSHIFT)
|
||||
# define LCD_GCR_DUTY_BP(n) (((n)-1) << LCD_GCR_DUTYSHIFT) /* Use n BP (1/n duty cyle) */
|
||||
#define LCD_GCR_LCLK_SHIFT (3) /* Bits 3-5: LCD clock prescaler */
|
||||
#define LCD_GCR_LCLK_MASK (7 << LCD_GCR_LCLK_SHIFT)
|
||||
#define LCD_GCR_SOURCE (1 << 6) /* Bit 6: LCD clock source select */
|
||||
#define LCD_GCR_LCDEN (1 << 7) /* Bit 7: LCD driver enable */
|
||||
#define LCD_GCR_LCDSTP (1 << 8) /* Bit 8: Stop mode */
|
||||
#define LCD_GCR_LCDWAIT (1 << 9) /* Bit 9: Wait mode */
|
||||
/* Bits 10-11: Reserved */
|
||||
#define LCD_GCR_ALTDIV_SHIFT (12) /* Bits 12-13: LCD alternate clock divider */
|
||||
#define LCD_GCR_ALTDIV_MASK (3 << LCD_GCR_ALTDIV_SHIFT)
|
||||
# define LCD_GCR_ALTDIV_DIV (0 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 1 (No divide) */
|
||||
# define LCD_GCR_ALTDIV_DIV (1 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 8 */
|
||||
# define LCD_GCR_ALTDIV_DIV (2 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 64 */
|
||||
# define LCD_GCR_ALTDIV_DIV (3 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 512 */
|
||||
#define LCD_GCR_FDCIEN (1 << 14) /* Bit 14: LCD fault detection complete interrupt enable */
|
||||
#define LCD_GCR_LCDIEN (1 << 15) /* Bit 15: LCD frame frequency interrupt enable */
|
||||
#define LCD_GCR_VSUPPLY_SHIFT (16) /* Bits 16-17: Voltage supply control */
|
||||
#define LCD_GCR_VSUPPLY_MASK (3 << LCD_GCR_VSUPPLY_SHIFT)
|
||||
#define LCD_GCR_VSUPPLY_INTVLL2 (0 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL2 internally from VDD */
|
||||
#define LCD_GCR_VSUPPLY_INTVLL3 (1 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 internally from VDD */
|
||||
#define LCD_GCR_VSUPPLY_EXTVLL3 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 externally from VDD */
|
||||
#define LCD_GCR_VSUPPLY_INTVLL1 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL1 internally from VIREG */
|
||||
/* Bits 18-19: Reserved */
|
||||
#define LCD_GCR_LADJ_SHIFT (20) /* Bits 20-21: Load adjust */
|
||||
#define LCD_GCR_LADJ_MASK (3 << LCD_GCR_LADJ_SHIFT)
|
||||
# define LCD_GCR_LADJ_LOW (0 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=0, Low load <=2000pF */
|
||||
# define LCD_GCR_LADJ_MIDLOW (1 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=0, Low load <=2000pF */
|
||||
# define LCD_GCR_LADJ_MIDHIGH (2 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=0, High load <=8000pF */
|
||||
# define LCD_GCR_LADJ_HIGH (3 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=0, High load <=8000pF */
|
||||
# define LCD_GCR_LADJ_FAST (0 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=8000pF */
|
||||
# define LCD_GCR_LADJ_MIDFAST (1 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=6000pF */
|
||||
# define LCD_GCR_LADJ_MIDSLOW (2 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=4000pF */
|
||||
# define LCD_GCR_LADJ_SLOW (3 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=2000pF */
|
||||
#define LCD_GCR_HREFSEL (1 << 22) /* Bit 22: High reference select */
|
||||
#define LCD_GCR_CPSEL (1 << 23) /* Bit 23: Charge pump or resistor bias select */
|
||||
#define LCD_GCR_RVTRIM_SHIFT (24) /* Bits 24-27: Regulated voltage trim */
|
||||
#define LCD_GCR_RVTRIM_MASK (15 << LCD_GCR_RVTRIM_SHIFT)
|
||||
/* Bits 28-30: Reserved */
|
||||
#define LCD_GCR_RVEN (1 << 31) /* Bit 31: Regulated voltage enable */
|
||||
|
||||
/* LCD auxiliary register */
|
||||
|
||||
#define LCD_AR_BRATE_SHIFT (0) /* Bits 0-2: Blink-rate configuration */
|
||||
#define LCD_AR_BRATE_MASK (7 << LCD_AR_BRATE_SHIFT)
|
||||
#define LCD_AR_BMODE (1 << 3) /* Bit 3: Blink mode */
|
||||
/* Bit 4: Reserved */
|
||||
#define LCD_AR_BLANK (1 << 5) /* Bit 5: Blank display mode
|
||||
#define LCD_AR_ALT (1 << 6) /* Bit 6: Alternate display mode */
|
||||
#define LCD_AR_BLINK (1 << 7) /* Bit 7: Blink command */
|
||||
/* Bits 8-14: Reserved */
|
||||
#define LCD_AR_LCDIF (1 << 15) /* Bit 15: LCD frame frequency interrupt flag */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* LCD fault detect control register */
|
||||
|
||||
#define LCD_FDCR_FDPINID_SHIFT (0) /* Bits 0-5: Fault detect pin ID */
|
||||
#define LCD_FDCR_FDPINID_MASK (63 << LCD_FDCR_FDPINID_SHIFT)
|
||||
#define LCD_FDCR_FDBPEN (1 << 6) /* Bit 6: Fault detect backplane enable */
|
||||
#define LCD_FDCR_FDEN (1 << 7) /* Bit 7: Fault detect enable */
|
||||
/* Bit 8: Reserved */
|
||||
#define LCD_FDCR_FDSWW_SHIFT (9) /* Bits 9-11: Fault detect sample window width */
|
||||
#define LCD_FDCR_FDSWW_MASK (7 << LCD_FDCR_FDSWW_SHIFT)
|
||||
#define LCD_FDCR_FDPRS_SHIFT (12) /* Bits 12-14: Fault detect clock prescaler */
|
||||
#define LCD_FDCR_FDPRS_MASK (7 << LCD_FDCR_FDPRS_SHIFT)
|
||||
# define LCD_FDCR_FDPRS_DIV1 (0 << LCD_FDCR_FDPRS_SHIFT) /* Bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV2 (1 << LCD_FDCR_FDPRS_SHIFT) /* 1/2 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV4 (2 << LCD_FDCR_FDPRS_SHIFT) /* 1/4 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV8 (3 << LCD_FDCR_FDPRS_SHIFT) /* 1/8 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV16 (4 << LCD_FDCR_FDPRS_SHIFT) /* 1/16 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV32 (5 << LCD_FDCR_FDPRS_SHIFT) /* 1/32 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV64 (6 << LCD_FDCR_FDPRS_SHIFT) /* 1/64 bus clock */
|
||||
# define LCD_FDCR_FDPRS_DIV128 (7 << LCD_FDCR_FDPRS_SHIFT) /* 1/128 bus clock */
|
||||
/* Bits 15-31: Reserved */
|
||||
/* LCD fault detect status register */
|
||||
|
||||
#define LCD_FDSR_FDCNT_SHIFT (0) /* Bits 0-7: Fault detect counter */
|
||||
#define LCD_FDSR_FDCNT_MASK (0xff << LCD_FDSR_FDCNT_SHIFT)
|
||||
/* Bits 8-14: Reserved */
|
||||
#define LCD_FDSR_FDCF (1 << 15) /* Bit 15: Fault detection complete flag */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* LCD pin enable register low/high (64 pin bits in two 32-bit registers) */
|
||||
|
||||
|
||||
/* LCD backplane enable register (64 pin bits in two 32-bit registers) */
|
||||
|
||||
#define LCD_BPENL(n) (1 << (n)) /* Bit n: Enable backplane operation pin n, n=0-31 */
|
||||
#define LCD_BPENH(n) (1 << ((n)-32)) /* Bit n-32: Enable backplane operation pin n, n=32-63 */
|
||||
|
||||
/* LCD waveform registers */
|
||||
|
||||
#define LCD_WF3TO0_WF0_SHIFT (0) /* Bits 0-7: Waveform control field 0 segment bits */
|
||||
#define LCD_WF3TO0_WF0_MASK (0xff << LCD_WF3TO0_WF0_SHIFT)
|
||||
# define LCD_WF3TO0_WF0_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF0_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF3TO0_WF1_SHIFT (8) /* Bits 8-15: Waveform control field 1 segment bits */
|
||||
#define LCD_WF3TO0_WF1_MASK (0xff << LCD_WF3TO0_WF1_SHIFT)
|
||||
# define LCD_WF3TO0_WF1_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF1_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF3TO0_WF2_SHIFT (16) /* Bits 16-23: Waveform control field 2 segment bits */
|
||||
#define LCD_WF3TO0_WF2_MASK (0xff << LCD_WF3TO0_WF2_SHIFT)
|
||||
# define LCD_WF3TO0_WF2_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF2_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF3TO0_WF3_SHIFT (24) /* Bits 24-31: Waveform control field 3 segment bits */
|
||||
#define LCD_WF3TO0_WF3_MASK (0xff << LCD_WF3TO0_WF3_SHIFT)
|
||||
# define LCD_WF3TO0_WF3_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF3_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF7TO4_WF4_SHIFT (0) /* Bits 0-7: Waveform control field 4 segment bits */
|
||||
#define LCD_WF7TO4_WF4_MASK (0xff << LCD_WF7TO4_WF4_SHIFT)
|
||||
# define LCD_WF7TO4_WF4_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF4_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF7TO4_WF5_SHIFT (8) /* Bits 8-15: Waveform control field 5 segment bits */
|
||||
#define LCD_WF7TO4_WF5_MASK (0xff << LCD_WF7TO4_WF5_SHIFT)
|
||||
# define LCD_WF7TO4_WF5_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF5_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF7TO4_WF6_SHIFT (16) /* Bits 16-23: Waveform control field 6 segment bits */
|
||||
#define LCD_WF7TO4_WF6_MASK (0xff << LCD_WF7TO4_WF6_SHIFT)
|
||||
# define LCD_WF7TO4_WF6_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF6_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF7TO4_WF7_SHIFT (24) /* Bits 24-31: Waveform control field 7 segment bits */
|
||||
#define LCD_WF7TO4_WF7_MASK (0xff << LCD_WF7TO4_WF7_SHIFT)
|
||||
# define LCD_WF7TO4_WF7_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF7_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF11TO8_WF8_SHIFT (0) /* Bits 0-7: Waveform control field 8 segment bits */
|
||||
#define LCD_WF11TO8_WF8_MASK (0xff << LCD_WF11TO8_WF8_SHIFT)
|
||||
# define LCD_WF11TO8_WF8_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF8_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF11TO8_WF9_SHIFT (8) /* Bits 8-15: Waveform control field 9 segment bits */
|
||||
#define LCD_WF11TO8_WF9_MASK (0xff << LCD_WF11TO8_WF9_SHIFT)
|
||||
# define LCD_WF11TO8_WF9_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF9_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF11TO8_WF10_SHIFT (16) /* Bits 16-23: Waveform control field 10 segment bits */
|
||||
#define LCD_WF11TO8_WF10_MASK (0xff << LCD_WF11TO8_WF10_SHIFT)
|
||||
# define LCD_WF11TO8_WF10_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF10_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF11TO8_WF11_SHIFT (24) /* Bits 24-31: Waveform control field 11 segment bits */
|
||||
#define LCD_WF11TO8_WF11_MASK (0xff << LCD_WF11TO8_WF11_SHIFT)
|
||||
# define LCD_WF11TO8_WF11_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF11_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF15TO12_WF12_SHIFT (0) /* Bits 0-7: Waveform control field 12 segment bits */
|
||||
#define LCD_WF15TO12_WF12_MASK (0xff << LCD_WF15TO12_WF12_SHIFT)
|
||||
# define LCD_WF15TO12_WF12_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF12_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF15TO12_WF13_SHIFT (8) /* Bits 8-15: Waveform control field 13 segment bits */
|
||||
#define LCD_WF15TO12_WF13_MASK (0xff << LCD_WF15TO12_WF13_SHIFT)
|
||||
# define LCD_WF15TO12_WF13_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF13_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF15TO12_WF14_SHIFT (16) /* Bits 16-23: Waveform control field 14 segment bits */
|
||||
#define LCD_WF15TO12_WF14_MASK (0xff << LCD_WF15TO12_WF14_SHIFT)
|
||||
# define LCD_WF15TO12_WF14_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF14_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF15TO12_WF15_SHIFT (24) /* Bits 24-31: Waveform control field 15 segment bits */
|
||||
#define LCD_WF15TO12_WF15_MASK (0xff << LCD_WF15TO12_WF15_SHIFT)
|
||||
# define LCD_WF15TO12_WF15_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF15_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF19TO16_WF16_SHIFT (0) /* Bits 0-7: Waveform control field 16 segment bits */
|
||||
#define LCD_WF19TO16_WF16_MASK (0xff << LCD_WF19TO16_WF16_SHIFT)
|
||||
# define LCD_WF19TO16_WF16_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF16_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF19TO16_WF17_SHIFT (8) /* Bits 8-15: Waveform control field 17 segment bits */
|
||||
#define LCD_WF19TO16_WF17_MASK (0xff << LCD_WF19TO16_WF17_SHIFT)
|
||||
# define LCD_WF19TO16_WF17_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF17_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF19TO16_WF18_SHIFT (16) /* Bits 16-23: Waveform control field 18 segment bits */
|
||||
#define LCD_WF19TO16_WF18_MASK (0xff << LCD_WF19TO16_WF18_SHIFT)
|
||||
# define LCD_WF19TO16_WF18_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF18_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF19TO16_WF19_SHIFT (24) /* Bits 24-31: Waveform control field 19 segment bits */
|
||||
#define LCD_WF19TO16_WF19_MASK (0xff << LCD_WF19TO16_WF19_SHIFT)
|
||||
# define LCD_WF19TO16_WF19_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF19_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF23TO20_WF20_SHIFT (0) /* Bits 0-7: Waveform control field 20 segment bits */
|
||||
#define LCD_WF23TO20_WF20_MASK (0xff << LCD_WF23TO20_WF20_SHIFT)
|
||||
# define LCD_WF23TO20_WF20_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF20_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF23TO20_WF21_SHIFT (8) /* Bits 8-15: Waveform control field 21 segment bits */
|
||||
#define LCD_WF23TO20_WF21_MASK (0xff << LCD_WF23TO20_WF21_SHIFT)
|
||||
# define LCD_WF23TO20_WF21_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF21_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF23TO20_WF22_SHIFT (16) /* Bits 16-23: Waveform control field 22 segment bits */
|
||||
#define LCD_WF23TO20_WF22_MASK (0xff << LCD_WF23TO20_WF22_SHIFT)
|
||||
# define LCD_WF23TO20_WF22_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF22_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF23TO20_WF23_SHIFT (24) /* Bits 24-31: Waveform control field 23 segment bits */
|
||||
#define LCD_WF23TO20_WF23_MASK (0xff << LCD_WF23TO20_WF23_SHIFT)
|
||||
# define LCD_WF23TO20_WF23_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF23_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF27TO24_WF24_SHIFT (0) /* Bits 0-7: Waveform control field 24 segment bits */
|
||||
#define LCD_WF27TO24_WF24_MASK (0xff << LCD_WF27TO24_WF24_SHIFT)
|
||||
# define LCD_WF27TO24_WF24_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF24_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF27TO24_WF25_SHIFT (8) /* Bits 8-15: Waveform control field 25 segment bits */
|
||||
#define LCD_WF27TO24_WF25_MASK (0xff << LCD_WF27TO24_WF25_SHIFT)
|
||||
# define LCD_WF27TO24_WF25_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF25_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF27TO24_WF26_SHIFT (16) /* Bits 16-23: Waveform control field 26 segment bits */
|
||||
#define LCD_WF27TO24_WF26_MASK (0xff << LCD_WF27TO24_WF26_SHIFT)
|
||||
# define LCD_WF27TO24_WF26_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF26_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF27TO24_WF27_SHIFT (24) /* Bits 24-31: Waveform control field 27 segment bits */
|
||||
#define LCD_WF27TO24_WF27_MASK (0xff << LCD_WF27TO24_WF27_SHIFT)
|
||||
# define LCD_WF27TO24_WF27_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF27_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF31TO28_WF28_SHIFT (0) /* Bits 0-7: Waveform control field 28 segment bits */
|
||||
#define LCD_WF31TO28_WF28_MASK (0xff << LCD_WF31TO28_WF28_SHIFT)
|
||||
# define LCD_WF31TO28_WF28_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF28_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF31TO28_WF29_SHIFT (8) /* Bits 8-15: Waveform control field 29 segment bits */
|
||||
#define LCD_WF31TO28_WF29_MASK (0xff << LCD_WF31TO28_WF29_SHIFT)
|
||||
# define LCD_WF31TO28_WF29_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF29_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF31TO28_WF30_SHIFT (16) /* Bits 16-23: Waveform control field 30 segment bits */
|
||||
#define LCD_WF31TO28_WF30_MASK (0xff << LCD_WF31TO28_WF30_SHIFT)
|
||||
# define LCD_WF31TO28_WF30_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF30_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF31TO28_WF31_SHIFT (24) /* Bits 24-31: Waveform control field 31 segment bits */
|
||||
#define LCD_WF31TO28_WF31_MASK (0xff << LCD_WF31TO28_WF31_SHIFT)
|
||||
# define LCD_WF31TO28_WF31_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF31_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF35TO32_WF32_SHIFT (0) /* Bits 0-7: Waveform control field 32 segment bits */
|
||||
#define LCD_WF35TO32_WF32_MASK (0xff << LCD_WF35TO32_WF32_SHIFT)
|
||||
# define LCD_WF35TO32_WF32_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF32_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF35TO32_WF33_SHIFT (8) /* Bits 8-15: Waveform control field 33 segment bits */
|
||||
#define LCD_WF35TO32_WF33_MASK (0xff << LCD_WF35TO32_WF33_SHIFT)
|
||||
# define LCD_WF35TO32_WF33_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF33_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF35TO32_WF34_SHIFT (16) /* Bits 16-23: Waveform control field 34 segment bits */
|
||||
#define LCD_WF35TO32_WF34_MASK (0xff << LCD_WF35TO32_WF34_SHIFT)
|
||||
# define LCD_WF35TO32_WF34_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF34_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF35TO32_WF35_SHIFT (24) /* Bits 24-31: Waveform control field 35 segment bits */
|
||||
#define LCD_WF35TO32_WF35_MASK (0xff << LCD_WF35TO32_WF35_SHIFT)
|
||||
# define LCD_WF35TO32_WF35_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF35_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF39TO36_WF36_SHIFT (0) /* Bits 0-7: Waveform control field 36 segment bits */
|
||||
#define LCD_WF39TO36_WF36_MASK (0xff << LCD_WF39TO36_WF36_SHIFT)
|
||||
# define LCD_WF39TO36_WF36_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF36_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF39TO36_WF37_SHIFT (8) /* Bits 8-15: Waveform control field 37 segment bits */
|
||||
#define LCD_WF39TO36_WF37_MASK (0xff << LCD_WF39TO36_WF37_SHIFT)
|
||||
# define LCD_WF39TO36_WF37_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF37_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF39TO36_WF38_SHIFT (16) /* Bits 16-23: Waveform control field 38 segment bits */
|
||||
#define LCD_WF39TO36_WF38_MASK (0xff << LCD_WF39TO36_WF38_SHIFT)
|
||||
# define LCD_WF39TO36_WF38_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF38_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF39TO36_WF39_SHIFT (24) /* Bits 24-31: Waveform control field 39 segment bits */
|
||||
#define LCD_WF39TO36_WF39_MASK (0xff << LCD_WF39TO36_WF39_SHIFT)
|
||||
# define LCD_WF39TO36_WF39_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF39_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF43TO40_WF40_SHIFT (0) /* Bits 0-7: Waveform control field 40 segment bits */
|
||||
#define LCD_WF43TO40_WF40_MASK (0xff << LCD_WF43TO40_WF40_SHIFT)
|
||||
# define LCD_WF43TO40_WF40_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF40_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF43TO40_WF41_SHIFT (8) /* Bits 8-15: Waveform control field 41 segment bits */
|
||||
#define LCD_WF43TO40_WF41_MASK (0xff << LCD_WF43TO40_WF41_SHIFT)
|
||||
# define LCD_WF43TO40_WF41_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF41_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF43TO40_WF42_SHIFT (16) /* Bits 16-23: Waveform control field 42 segment bits */
|
||||
#define LCD_WF43TO40_WF42_MASK (0xff << LCD_WF43TO40_WF42_SHIFT)
|
||||
# define LCD_WF43TO40_WF42_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF42_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF43TO40_WF43_SHIFT (24) /* Bits 24-31: Waveform control field 43 segment bits */
|
||||
#define LCD_WF43TO40_WF43_MASK (0xff << LCD_WF43TO40_WF43_SHIFT)
|
||||
# define LCD_WF43TO40_WF43_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF43_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF47TO44_WF44_SHIFT (0) /* Bits 0-7: Waveform control field 44 segment bits */
|
||||
#define LCD_WF47TO44_WF44_MASK (0xff << LCD_WF47TO44_WF44_SHIFT)
|
||||
# define LCD_WF47TO44_WF44_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF44_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF47TO44_WF45_SHIFT (8) /* Bits 8-15: Waveform control field 45 segment bits */
|
||||
#define LCD_WF47TO44_WF45_MASK (0xff << LCD_WF47TO44_WF45_SHIFT)
|
||||
# define LCD_WF47TO44_WF45_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF45_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF47TO44_WF46_SHIFT (16) /* Bits 16-23: Waveform control field 46 segment bits */
|
||||
#define LCD_WF47TO44_WF46_MASK (0xff << LCD_WF47TO44_WF46_SHIFT)
|
||||
# define LCD_WF47TO44_WF46_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF46_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF47TO44_WF47_SHIFT (24) /* Bits 24-31: Waveform control field 47 segment bits */
|
||||
#define LCD_WF47TO44_WF47_MASK (0xff << LCD_WF47TO44_WF47_SHIFT)
|
||||
# define LCD_WF47TO44_WF47_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF47_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF51TO48_WF48_SHIFT (0) /* Bits 0-7: Waveform control field 48 segment bits */
|
||||
#define LCD_WF51TO48_WF48_MASK (0xff << LCD_WF51TO48_WF48_SHIFT)
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# define LCD_WF51TO48_WF48_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF48_SHIFT) /* Segment n, n=0..7 */
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#define LCD_WF51TO48_WF49_SHIFT (8) /* Bits 8-15: Waveform control field 49 segment bits */
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#define LCD_WF51TO48_WF49_MASK (0xff << LCD_WF51TO48_WF49_SHIFT)
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# define LCD_WF51TO48_WF49_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF49_SHIFT) /* Segment n, n=0..7 */
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#define LCD_WF51TO48_WF50_SHIFT (16) /* Bits 16-23: Waveform control field 50 segment bits */
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#define LCD_WF51TO48_WF50_MASK (0xff << LCD_WF51TO48_WF50_SHIFT)
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# define LCD_WF51TO48_WF50_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF50_SHIFT) /* Segment n, n=0..7 */
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#define LCD_WF51TO48_WF51_SHIFT (24) /* Bits 24-31: Waveform control field 51 segment bits */
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||||
#define LCD_WF51TO48_WF51_MASK (0xff << LCD_WF51TO48_WF51_SHIFT)
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# define LCD_WF51TO48_WF51_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF51_SHIFT) /* Segment n, n=0..7 */
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||||
#define LCD_WF55TO52_WF52_SHIFT (0) /* Bits 0-7: Waveform control field 52 segment bits */
|
||||
#define LCD_WF55TO52_WF52_MASK (0xff << LCD_WF55TO52_WF52_SHIFT)
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||||
# define LCD_WF55TO52_WF52_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF52_SHIFT) /* Segment n, n=0..7 */
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||||
#define LCD_WF55TO52_WF53_SHIFT (8) /* Bits 8-15: Waveform control field 53 segment bits */
|
||||
#define LCD_WF55TO52_WF53_MASK (0xff << LCD_WF55TO52_WF53_SHIFT)
|
||||
# define LCD_WF55TO52_WF53_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF53_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF55TO52_WF54_SHIFT (16) /* Bits 16-23: Waveform control field 54 segment bits */
|
||||
#define LCD_WF55TO52_WF54_MASK (0xff << LCD_WF55TO52_WF54_SHIFT)
|
||||
# define LCD_WF55TO52_WF54_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF54_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF55TO52_WF55_SHIFT (24) /* Bits 24-31: Waveform control field 55 segment bits */
|
||||
#define LCD_WF55TO52_WF55_MASK (0xff << LCD_WF55TO52_WF55_SHIFT)
|
||||
# define LCD_WF55TO52_WF55_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF55_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF59TO56_WF56_SHIFT (0) /* Bits 0-7: Waveform control field 56 segment bits */
|
||||
#define LCD_WF59TO56_WF56_MASK (0xff << LCD_WF59TO56_WF56_SHIFT)
|
||||
# define LCD_WF59TO56_WF56_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF56_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF59TO56_WF57_SHIFT (8) /* Bits 8-15: Waveform control field 57 segment bits */
|
||||
#define LCD_WF59TO56_WF57_MASK (0xff << LCD_WF59TO56_WF57_SHIFT)
|
||||
# define LCD_WF59TO56_WF57_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF57_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF59TO56_WF58_SHIFT (16) /* Bits 16-23: Waveform control field 58 segment bits */
|
||||
#define LCD_WF59TO56_WF58_MASK (0xff << LCD_WF59TO56_WF58_SHIFT)
|
||||
# define LCD_WF59TO56_WF58_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF58_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF59TO56_WF59_SHIFT (24) /* Bits 24-31: Waveform control field 59 segment bits */
|
||||
#define LCD_WF59TO56_WF59_MASK (0xff << LCD_WF59TO56_WF59_SHIFT)
|
||||
# define LCD_WF59TO56_WF59_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF59_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
#define LCD_WF63TO60_WF60_SHIFT (0) /* Bits 0-7: Waveform control field 60 segment bits */
|
||||
#define LCD_WF63TO60_WF60_MASK (0xff << LCD_WF63TO60_WF60_SHIFT)
|
||||
# define LCD_WF63TO60_WF60_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF60_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF63TO60_WF61_SHIFT (8) /* Bits 8-15: Waveform control field 61 segment bits */
|
||||
#define LCD_WF63TO60_WF61_MASK (0xff << LCD_WF63TO60_WF61_SHIFT)
|
||||
# define LCD_WF63TO60_WF61_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF61_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF63TO60_WF62_SHIFT (16) /* Bits 16-23: Waveform control field 62 segment bits */
|
||||
#define LCD_WF63TO60_WF62_MASK (0xff << LCD_WF63TO60_WF62_SHIFT)
|
||||
# define LCD_WF63TO60_WF62_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF62_SHIFT) /* Segment n, n=0..7 */
|
||||
#define LCD_WF63TO60_WF63_SHIFT (24) /* Bits 24-31: Waveform control field 63 segment bits */
|
||||
#define LCD_WF63TO60_WF63_MASK (0xff << LCD_WF63TO60_WF63_SHIFT)
|
||||
# define LCD_WF63TO60_WF63_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF63_SHIFT) /* Segment n, n=0..7 */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
Loading…
Reference in New Issue
Block a user