Initial SSI debug
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1822 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -60,6 +60,20 @@
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* Definitions
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****************************************************************************/
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/* Enables debug output from this file (needs CONFIG_DEBUG with
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* CONFIG_DEBUG_VERBOSE too)
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*/
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#undef SSI_DEBUG /* Define to enable debug */
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#ifdef SSI_DEBUG
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# define ssidbg lldbg
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# define ssivdbg llvdbg
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#else
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# define ssidbg(x...)
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# define ssivdbg(x...)
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#endif
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/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
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* modules (others may support more -- in such case, the following must be
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* expanded).
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@ -181,7 +195,7 @@ static void ssi_rxnull(struct lm32_ssidev_s *priv);
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static void ssi_rxuint16(struct lm32_ssidev_s *priv);
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static void ssi_rxubyte(struct lm32_ssidev_s *priv);
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static inline boolean ssi_txfifofull(struct lm32_ssidev_s *priv);
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static inline boolean ssi_rxfifonotempty(struct lm32_ssidev_s *priv);
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static inline boolean ssi_rxfifoempty(struct lm32_ssidev_s *priv);
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static int ssi_performtx(struct lm32_ssidev_s *priv);
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static inline void ssi_performrx(struct lm32_ssidev_s *priv);
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static int ssi_transfer(struct lm32_ssidev_s *priv, const void *txbuffer,
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@ -341,6 +355,7 @@ static uint32 ssi_disable(struct lm32_ssidev_s *priv)
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retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
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regval = (retval & ~SSI_CR1_SSE);
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ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
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ssivdbg("CR1: %08x\n", regval);
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return retval;
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}
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@ -364,6 +379,7 @@ static void ssi_enable(struct lm32_ssidev_s *priv, uint32 enable)
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regval &= ~SSI_CR1_SSE;
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regval |= (enable & SSI_CR1_SSE);
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ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
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ssivdbg("CR1: %08x\n", regval);
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}
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/****************************************************************************
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@ -467,7 +483,7 @@ static void ssi_rxubyte(struct lm32_ssidev_s *priv)
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* Name: ssi_txfifofull
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*
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* Description:
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* Return TRUE if the Tx FIFO is not full
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* Return TRUE if the Tx FIFO is full
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*
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* Input Parameters:
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* priv - Device-specific state data
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@ -479,14 +495,14 @@ static void ssi_rxubyte(struct lm32_ssidev_s *priv)
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static inline boolean ssi_txfifofull(struct lm32_ssidev_s *priv)
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{
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return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) != 0;
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return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
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}
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/****************************************************************************
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* Name: ssi_rxfifonotempty
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* Name: ssi_rxfifoempty
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*
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* Description:
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* Return TRUE if the Rx FIFO is not empty
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* Return TRUE if the Rx FIFO is empty
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*
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* Input Parameters:
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* priv - Device-specific state data
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@ -496,9 +512,9 @@ static inline boolean ssi_txfifofull(struct lm32_ssidev_s *priv)
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*
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****************************************************************************/
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static inline boolean ssi_rxfifonotempty(struct lm32_ssidev_s *priv)
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static inline boolean ssi_rxfifoempty(struct lm32_ssidev_s *priv)
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{
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return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) != 0;
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return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
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}
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/****************************************************************************
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@ -555,7 +571,7 @@ static int ssi_performtx(struct lm32_ssidev_s *priv)
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*/
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#ifdef CONFIG_DEBUG
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regval |= (SSI_IM_TX|SSI_RIS_ROR)
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regval |= (SSI_IM_TX|SSI_RIS_ROR);
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#else
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regval |= SSI_IM_TX;
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#endif
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@ -597,7 +613,7 @@ static inline void ssi_performrx(struct lm32_ssidev_s *priv)
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/* Loop while data is available in the Rx FIFO */
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while (ssi_rxfifonotempty(priv))
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while (!ssi_rxfifoempty(priv))
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{
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/* Have all of the requested words been transferred from the Rx FIFO? */
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@ -671,6 +687,7 @@ static int ssi_transfer(struct lm32_ssidev_s *priv, const void *txbuffer,
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#endif
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int ntxd;
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ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
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ssi_semtake(&priv->exclsem);
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/* Set up to perform the transfer */
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@ -707,24 +724,40 @@ static int ssi_transfer(struct lm32_ssidev_s *priv, const void *txbuffer,
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/* Prime the Tx FIFO to start the sequence (saves one interrupt).
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* At this point, all SSI interrupts should be disabled, but the
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* operation of ssi_performtx() will set up the interrupts
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* approapriately.
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* approapriately (if nwords > TxFIFO size).
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*/
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#ifndef CONFIG_SSI_POLLWAIT
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flags = irqsave();
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ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
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priv->ntxwords, priv->nrxwords, priv->nwords,
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ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
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ntxd = ssi_performtx(priv);
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/* For the case where nwords < Tx FIFO size, ssi_performrx will
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* configure interrupts correctly for the final phase of the
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* the transfer.
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*/
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ssi_performrx(priv);
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ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
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priv->ntxwords, priv->nrxwords, priv->nwords,
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ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
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ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
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/* Wait for the transfer to complete. Since there is no handshake
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* with SPI, the following should complete even if there are problems
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* with the transfer, so it should be safe with no timeout.
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*/
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ssivdbg("Waiting for transfer complete\n");
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irqrestore(flags);
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do
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{
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ssi_semtake(&priv->xfrsem);
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}
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while (priv->nrxwords < priv->nwords);
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ssidbg("Transfer complete\n");
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#else
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/* Perform the transfer using polling logic. This will totally
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@ -832,6 +865,10 @@ static int ssi_interrupt(int irq, void *context)
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}
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#endif
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ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
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priv->ntxwords, priv->nrxwords, priv->nwords,
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ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
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/* Handle outgoing Tx FIFO transfers */
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ntxd = ssi_performtx(priv);
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@ -840,6 +877,11 @@ static int ssi_interrupt(int irq, void *context)
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ssi_performrx(priv);
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ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
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priv->ntxwords, priv->nrxwords, priv->nwords,
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ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
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ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
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/* Check if the transfer is complete */
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if (priv->nrxwords >= priv->nwords)
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@ -850,6 +892,7 @@ static int ssi_interrupt(int irq, void *context)
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/* Wake up the waiting thread */
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ssidbg("Transfer complete\n");
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ssi_semgive(&priv->xfrsem);
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}
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return OK;
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@ -878,6 +921,7 @@ static void ssi_setfrequencyinternal(struct lm32_ssidev_s *priv, uint32 frequenc
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uint32 regval;
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uint32 scr;
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ssidbg("frequency: %d\n", frequency);
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if (priv && frequency != priv->frequency)
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{
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/* "The serial bit rate is derived by dividing down the input clock
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@ -934,7 +978,7 @@ static void ssi_setfrequencyinternal(struct lm32_ssidev_s *priv, uint32 frequenc
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/* Set CPDVSR */
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DEBUGASSERT(cpdvsr < 255);
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DEBUGASSERT(cpsdvsr < 255);
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ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
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/* Set SCR */
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@ -943,6 +987,7 @@ static void ssi_setfrequencyinternal(struct lm32_ssidev_s *priv, uint32 frequenc
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regval &= ~SSI_CR0_SCR_MASK;
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regval |= (scr << SSI_CR0_SCR_SHIFT);
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ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
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ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
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/* Calcluate the actual frequency */
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@ -985,7 +1030,7 @@ static void ssi_setmodeinternal(struct lm32_ssidev_s *priv, enum spi_mode_e mode
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uint32 modebits;
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uint32 regval;
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ssi_semtake(&priv->exclsem);
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ssidbg("mode: %d\n", mode);
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if (priv && mode != priv->mode)
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{
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/* Select the CTL register bits based on the selected mode */
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@ -1018,6 +1063,7 @@ static void ssi_setmodeinternal(struct lm32_ssidev_s *priv, enum spi_mode_e mode
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regval &= ~SSI_CR0_FRF_MASK;
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regval |= modebits;
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ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
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ssivdbg("CR0: %08x\n", regval);
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}
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}
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@ -1054,13 +1100,14 @@ static void ssi_setbitsinternal(struct lm32_ssidev_s *priv, int nbits)
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{
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uint32 regval;
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ssi_semtake(&priv->exclsem);
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ssidbg("nbits: %d\n", nbits);
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if (priv && nbits != priv->nbits && nbits >=4 && nbits <= 16)
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{
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regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
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regval &= ~SSI_CR0_DSS_MASK;
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regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
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ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
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ssivdbg("CR0: %08x\n", regval);
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priv->nbits = nbits;
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}
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@ -1220,6 +1267,8 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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irqstate_t flags;
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ubyte regval;
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ssidbg("port: %d\n", port);
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/* Set up for the selected port */
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flags = irqsave();
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@ -1236,6 +1285,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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regval = getreg32(LM3S_SYSCON_RCGC1);
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regval |= SYSCON_RCGC1_SSI0;
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putreg32(regval, LM3S_SYSCON_RCGC1);
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ssivdbg("RCGC1: %08x\n", regval);
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/* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
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* logic in this file makes no assumptions about chip select)
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@ -1259,6 +1309,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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regval = getreg32(LM3S_SYSCON_RCGC1);
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regval |= SYSCON_RCGC1_SSI1;
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putreg32(regval, LM3S_SYSCON_RCGC1);
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ssivdbg("RCGC1: %08x\n", regval);
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/* Configure SSI1 GPIOs */
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@ -1289,19 +1340,28 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
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/* Set the initial mode to mode 0 */
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/* Set the initial mode to mode 0. The application may override
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* this initial setting using the setmode() method.
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*/
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ssi_setmodeinternal(priv, SPIDEV_MODE0);
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/* Set the initial data width to 8-bits */
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/* Set the initial data width to 8-bits. The application may
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* override this initial setting using the setbits() method.
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*/
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ssi_setbitsinternal(priv, 8);
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/* Set the initialize clock frequency for detection */
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/* Pick some initialize clock frequency. 400,000Hz is the startup
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* MMC/SD frequency used for card detection. The application may
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* override this setting using the setfrequency() method.
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*/
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ssi_setfrequencyinternal(priv, 400000);
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/* Disable all SSI interrupt sources */
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/* Disable all SSI interrupt sources. They will be enabled only
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* while there is an SSI transfer in progress.
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*/
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ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
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