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Merge branch 'master' of bitbucket.org:pnb990/nuttx-kernel-arch

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This commit is contained in:
pnb 2015-12-22 13:28:39 +01:00
commit 0ef3dc81aa
5 changed files with 1370 additions and 524 deletions
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130
arch/arm/src/stm32/Kconfig
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@ -5120,6 +5120,136 @@ config STM32_TIM14_DAC2
endchoice
config STM32_TIM1_CAP
bool "TIM1 Capture
default n
depends on STM32_HAVE_TIM1
---help---
Reserve timer 1 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM1_CAP
bool "TIM1 Capture
default n
depends on STM32_HAVE_TIM1
---help---
Reserve timer 1 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM2_CAP
bool "TIM2 Capture
default n
depends on STM32_HAVE_TIM2
---help---
Reserve timer 2 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM3_CAP
bool "TIM3 Capture
default n
depends on STM32_HAVE_TIM3
---help---
Reserve timer 3 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM4_CAP
bool "TIM4 Capture
default n
depends on STM32_HAVE_TIM4
---help---
Reserve timer 4 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM5_CAP
bool "TIM5 Capture
default n
depends on STM32_HAVE_TIM5
---help---
Reserve timer 5 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM8_CAP
bool "TIM8 Capture
default n
depends on STM32_HAVE_TIM8
---help---
Reserve timer 8 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM9_CAP
bool "TIM9 Capture
default n
depends on STM32_HAVE_TIM9
---help---
Reserve timer 9 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM10_CAP
bool "TIM10 Capture
default n
depends on STM32_HAVE_TIM10
---help---
Reserve timer 10 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM11_CAP
bool "TIM11 Capture
default n
depends on STM32_HAVE_TIM11
---help---
Reserve timer 11 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM12_CAP
bool "TIM12 Capture
default n
depends on STM32_HAVE_TIM12
---help---
Reserve timer 12 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM13_CAP
bool "TIM13 Capture
default n
depends on STM32_HAVE_TIM13
---help---
Reserve timer 13 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM14_CAP
bool "TIM14 Capture
default n
depends on STM32_HAVE_TIM14
---help---
Reserve timer 14 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
menu "ADC Configuration"
depends on STM32_ADC

804
arch/arm/src/stm32/stm32_capture.c Normal file
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@ -0,0 +1,804 @@
/************************************************************************************
* arm/arm/src/stm32/stm32_capture.c
*
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
* Author: Bouteville Pierre-Noel <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <debug.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_internal.h"
#include "up_arch.h"
#include "stm32.h"
#include "stm32_gpio.h"
#include "stm32_capture.h"
/************************************************************************************
* Private Types
************************************************************************************/
/* Configuration ********************************************************************/
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \
defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \
defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN)
# define HAVE_CH1IN 1
#endif
#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \
defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \
defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN)
# define HAVE_CH2IN 1
#endif
#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \
defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN)
# define HAVE_CH3IN 1
#endif
#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \
defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN)
# define HAVE_CH4IN 1
#endif
#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM1_CAP)
#define HAVE_ADANCED_TIM 1
#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
*/
#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \
defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || defined(CONFIG_STM32_TIM8_CAP) || \
defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || defined(CONFIG_STM32_TIM11_CAP) || \
defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP)
/************************************************************************************
* Private Types
************************************************************************************/
/* TIM Device Structure */
struct stm32_cap_priv_s
{
const struct stm32_cap_ops_s *ops;
const uint32_t base; /* TIMn base address */
const int irq; /* irq vector */
#define HAVE_ADANCED_TIM 1
const int irq_of; /* irq timer overflow is deferent in advanced timer */
#endif
};
/************************************************************************************
* Private Functions
************************************************************************************/
/* Get a 16-bit register value by offset */
static inline uint16_t stm32_getreg16(FAR struct stm32_cap_priv_s *priv,
uint8_t offset)
{
return getreg16(priv->base + offset);
}
/* Put a 16-bit register value by offset */
static inline void stm32_putreg16(FAR struct stm32_cap_priv_s *priv, uint8_t offset,
uint16_t value)
{
putreg16(value, priv->base + offset);
}
/* Modify a 16-bit register value by offset */
static inline void stm32_modifyreg16(FAR struct stm32_cap_priv_s *priv,
uint8_t offset, uint16_t clearbits,
uint16_t setbits)
{
modifyreg16(priv->base + offset, clearbits, setbits);
}
/* Get a 32-bit register value by offset. This applies only for the STM32 F4
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/
static inline uint32_t stm32_getreg32(FAR struct stm32_cap_priv_s *priv,
uint8_t offset)
{
return getreg32(priv->base + offset);
}
/* Put a 32-bit register value by offset. This applies only for the STM32 F4
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/
static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t offset,
uint32_t value)
{
putreg32(value, priv->base + offset);
}
/************************************************************************************
* gpio Functions
************************************************************************************/
static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int channel)
{
switch(priv->base)
{
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
#if defined(GPIO_TIM1_CH1IN)
case 0: return GPIO_TIM1_CH1IN;
#endif
#if defined(GPIO_TIM1_CH2IN)
case 1: return GPIO_TIM1_CH2IN;
#endif
#if defined(GPIO_TIM1_CH3IN)
case 2: return GPIO_TIM1_CH3IN;
#endif
#if defined(GPIO_TIM1_CH4IN)
case 3: return GPIO_TIM1_CH4IN;
#endif
}
break;
#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
#if defined(GPIO_TIM2_CH1IN)
case 0: return GPIO_TIM2_CH1IN;
#endif
#if defined(GPIO_TIM2_CH2IN)
case 1: return GPIO_TIM2_CH2IN;
#endif
#if defined(GPIO_TIM2_CH3IN)
case 2: return GPIO_TIM2_CH3IN;
#endif
#if defined(GPIO_TIM2_CH4IN)
case 3: return GPIO_TIM2_CH4IN;
#endif
}
break;
#endif
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
#if defined(GPIO_TIM3_CH1IN)
case 0: return GPIO_TIM3_CH1IN;
#endif
#if defined(GPIO_TIM3_CH2IN)
case 1: return GPIO_TIM3_CH2IN;
#endif
#if defined(GPIO_TIM3_CH3IN)
case 2: return GPIO_TIM3_CH3IN;
#endif
#if defined(GPIO_TIM3_CH4IN)
case 3: return GPIO_TIM3_CH4IN;
#endif
}
break;
#endif
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
#if defined(GPIO_TIM4_CH1IN)
case 0: return GPIO_TIM4_CH1IN;
#endif
#if defined(GPIO_TIM4_CH2IN)
case 1: return GPIO_TIM4_CH2IN;
#endif
#if defined(GPIO_TIM4_CH3IN)
case 2: return GPIO_TIM4_CH3IN;
#endif
#if defined(GPIO_TIM4_CH4IN)
case 3: return GPIO_TIM4_CH4IN;
#endif
}
break;
#endif
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
#if defined(GPIO_TIM5_CH1IN)
case 0: return GPIO_TIM5_CH1IN;
#endif
#if defined(GPIO_TIM5_CH2IN)
case 1: return GPIO_TIM5_CH2IN;
#endif
#if defined(GPIO_TIM5_CH3IN)
case 2: return GPIO_TIM5_CH3IN;
#endif
#if defined(GPIO_TIM5_CH4IN)
case 3: return GPIO_TIM5_CH4IN;
#endif
}
break;
#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
#if defined(GPIO_TIM8_CH1IN)
case 0: return GPIO_TIM8_CH1OUIN ;
#endif
#if defined(GPIO_TIM8_CH2IN)
case 1: return GPIO_TIM8_CH2OUIN ;
#endif
#if defined(GPIO_TIM8_CH3IN)
case 2: return GPIO_TIM8_CH3OUIN ;
#endif
#if defined(GPIO_TIM8_CH4IN)
case 3: return GPIO_TIM8_CH4OUIN ;
#endif
}
break;
#endif
}
return gpio;
}
/************************************************************************************
* Basic Functions
************************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src,
uint32_t prescaler)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
if (prescaler == 0)
{
//disable Timer
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,ATIM_CR1_CEN,0);
return 0;
}
/* We need to decrement value for '1', but only, if we are allowed to
* not to cause underflow. Check for overflow.
*/
if (prescaler > 0)
prescaler--;
if (prescaler > 0xffff)
prescaler = 0xffff;
switch(clk_src)
{
case STM32_CAP_CLK_INT:
regval = GTIM_SMCR_DISAB;
break;
case STM32_CAP_CLK_EXT:
regval = GTIM_SMCR_EXTCLK1
break;
/* TODO: Add other case */
default:
return ERROR;
}
stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval );
// Set Maximum
stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, period);
// Set prescaler
stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler);
//reset counter timer
stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET,0,BTIM_EGR_UG);
//enable timer
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,0,BTIM_CR1_CEN);
#ifdef HAVE_ADANCED_TIM
/* Advanced registers require Main Output Enable */
if ((priv->base == STM32_TIM1_BASE) || (priv->base == STM32_TIM8_BASE))
{
stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
}
#endif
return prescaler;
}
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
int irq;
#ifdef HAVE_ADANCED_TIM
int irq_of;
#endif
ASSERT(dev);
irq = priv->irq;
#ifdef HAVE_ADANCED_TIM
irq_of = priv->irq_of;
#endif
/* Disable interrupt when callback is removed */
if (!handler)
{
up_disable_irq(irq);
irq_detach(irq);
#ifdef HAVE_ADANCED_TIM
if (priv->irq_of)
{
up_disable_irq(irq_of);
irq_detach(irq_of);
}
#endif
return OK;
}
/* Otherwise set callback and enable interrupt */
irq_attach(irq, handler);
up_enable_irq(irq);
#ifdef HAVE_ADANCED_TIM
if (priv->irq_of)
{
irq_attach(priv->irq_of, handler);
up_enable_irq(priv->irq_of);
}
#endif
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
# ifdef HAVE_ADANCED_TIM
if (priv->irq_of)
{
up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
}
# endif
#endif
return OK;
}
static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
stm32_cap_flags_t src, bool on)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint16_t mask;
ASSERT(dev);
if (src & STM32_TIM_FLAG_IRQ_OVERFLOW)
regval |= ATIM_DIER_UIE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1)
regval |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2)
regval |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3)
regval |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4)
regval |= ATIM_DIER_CC1IE;
/* Not IRQ on channel overflow */
if (on)
stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,0,mask);
else
stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,mask,0);
}
static void stm32_cap_ackflags(FAR struct stm32_cap_dev_s *dev, int src)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint16_t mask = 0;
if (src & STM32_TIM_FLAG_IRQ_OVERFLOW)
regval |= ATIM_SR_UIF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1)
regval |= ATIM_SR_CC1IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2)
regval |= ATIM_SR_CC2IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3)
regval |= ATIM_SR_CC3IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4)
regval |= ATIM_SR_CC4IF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_1)
regval |= ATIM_SR_CC1OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_2)
regval |= ATIM_SR_CC2OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_3)
regval |= ATIM_SR_CC3OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_4)
regval |= ATIM_SR_CC4OF;
stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask);
}
static stm32_cap_flags_t stm32_cap_getint(FAR struct stm32_cap_dev_s *dev)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
stm32_cap_flags_t src = 0;
regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET);
if (regval & ATIM_SR_UIF)
src |= STM32_TIM_FLAG_IRQ_OVERFLOW;
if (regval & ATIM_SR_CC1IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_1;
if (regval & ATIM_SR_CC2IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_2;
if (regval & ATIM_SR_CC3IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_3;
if (regval & ATIM_SR_CC4IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_4;
if (regval & ATIM_SR_CC1OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_1;
if (regval & ATIM_SR_CC2OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_2;
if (regval & ATIM_SR_CC3OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_3;
if (regval & ATIM_SR_CC4OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_4;
return src;
}
/************************************************************************************
* General Functions
************************************************************************************/
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
stm32_cap_ch_cfg_t edge)
{
int i;
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint32_t gpio = 0;
uint16_t mask;
uint16_t regval;
ASSERT(dev);
gpio = stm32_cap_gpio(priv,channel);
if ( gpio == 0 )
return ERROR;
/* change to zero base index */
channel--;
/* Set ccer */
switch (cfg & STM32_CAP_EDGE_MASK)
{
case STM32_CAP_EDGE_DISABLED:
regval = 0;
break;
case STM32_CAP_EDGE_RISING:
regval = GTIM_CCER_CC1E;
break;
case STM32_CAP_EDGE_FALLING:
regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P;
break;
case STM32_CAP_EDGE_BOTH:
regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP;
break;
default:
return ERROR;
}
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP)
mask <<= (channel << 2);
regval <<= (channel << 2);
stm32_modifyreg16(priv,mask,regval);
/* Set ccmr */
ccmr_val = cfg;
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 0 )
return ERROR; /* configured as output */
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 3 )
return ERROR; /* Not implemented */
/* Define its position (shift) and get register offset */
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK)
ccmr_val &= mask
if (channel & 1)
{
ccmr_val <<= 8;
ccmr_mask <<= 8;
}
if (channel < 2)
stm32_modifyreg16(priv,STM32_GTIM_CCMR1_OFFSET,ccmr_mask,ccmr_val);
else
stm32_modifyreg16(priv,STM32_GTIM_CCMR2_OFFSET,ccmr_mask,ccmr_val);
/* set GPIO */
if ( (cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED)
stm32_unconfiggpio(gpio);
else
stm32_configgpio(gpio);
return OK;
}
static int stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
ASSERT(dev);
switch (channel)
{
#ifdef HAVE_CH1IN
case 1:
return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 2:
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 3:
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 4:
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
#endif
}
return ERROR;
}
/************************************************************************************
* Advanced Functions
************************************************************************************/
/* TODO: Advanced functions for the STM32_ATIM */
/************************************************************************************
* Device Structures, Instantiation
************************************************************************************/
struct stm32_cap_ops_s stm32_cap_ops =
{
.setclock = &stm32_cap_setclock,
.setchannel = &stm32_cap_setchannel,
.getcapture = &stm32_cap_getcapture,
.setisr = &stm32_cap_setisr,
.enableint = &stm32_cap_enableint,
.ackflags = &stm32_cap_ackflags,
.getflags = &stm32_cap_getflags
};
#ifdef CONFIG_STM32_TIM2_CAP
const struct stm32_cap_priv_s stm32_tim2_priv =
{
.ops = &stm32_cap_ops,
.base = STM32_TIM2_BASE,
.irg = STM32_IRQ_TIM2,
#define HAVE_ADANCED_TIM 1
.irg_of = -1,
#endif
.gpio_clk = GPIO_TIM2_CLKIN;
.channels = {
#if defined(GPIO_TIM2_CH1IN)
.gpio = GPIO_TIM2_CH1IN;
#endif
#if defined(GPIO_TIM2_CH2IN)
.gpio = GPIO_TIM2_CH2IN;
.ccmr = ( GPIO_TIM2_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
#if defined(GPIO_TIM2_CH3IN)
.gpio = GPIO_TIM2_CH3IN;
.ccmr = ( GPIO_TIM2_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
#if defined(GPIO_TIM2_CH4IN)
.gpio = GPIO_TIM2_CH4IN;
.ccmr = ( GPIO_TIM2_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
}
};
#endif
/************************************************************************************
* Public Function - Initialization
************************************************************************************/
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer)
{
struct stm32_cap_priv_s *priv = NULL;
/* Get structure and enable power */
switch (timer)
{
#ifdef CONFIG_STM32_TIM1_CAP
case 1:
priv = &stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
case 2:
priv = &stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case 3:
priv = &stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case 4:
priv = &stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case 5:
priv = &stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32_TIM8_CAP
case 8:
priv = &stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
case 9:
priv = &stm32_tim9_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
default:
return NULL;
}
if (priv->gpio_clk)
stm32_configgpio(priv->gpio_clk)
// disable timer while is not configured
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
return (struct stm32_cap_dev_s *)priv;
}
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev)
{
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
ASSERT(dev);
// disable timer while is not configured
stm32_modifyreg16(dev, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
if (priv->gpio_clk)
stm32_unconfiggpio(priv->gpio_clk)
switch (priv->base)
{
#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
default:
return ERROR;
}
return OK;
}
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */

197
arch/arm/src/stm32/stm32_capture.h Normal file
View File

@ -0,0 +1,197 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_capture.h
*
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
* Author: Bouteville Pierre-Noel <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H
#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include <arch/board/board.h>
#include "chip/stm32_tim.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helpers **************************************************************************/
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
#define STM32_TIM_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on))
#define STM32_TIM_ACKFLAGS(d,s) ((d)->ops->ackflags(d,s))
#define STM32_TIM_GETFLAGS(d) ((d)->ops->getflags(d))
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Capture Device Structure */
struct stm32_cap_dev_s
{
struct stm32_cap_ops_s *ops;
};
/* Capture input EDGE sources */
typedef enum
{
/* Mapped */
STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK),
STM32_CAP_MAPPED_TI1 = (1<<GTIM_CCMR1_CC1S_SHIFT),
STM32_CAP_MAPPED_TI2 = (2<<GTIM_CCMR1_CC1S_SHIFT),
/*TODO STM32_CAP_MAPPED_TRC = (3<<GTIM_CCMR1_CC1S_SHIFT),*/
/* Event prescaler */
STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK),
STM32_CAP_INPSC_NO = (0<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_2EVENTS = (1<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_4EVENTS = (2<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_8EVENTS = (3<<GTIM_CCMR1_IC1PSC_SHIFT),
/* Event prescaler */
STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK),
STM32_CAP_FILTER_NO = (0<<GTIM_CCMR1_IC1F_SHIFT),
/* internal clock with N time to confirm event */
STM32_CAP_FILTER_INT_N2 = (1<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N4 = (2<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N8 = (3<<GTIM_CCMR1_IC1F_SHIFT),
/* DTS clock div by D with N time to confirm event */
STM32_CAP_FILTER_DTS_D2_N6 = (4<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D2_N8 = (5<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N6 = (6<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N8 = (7<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N6 = (8<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N8 = (9<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N5 = (10<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N6 = (11<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N8 = (12<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N5 = (13<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N6 = (14<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N8 = (15<<GTIM_CCMR1_IC1F_SHIFT),
/* EDGE */
STM32_CAP_EDGE_MASK = (3<<8),
STM32_CAP_EDGE_DISABLED = (0<<8),
STM32_CAP_EDGE_RISING = (1<<8),
STM32_CAP_EDGE_FALLING = (2<<8),
STM32_CAP_EDGE_BOTH = (3<<8),
} stm32_cap_ch_cfg_t;
/* TIM clock sources */
typedef enum
{
STM32_CAP_CLK_INT= 0,
STM32_CAP_CLK_EXT,
/* TODO: Add other clock */
} stm32_cap_clk_t;
/* TIM Sources */
typedef enum
{
/* One of the following */
STM32_CAP_FLAG_IRQ_TIMER = (GTIM_SR_UIF),
STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF),
STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF),
STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF),
STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF),
STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF),
STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF),
STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF),
STM32_CAP_FLAG_OF_CH_4 = (GTIM_SR_CC4OF)
} stm32_cap_flags_t;
/* TIM Operations */
struct stm32_cap_ops_s
{
int (*setclock)(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src,
uint32_t prescaler);
int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel);
int (*setisr)(FAR struct stm32_tim_dev_s *dev,xcpt_t handler);
void (*enableint)(FAR struct stm32_tim_dev_s *dev, stm32_cap_flags_t src, bool on );
};
/************************************************************************************
* Public Functions
************************************************************************************/
/* Power-up timer and get its structure */
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer);
/* Power-down timer, mark it as unused */
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */

720
arch/arm/src/stm32/stm32_tim.c
View File

@ -145,28 +145,48 @@
# undef CONFIG_STM32_TIM14
#endif
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \
defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \
defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN)
# define HAVE_CH1IN 1
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \
defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \
defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN)
# define HAVE_CH2IN 1
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \
defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN)
# define HAVE_CH3IN 1
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \
defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN)
# define HAVE_CH4IN 1
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
@ -268,6 +288,24 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
stm32_tim_disable(dev);
}
#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
{
/* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
if (mode & STM32_TIM_CH_MODE_MASK)
{
stm32_configgpio(cfg);
}
else
{
stm32_unconfiggpio(cfg);
}
}
#endif
/************************************************************************************
* Basic Functions
************************************************************************************/
@ -411,117 +449,21 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
return OK;
}
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
{
uint16_t mask;
ASSERT(dev);
if (source & STM32_TIM_INT_SRC_OVERFLOW)
regval |= ATIM_DIER_UIE;
#ifdef HAVE_CH1IN
if (source & STM32_TIM_INT_SRC_CAPTURE_1)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH2IN
if (source & STM32_TIM_INT_SRC_CAPTURE_2)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH3IN
if (source & STM32_TIM_INT_SRC_CAPTURE_3)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH4IN
if (source & STM32_TIM_INT_SRC_CAPTURE_4)
regval |= ATIM_DIER_CC1IE;
#endif
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET,0,mask);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
}
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
{
uint16_t mask;
ASSERT(dev);
if (source & STM32_TIM_INT_SRC_OVERFLOW)
regval |= ATIM_DIER_UIE;
#ifdef HAVE_CH1IN
if (source & STM32_TIM_INT_SRC_CAPTURE_1)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH2IN
if (source & STM32_TIM_INT_SRC_CAPTURE_2)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH3IN
if (source & STM32_TIM_INT_SRC_CAPTURE_3)
regval |= ATIM_DIER_CC1IE;
#endif
#ifdef HAVE_CH4IN
if (source & STM32_TIM_INT_SRC_CAPTURE_4)
regval |= ATIM_DIER_CC1IE;
#endif
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET,mask, 0);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
}
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
{
uint16_t mask = 0;
if (source & STM32_TIM_INT_SRC_OVERFLOW)
regval |= ATIM_SR_UIF;
#ifdef HAVE_CH1IN
if (source & STM32_TIM_INT_SRC_CAPTURE_1)
regval |= ATIM_SR_CC1IF;
#endif
#ifdef HAVE_CH2IN
if (source & STM32_TIM_INT_SRC_CAPTURE_2)
regval |= ATIM_SR_CC2IF;
#endif
#ifdef HAVE_CH3IN
if (source & STM32_TIM_INT_SRC_CAPTURE_3)
regval |= ATIM_SR_CC3IF;
#endif
#ifdef HAVE_CH4IN
if (source & STM32_TIM_INT_SRC_CAPTURE_4)
regval |= ATIM_SR_CC4IF;
#endif
stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~mask);
}
static int stm32_tim_getintsrc(FAR struct stm32_tim_dev_s *dev, int source)
{
uint16_t regval = 0;
int source = 0;
regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET);
if (regval & ATIM_SR_UIF)
source |= STM32_TIM_INT_SRC_OVERFLOW;
#ifdef HAVE_CH1IN
if (regval & ATIM_SR_CC1IF)
source |= STM32_TIM_INT_SRC_CAPTURE_1;
#endif
#ifdef HAVE_CH2IN
if (regval & ATIM_SR_CC2IF)
source |= STM32_TIM_INT_SRC_CAPTURE_2;
#endif
#ifdef HAVE_CH3IN
if (regval & ATIM_SR_CC3IF)
source |= STM32_TIM_INT_SRC_CAPTURE_3;
#endif
#ifdef HAVE_CH4IN
if (regval & ATIM_SR_CC4IF)
source |= STM32_TIM_INT_SRC_CAPTURE_4;
#endif
return source;
stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
}
/************************************************************************************
@ -596,8 +538,6 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode)
{
uint32_t gpio_in_cfg = 0;
uint32_t gpio_out_cfg= 0;
uint16_t ccmr_orig = 0;
uint16_t ccmr_val = 0;
uint16_t ccmr_mask = 0xff;
@ -631,327 +571,16 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
}
#endif
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM2_CH1OUT)
gpio_out_cfg = GPIO_TIM2_CH1OUT;
#endif
#if defined(GPIO_TIM2_CH1IN)
gpio_in_cfg = GPIO_TIM2_CH1IN;
ccmr_val |= ( GPIO_TIM2_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM2_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM2_CH2OUT)
gpio_out_cfg = GPIO_TIM2_CH2OUT;
#endif
#if defined(GPIO_TIM2_CH2IN)
gpio_in_cfg = GPIO_TIM2_CH2IN;
ccmr_val |= ( GPIO_TIM2_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM2_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM2_CH3OUT)
gpio_out_cfg = GPIO_TIM2_CH3OUT;
#endif
#if defined(GPIO_TIM2_CH3IN)
gpio_in_cfg = GPIO_TIM2_CH3IN;
ccmr_val |= ( GPIO_TIM2_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM2_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM2_CH4OUT)
gpio_out_cfg = GPIO_TIM2_CH4OUT;
#endif
#if defined(GPIO_TIM2_CH4IN)
gpio_in_cfg = GPIO_TIM2_CH4IN;
ccmr_val |= ( GPIO_TIM2_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM2_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default:
return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM3_CH1OUT)
gpio_out_cfg = GPIO_TIM3_CH1OUT;
#endif
#if defined(GPIO_TIM3_CH1IN)
gpio_in_cfg = GPIO_TIM3_CH1IN;
ccmr_val |= ( GPIO_TIM3_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM3_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM3_CH2OUT)
gpio_out_cfg = GPIO_TIM3_CH2OUT;
#endif
#if defined(GPIO_TIM3_CH2IN)
gpio_in_cfg = GPIO_TIM3_CH2IN;
ccmr_val |= ( GPIO_TIM3_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM3_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM3_CH3OUT)
gpio_out_cfg = GPIO_TIM3_CH3OUT;
#endif
#if defined(GPIO_TIM3_CH3IN)
gpio_in_cfg = GPIO_TIM3_CH3IN;
ccmr_val |= ( GPIO_TIM3_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM3_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM3_CH4OUT)
gpio_out_cfg = GPIO_TIM3_CH4OUT;
#endif
#if defined(GPIO_TIM3_CH4IN)
gpio_in_cfg = GPIO_TIM3_CH4IN;
ccmr_val |= ( GPIO_TIM3_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM3_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default:
return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM4_CH1OUT)
gpio_out_cfg = GPIO_TIM4_CH1OUT;
#endif
#if defined(GPIO_TIM4_CH1IN)
gpio_in_cfg = GPIO_TIM4_CH1IN;
ccmr_val |= ( GPIO_TIM4_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM4_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM4_CH2OUT)
gpio_out_cfg = GPIO_TIM4_CH2OUT;
#endif
#if defined(GPIO_TIM4_CH2IN)
gpio_in_cfg = GPIO_TIM4_CH2IN;
ccmr_val |= ( GPIO_TIM4_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM4_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM4_CH3OUT)
gpio_out_cfg = GPIO_TIM4_CH3OUT;
#endif
#if defined(GPIO_TIM4_CH3IN)
gpio_in_cfg = GPIO_TIM4_CH3IN;
ccmr_val |= ( GPIO_TIM4_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM4_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM4_CH4OUT)
gpio_out_cfg = GPIO_TIM4_CH4OUT;
#endif
#if defined(GPIO_TIM4_CH4IN)
gpio_in_cfg = GPIO_TIM4_CH4IN;
ccmr_val |= ( GPIO_TIM4_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM4_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default: return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM5_CH1OUT)
gpio_out_cfg = GPIO_TIM5_CH1OUT;
#endif
#if defined(GPIO_TIM5_CH1IN)
gpio_in_cfg = GPIO_TIM5_CH1IN;
ccmr_val |= ( GPIO_TIM5_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM5_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM5_CH2OUT)
gpio_out_cfg = GPIO_TIM5_CH2OUT;
#endif
#if defined(GPIO_TIM5_CH2IN)
gpio_in_cfg = GPIO_TIM5_CH2IN;
ccmr_val |= ( GPIO_TIM5_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM5_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM5_CH3OUT)
gpio_out_cfg = GPIO_TIM5_CH3OUT;
#endif
#if defined(GPIO_TIM5_CH3IN)
gpio_in_cfg = GPIO_TIM5_CH3IN;
ccmr_val |= ( GPIO_TIM5_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM5_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM5_CH4OUT)
gpio_out_cfg = GPIO_TIM5_CH4OUT;
#endif
#if defined(GPIO_TIM5_CH4IN)
gpio_in_cfg = GPIO_TIM5_CH4IN;
ccmr_val |= ( GPIO_TIM5_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM5_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default: return ERROR;
}
break;
#endif
#if STM32_NATIM > 0
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM1_CH1OUT)
gpio_out_cfg = GPIO_TIM1_CH1OUT;
#endif
#if defined(GPIO_TIM1_CH1IN)
gpio_in_cfg = GPIO_TIM1_CH1IN;
ccmr_val |= ( GPIO_TIM1_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM1_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM1_CH2OUT)
gpio_out_cfg = GPIO_TIM1_CH2OUT;
#endif
#if defined(GPIO_TIM1_CH2IN)
gpio_in_cfg = GPIO_TIM1_CH2IN;
ccmr_val |= ( GPIO_TIM1_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM1_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM1_CH3OUT)
gpio_out_cfg = GPIO_TIM1_CH3OUT;
#endif
#if defined(GPIO_TIM1_CH3IN)
gpio_in_cfg = GPIO_TIM1_CH3IN;
ccmr_val |= ( GPIO_TIM1_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM1_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM1_CH4OUT)
gpio_out_cfg = GPIO_TIM1_CH4OUT;
#endif
#if defined(GPIO_TIM1_CH4IN)
gpio_in_cfg = GPIO_TIM1_CH4IN;
ccmr_val |= ( GPIO_TIM1_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM1_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default:
return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
case 0:
#if defined(GPIO_TIM8_CH1OUT)
gpio_out_cfg = GPIO_TIM8_CH1OUT, ;
#endif
#if defined(GPIO_TIM8_CH1IN)
gpio_in_cfg = GPIO_TIM8_CH1OUIN ;
ccmr_val |= ( GPIO_TIM8_CH1_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM8_CH1_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 1:
#if defined(GPIO_TIM8_CH2OUT)
gpio_out_cfg = GPIO_TIM8_CH2OUT, ;
#endif
#if defined(GPIO_TIM8_CH2IN)
gpio_in_cfg = GPIO_TIM8_CH2OUIN ;
ccmr_val |= ( GPIO_TIM8_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM8_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 2:
#if defined(GPIO_TIM8_CH3OUT)
gpio_out_cfg = GPIO_TIM8_CH3OUT, ;
#endif
#if defined(GPIO_TIM8_CH3IN)
gpio_in_cfg = GPIO_TIM8_CH3OUIN ;
ccmr_val |= ( GPIO_TIM8_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM8_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
case 3:
#if defined(GPIO_TIM8_CH4OUT)
gpio_out_cfg = GPIO_TIM8_CH4OUT, ;
#endif
#if defined(GPIO_TIM8_CH4IN)
gpio_in_cfg = GPIO_TIM8_CH4OUIN ;
ccmr_val |= ( GPIO_TIM8_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT );
ccmr_val |= ( GPIO_TIM8_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
break;
default:
return ERROR;
}
break;
#endif
#endif
default:
return ERROR;
}
/* Decode configuration */
switch (mode & STM32_TIM_CH_MODE_MASK)
{
case STM32_TIM_CH_DISABLED:
ccmr_val = 0;
break;
case STM32_TIM_CH_INCAPTURE:
ccmr_val |= (ATIM_CCMR_CCS_CCIN1 << ATIM_CCMR1_CC1S_SHIFT);
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
if ( gpio_in_cfg == 0 )
return ERROR;
break;
case STM32_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
if ( gpio_out_cfg == 0 )
return ERROR;
break;
default:
@ -985,20 +614,177 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
/* set GPIO */
if ( gpio_in_cfg )
switch (((struct stm32_tim_priv_s *)dev)->base)
{
if ( mode & STM32_TIM_CH_MODE_IN_MASK )
stm32_configgpio(gpio_in_cfg);
else
stm32_unconfiggpio(gpio_in_cfg);
}
if ( gpio_out_cfg )
{
if ( mode & STM32_TIM_CH_MODE_OUT_MASK )
stm32_configgpio(gpio_in_cfg);
else
stm32_unconfiggpio(gpio_out_cfg);
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
#if defined(GPIO_TIM2_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
#if defined(GPIO_TIM3_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
#if defined(GPIO_TIM4_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
break;
#endif
default: return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
#if defined(GPIO_TIM5_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
break;
#endif
default: return ERROR;
}
break;
#endif
#if STM32_NATIM > 0
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
#if defined(GPIO_TIM1_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM1_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
#endif
default: return ERROR;
}
break;
#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
#if defined(GPIO_TIM8_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
#endif
#if defined(GPIO_TIM8_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
#endif
default:
return ERROR;
}
break;
#endif
#endif
default:
return ERROR;
}
return OK;
@ -1035,69 +821,19 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
switch (channel)
{
#ifdef HAVE_CH1IN
case 1:
return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 2:
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 3:
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
#endif
#ifdef HAVE_CH1IN
case 4:
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
#endif
}
return ERROR;
}
static bool stm32_tim_captureoverflow(FAR struct stm32_tim_dev_s *dev, int channel,
bool clear)
{
uint16_t regval;
uint16_t mask;
ASSERT(dev);
switch (channel)
{
#ifdef HAVE_CH1IN
case 1:
mask = GTIM_SR_CC1OF;
break;
#endif
#ifdef HAVE_CH2IN
case 2:
mask = GTIM_SR_CC2IF;
break;
#endif
#ifdef HAVE_CH3IN
case 3:
mask = GTIM_SR_CC3IF;
break;
#endif
#ifdef HAVE_CH4IN
case 4:
mask = GTIM_SR_CC4IF;
break;
#endif
default:
return ERROR;
}
regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET);
if (regval & mask)
{
if (clear)
stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~mask);
return 1;
}
return 0;
}
/************************************************************************************
* Advanced Functions
************************************************************************************/
@ -1116,12 +852,10 @@ struct stm32_tim_ops_s stm32_tim_ops =
.setchannel = &stm32_tim_setchannel,
.setcompare = &stm32_tim_setcompare,
.getcapture = &stm32_tim_getcapture,
.captureoverflow= &stm32_tim_captureoverflow,
.setisr = &stm32_tim_setisr,
.enableint = &stm32_tim_enableint,
.disableint = &stm32_tim_disableint,
.ackint = &stm32_tim_ackint,
.getintsrc = &stm32_tim_getintsrc
.ackint = &stm32_tim_ackint
};
#ifdef CONFIG_STM32_TIM2

43
arch/arm/src/stm32/stm32_tim.h
View File

@ -55,16 +55,16 @@
************************************************************************************/
/* Helpers **************************************************************************/
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
/************************************************************************************
* Public Types
@ -122,21 +122,6 @@ typedef enum
} stm32_tim_mode_t;
/* TIM Sources */
typedef enum
{
/* One of the following */
STM32_TIM_INT_SRC_OVERFLOW = 0x0001,
STM32_TIM_INT_SRC_CAPTURE_1 = 0x0002,
STM32_TIM_INT_SRC_CAPTURE_2 = 0x0004,
STM32_TIM_INT_SRC_CAPTURE_3 = 0x0008,
STM32_TIM_INT_SRC_CAPTURE_4 = 0x0010
} stm32_tim_source_t;
/* TIM Channel Modes */
typedef enum
@ -150,19 +135,15 @@ typedef enum
/* MODES: */
STM32_TIM_CH_MODE_OUT_MASK = 0x06,
STM32_TIM_CH_MODE_IN_MASK = 0x10,
STM32_TIM_CH_MODE_MASK = 0x16,
STM32_TIM_CH_MODE_MASK = 0x06,
/* Output Compare Modes */
STM32_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
//STM32_TIM_CH_OUTCOMPARE = 0x06,
/* Input Compare Modes */
STM32_TIM_CH_INCAPTURE = 0x10,
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
//STM32_TIM_CH_INCAPTURE = 0x10,
//STM32_TIM_CH_INPWM = 0x20
//STM32_TIM_CH_DRIVE_OC -- open collector mode