arch/arm/src/kinetis: Add SIM register definitions for the K28F.
This commit is contained in:
Gregory Nutt
parent
3c7fa88fd4
commit
0f2b8b0ca2
@ -135,8 +135,14 @@
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* KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC - SoC has SOPT4[TPM2CH0SRC]
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* KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL - SoC has SOPT4[TPM2CLKSEL]
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* KINETIS_SIM_HAS_SOPT5 - SoC has SOPT5 Register
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* KINETIS_SIM_HAS_SOPT5_UART0RXSRC - SoC has SOPT5[UART0RXSRC]
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* KINETIS_SIM_HAS_SOPT5_UART0TXSRC - SoC has SOPT5[UART0TXSRC]
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* KINETIS_SIM_HAS_SOPT5_UART1RXSRC - SoC has SOPT5[UART1RXSRC]
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* KINETIS_SIM_HAS_SOPT5_UART1TXSRC - SoC has SOPT5[UART1TXSRC]
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* KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC - SoC has SOPT5[LPUART0RXSRC]
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* KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC - SoC has SOPT5[LPUART0TXSRC]
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* KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC - SoC has SOPT5[LPUART1RXSRC]
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* KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC - SoC has SOPT5[LPUART1TXSRC]
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* KINETIS_SIM_HAS_SOPT6 - SoC has SOPT6 Register
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* KINETIS_SIM_HAS_SOPT6_MCC - SoC has SOPT6[MCC]
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* KINETIS_SIM_HAS_SOPT6_PCR - SoC has SOPT6[PCR]
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@ -199,8 +205,15 @@
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* KINETIS_SIM_HAS_SCGC2 - SoC has SCGC2 Register
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* KINETIS_SIM_HAS_SCGC2_ENET - SoC has SCGC2[ENET]
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* KINETIS_SIM_HAS_SCGC2_LPUART0 - SoC has SCGC2[LPUART0]
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* KINETIS_SIM_HAS_SCGC2_LPUART1 - SoC has SCGC2[LPUART1]
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* KINETIS_SIM_HAS_SCGC2_LPUART2 - SoC has SCGC2[LPUART2]
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* KINETIS_SIM_HAS_SCGC2_LPUART3 - SoC has SCGC2[LPUART3]
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* KINETIS_SIM_HAS_SCGC2_LPUART4 - SoC has SCGC2[LPUART4]
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* KINETIS_SIM_HAS_SCGC2_TPM1 - SoC has SCGC2[TPM1]
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* KINETIS_SIM_HAS_SCGC2_TPM2 - SoC has SCGC2[TPM2]
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* KINETIS_SIM_HAS_SCGC2_DAC1 - SoC has SCGC2[DAC1]
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* KINETIS_SIM_HAS_SCGC2_QSPI - SoC has SCGC2[QSPI]
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* KINETIS_SIM_HAS_SCGC2_FLEXIO - SoC has SCGC2[FLEXIO]
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* KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register
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* KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register
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* KINETIS_SIM_HAS_SCGC3_RNGA - SoC has SCGC3[RNGA]
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@ -210,6 +223,7 @@
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* KINETIS_SIM_HAS_SCGC3_FLEXCAN1 - SoC has SCGC3[FLEXCAN1]
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* KINETIS_SIM_HAS_SCGC3_NFC - SoC has SCGC3[NFC]
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* KINETIS_SIM_HAS_SCGC3_SPI2 - SoC has SCGC3[SPI2]
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* KINETIS_SIM_HAS_SCGC3_SPI3 - SoC has SCGC3[SPI3]
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* KINETIS_SIM_HAS_SCGC3_SAI1 - SoC has SCGC3[SAI1]
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* KINETIS_SIM_HAS_SCGC3_SDHC - SoC has SCGC3[SDHC]
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* KINETIS_SIM_HAS_SCGC3_FTM2 - SoC has SCGC3[FTM2]
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@ -225,11 +239,13 @@
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* KINETIS_SIM_HAS_SCGC4_UART3 - SoC has SCGC4[UART3]
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* KINETIS_SIM_HAS_SCGC5 - SoC has _SCGC5 Register
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* KINETIS_SIM_HAS_SCGC5_REGFILE - SoC has SCGC5[REGFILE]
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* KINETIS_SIM_HAS_SCGC5_LPTMR1 - SoC has SCGC5[LPTMR1]
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* KINETIS_SIM_HAS_SCGC5_TSI - SoC has SCGC5[TSI]
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* KINETIS_SIM_HAS_SCGC5_PORTF - SoC has SCGC5[PORTf]
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* KINETIS_SIM_HAS_SCGC6 - SoC has SCGC6 Register
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* KINETIS_SIM_HAS_SCGC6_FTFL - SoC has SCGC6[FTFL]
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* KINETIS_SIM_HAS_SCGC6_DMAMUX1 - SoC has SCGC6[DEMUX1]
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* KINETIS_SIM_HAS_SCGC6_FLEXCAN0 - SoC has SCGC6[FLEXCAN0]
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* KINETIS_SIM_HAS_SCGC6_USBHS - SoC has SCGC6[USBHS]
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* KINETIS_SIM_HAS_SCGC6_RNGA - SoC has SCGC6[RNGA]
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* KINETIS_SIM_HAS_SCGC6_FTM2 - SoC has SCGC6[FTM2]
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@ -289,6 +305,7 @@
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#define KINETIS_SIM_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
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#define KINETIS_SIM_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
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#define KINETIS_SIM_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
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#define KINETIS_SIM_VERSION_07 7 /* Verified to Document Number: K28P210M150SF5RM Rev. 4, August 2017 */
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/* MK20DX/DN---VLH5
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*
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@ -330,6 +347,278 @@
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# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
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/* MK28FN2M0---15-
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*
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* --------------- ------- --- ------- ------ ------- ------ -----
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* PART NUMBER CPU PIN PACKAGE PROGRAM EEPROM SRAM GPIO
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* FREQ CNT FLASH
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* --------------- ------- --- ------- ------ ------- ------ -----
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* MK28FN2M0VMI15 150 MHz 169 MAPBGA 2 MB None 1 MB 120
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* MK28FN2M0CAU15R 150 MHz 210 WLCSP 2 MB None 1 MB 120
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* --------------- ------- --- ------- ------ ------- ------ -----
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*/
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#elif defined(CONFIG_ARCH_CHIP_MK28FN2M0VMI15) || \
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defined(CONFIG_ARCH_CHIP_MK28FN2M0CAU15R)
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/* Verified to Document Number: K28P210M150SF5RM Rev. 4, August 2017 */
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# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_07
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/* SIM Register Configuration */
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# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */
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# undef KINETIS_SIM_HAS_SOPT1_RAMSIZE /* SoC does not have SOPT1[RAMSIZE] */
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# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC does not have SOPT1[OSC32KOUT] */
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# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */
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# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 1 bit SOPT1[OSC32KSEL] */
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# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */
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# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */
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# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
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# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
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# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
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# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */
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# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */
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# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */
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# define KINETIS_SIM_HAS_USBPHYCTL 1 /* SoC has USBPHYCTL Register */
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# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL 1 /* SoC has USBPHYCTL[USBVREGSEL] */
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# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD 1 /* SoC has USBPHYCTL[USBVREGPD] */
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# define KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG 1 /* SoC has USBPHYCTL[USB3VOUTTRG] */
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# define KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM 1 /* SoC has USBPHYCTL[USBDISILIM] */
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# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
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# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC does not have SOPT2[MCGCLKSEL] */
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# define KINETIS_SIM_HAS_SOPT2_USBSLSRC 1 /* SoC has SOPT2[USBSLSRC] */
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# define KINETIS_SIM_HAS_SOPT2_USBREGEN 1 /* SoC has SOPT2[USBREGEN] */
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# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC does not have SOPT2[USBHSRC] */
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# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */
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# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */
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# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
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# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC does not have SOPT2[CMTUARTPAD] */
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# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */
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# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC does not have SOPT2[PTD7PAD] */
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# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */
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# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */
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# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
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# undef KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC does not have SOPT2[RMIISRC] */
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# undef KINETIS_SIM_HAS_SOPT2_TIMESRC /* SoC does not have SOPT2[TIMESRC] */
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# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */
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# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC does not have SOPT2[USBFSRC] */
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# define KINETIS_SIM_HAS_SOPT2_TPMSRC 1 /* SoC has SOPT2[TPMSRC] */
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# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC does not have SOPT2[I2SSRC] */
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# define KINETIS_SIM_HAS_SOPT2_LPUARTSRC 1 /* SoC has SOPT2[LPUARTSRC] */
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# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */
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# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC does not have SOPT2[NFCSRC] */
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# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
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# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
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# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT2 /* SoC does not have SOPT4[FTM0FLT2] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC does not have SOPT4[FTM0FLT3] */
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# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT1 /* SoC does not have SOPT4[FTM1FLT1] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT2 /* SoC does not have SOPT4[FTM1FLT2] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT3 /* SoC does not have SOPT4[FTM1FLT3] */
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# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT1 /* SoC does not have SOPT4[FTM2FLT1] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT2 /* SoC does not have SOPT4[FTM2FLT2] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT3 /* SoC does not have SOPT4[FTM2FLT3] */
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# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT1 /* SoC does not have SOPT4[FTM3FLT1] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT2 /* SoC does not have SOPT4[FTM3FLT2] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT3 /* SoC does not have SOPT4[FTM3FLT3] */
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# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */
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# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */
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# define KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC 1 /* SoC has SOPT4[FTM2CH1SRC] */
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# undef KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC /* SoC does not have SOPT4[FTM3CH0SRC] */
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# define KINETIS_SIM_HAS_SOPT4_FTM0CLKSEL 1 /* SoC has SOPT4[FTM0CLKSEL] */
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# define KINETIS_SIM_HAS_SOPT4_FTM1CLKSEL 1 /* SoC has SOPT4[FTM1CLKSEL] */
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# define KINETIS_SIM_HAS_SOPT4_FTM2CLKSEL 1 /* SoC has SOPT4[FTM2CLKSEL] */
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# define KINETIS_SIM_HAS_SOPT4_FTM3CLKSEL 1 /* SoC has SOPT4[FTM3CLKSEL] */
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# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */
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# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */
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# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */
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# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */
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# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
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# undef KINETIS_SIM_HAS_SOPT5_UART0RXSRC /* SoC does not have SOPT5[UART0RXSRC] */
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# undef KINETIS_SIM_HAS_SOPT5_UART0TXSRC /* SoC does not have SOPT5[UART0TXSRC] */
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# undef KINETIS_SIM_HAS_SOPT5_UART1RXSRC /* SoC does not have SOPT5[UART1RXSRC] */
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# undef KINETIS_SIM_HAS_SOPT5_UART1TXSRC /* SoC does not have SOPT5[UART1TXSRC] */
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# define KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC 1 /* SoC has SOPT5[LPUART0RXSRC] */
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# define KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC 1 /* SoC has SOPT5[LPUART0TXSRC] */
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# define KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC 1 /* SoC has SOPT5[LPUART1RXSRC] */
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# define KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC 1 /* SoC has SOPT5[LPUART1TXSRC] */
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# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */
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# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
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# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
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# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */
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# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */
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# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
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# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 10 SOPT7[ADC0TRGSEL] */
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# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */
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# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */
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# undef KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL /* SoC does not have SOPT7[ADC1TRGSEL] */
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# undef KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL /* SoC does not have SOPT7[ADC1PRETRGSEL] */
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# undef KINETIS_SIM_SOPT7_ADC1ALTTRGEN /* ADC1 alternate trigger enable */
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# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC does not have SOPT7[ADC2TRGSEL] */
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# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC does not have SOPT7[ADC2PRETRGSEL] */
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# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */
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# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC does not have SOPT7[ADC3TRGSEL] */
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# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC does not have SOPT7[ADC3PRETRGSEL] */
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# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */
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# define KINETIS_SIM_HAS_SOPT8 1 /* SoC has SOPT8 Register */
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# define KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT 1 /* SoC has SOPT8[FTM0SYNCBIT] */
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# define KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT 1 /* SoC has SOPT8[FTM1SYNCBIT] */
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# define KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT 1 /* SoC has SOPT8[FTM2SYNCBIT] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT 1 /* SoC has SOPT8[FTM3SYNCBIT] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC 1 /* SoC has SOPT8[FTM0OCH0SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC 1 /* SoC has SOPT8[FTM0OCH1SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC 1 /* SoC has SOPT8[FTM0OCH2SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC 1 /* SoC has SOPT8[FTM0OCH3SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC 1 /* SoC has SOPT8[FTM0OCH4SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC 1 /* SoC has SOPT8[FTM0OCH5SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC 1 /* SoC has SOPT8[FTM0OCH6SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC 1 /* SoC has SOPT8[FTM0OCH7SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC 1 /* SoC has SOPT8[FTM3OCH0SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC 1 /* SoC has SOPT8[FTM3OCH1SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC 1 /* SoC has SOPT8[FTM3OCH2SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC 1 /* SoC has SOPT8[FTM3OCH3SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC 1 /* SoC has SOPT8[FTM3OCH4SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC 1 /* SoC has SOPT8[FTM3OCH5SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC 1 /* SoC has SOPT8[FTM3OCH6SRC] */
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# define KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC 1 /* SoC has SOPT8[FTM3OCH7SRC] */
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# define KINETIS_SIM_HAS_SOPT9 1 /* SoC has SOPT9 Register */
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# define KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC 1 /* SoC has SOPT9[TPM1CH0SRC] */
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# define KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC 1 /* SoC has SOPT9[TPM2CH0SRC] */
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# define KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL 1 /* SoC has SOPT9[TPM1CLKSEL] */
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# define KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL 1 /* SoC has SOPT9[TPM2CLKSEL] */
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# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
|
||||
# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
|
||||
# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */
|
||||
# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */
|
||||
# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC does not have SDID[SRAMSIZE] */
|
||||
# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */
|
||||
# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC does not have SCGC1[OSC1] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_I2C3 1 /* SoC has SCGC1[I2C3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_UART4 /* SoC does not have SCGC1[UART4] */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_UART5 /* SoC does not have SCGC1[UART5] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_ENET /* SoC does not have SCGC2[ENET] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART0 1 /* SoC has SCGC2[LPUART0] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART1 1 /* SoC has SCGC2[LPUART1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART2 1 /* SoC has SCGC2[LPUART2] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART3 1 /* SoC has SCGC2[LPUART3] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART4 1 /* SoC has SCGC2[LPUART4] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_TPM1 1 /* SoC has SCGC2[TPM1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_TPM2 1 /* SoC has SCGC2[TPM2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_DAC1 /* SoC does not have SCGC2[DAC1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_QSPI 1 /* SoC has SCGC2[QSPI] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_FLEXIO 1 /* SoC has SCGC2[FLEXIO] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[TRNG/RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC does not have SCGC3[USBHS] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC does not have SCGC3[USBHSPHY] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC does not have SCGC3[USBHSDCD] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC does not have SCGC3[FLEXCAN1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC does not have SCGC3[NFC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI3 1 /* SoC has SCGC3[SPI3] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_ADC1 /* SoC does not have SCGC3[ADC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC does not have SCGC3[ADC3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC does not have SCGC3[SLCD] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_UART0 /* SoC does not have SCGC4[UART0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_UART1 /* SoC does not have SCGC4[UART1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_UART2 /* SoC does not have SCGC4[UART2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_UART3 /* SoC does not have SCGC4[UART3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC does not have SCGC4[LLWU] clock gate */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC does not have SCGC5[REGFILE] */
|
||||
# define KINETIS_SIM_HAS_SCGC5_LPTMR1 1 /* SoC has SCGC5[LPTMR1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_TSI /* SoC does not have SCGC5[TSI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC does not have SCGC5[PORTF] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC does not have SCGC6[DEMUX1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_FLEXCAN0 /* SoC does not have SCGC6[FLEXCAN0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_RNGA /* SoC does not have SCGC6[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC does not have SCGC6[USBHS] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC does not have SCGC6[ADC2] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_SDRAMC 1 /* SoC has SCGC7[SDRAMC] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC does not have CLKDIV1[OUTDIV5] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC does not have CLKDIV2[USBHSFRAC] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC does not have CLKDIV2[USBHSDIV] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC does not have CLKDIV2[I2SFRAC] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC does not have CLKDIV2[I2SDIV] */
|
||||
|
||||
# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
|
||||
# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC does not have FCFG1[FTFDIS] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
|
||||
|
||||
# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
|
||||
# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 15 /* SoC has n bit of FCFG2[MAXADDR1] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 15 /* SoC has n bit of FCFG2[MAXADDR0] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */
|
||||
|
||||
# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
|
||||
# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
|
||||
# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
|
||||
# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV3 1 /* SoC has CLKDIV3 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC 1 /* SoC has CLKDIV3[PLLFLLFRAC] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV 1 /* SoC has CLKDIV3[PLLFLLDIV] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC does not have CLKDIV4[NFCFRAC] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC does not have CLKDIV4[NFCDIV] */
|
||||
|
||||
# undef KINETIS_SIM_HAS_MCR /* SoC does not have MCR Register */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
|
||||
|
||||
@ -490,8 +779,14 @@
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0RXSRC 1 /* SoC has SOPT5[UART0RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0TXSRC 1 /* SoC has SOPT5[UART0TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1RXSRC 1 /* SoC has SOPT5[UART1RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1TXSRC 1 /* SoC has SOPT5[UART1TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC /* SoC has SOPT5[LPUART1RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC /* SoC has SOPT5[LPUART1TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT6_MCC 1 /* SoC has SOPT6[MCC] */
|
||||
# define KINETIS_SIM_HAS_SOPT6_PCR 1 /* SoC has SOPT6[PCR] */
|
||||
@ -551,12 +846,18 @@
|
||||
# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_OSC1 1 /* SoC has SCGC1[OSC1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART1 /* SoC has SCGC2[LPUART1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART2 /* SoC has SCGC2[LPUART2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART3 /* SoC has SCGC2[LPUART3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART4 /* SoC has SCGC2[LPUART4] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_DAC1 1 /* SoC has SCGC2[DAC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_QSPI /* SoC has SCGC2[QSPI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_FLEXIO /* SoC has SCGC2[FLEXIO] */
|
||||
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
|
||||
@ -565,7 +866,8 @@
|
||||
# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_NFC 1 /* SoC has SCGC3[NFC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SPI3 /* SoC has SCGC3[SPI3] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
|
||||
@ -580,11 +882,13 @@
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
|
||||
# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_LPTMR1 /* SoC has SCGC5[LPTMR1] */
|
||||
# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
|
||||
# define KINETIS_SIM_HAS_SCGC5_PORTF 1 /* SoC has SCGC5[PORTF] */
|
||||
# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_FTFL /* SoC has SCGC6[FTFL] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_DMAMUX1 1 /* SoC has SCGC6[DEMUX1] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FLEXCAN0 1 /* SoC has SCGC6[FLEXCAN0] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_USBHS 1 /* SoC has SCGC6[USBHS] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */
|
||||
@ -717,8 +1021,14 @@
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0RXSRC 1 /* SoC has SOPT5[UART0RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0TXSRC 1 /* SoC has SOPT5[UART0TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1RXSRC 1 /* SoC has SOPT5[UART1RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1TXSRC 1 /* SoC has SOPT5[UART1TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC /* SoC has SOPT5[LPUART1RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC /* SoC has SOPT5[LPUART1TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
|
||||
@ -778,12 +1088,18 @@
|
||||
# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART1 /* SoC has SCGC2[LPUART1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART2 /* SoC has SCGC2[LPUART2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART3 /* SoC has SCGC2[LPUART3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART4 /* SoC has SCGC2[LPUART4] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_DAC1 1 /* SoC has SCGC2[DAC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_QSPI /* SoC has SCGC2[QSPI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_FLEXIO /* SoC has SCGC2[FLEXIO] */
|
||||
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
|
||||
@ -792,6 +1108,7 @@
|
||||
# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC has SCGC3[FLEXCAN1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SPI3 /* SoC has SCGC3[SPI3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
|
||||
@ -807,11 +1124,13 @@
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
|
||||
# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_LPTMR1 /* SoC has SCGC5[LPTMR1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_TSI /* SoC has SCGC5[TSI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
|
||||
# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FLEXCAN0 1 /* SoC has SCGC6[FLEXCAN0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */
|
||||
@ -891,15 +1210,18 @@
|
||||
# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
|
||||
# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
|
||||
# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
|
||||
# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */
|
||||
# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */
|
||||
# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */
|
||||
|
||||
# define KINETIS_SIM_HAS_USBPHYCTL 1 /* SoC has USBPHYCTL Register */
|
||||
# define KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG 1 /* SoC has USBPHYCTL[USB3VOUTTRG] */
|
||||
# define KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM 1 /* SoC has USBPHYCTL[USBDISILIM] */
|
||||
# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD 1 /* SoC has USBPHYCTL[USBVREGPD] */
|
||||
# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL 1 /* SoC has USBPHYCTL[USBVREGSEL] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
|
||||
# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */
|
||||
@ -923,6 +1245,7 @@
|
||||
# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
|
||||
# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
|
||||
@ -953,14 +1276,23 @@
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0RXSRC 1 /* SoC has SOPT5[UART0RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0TXSRC 1 /* SoC has SOPT5[UART0TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1RXSRC 1 /* SoC has SOPT5[UART1RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1TXSRC 1 /* SoC has SOPT5[UART1TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC 1 /* SoC has SOPT5[LPUART0RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC 1 /* SoC has SOPT5[LPUART0TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC /* SoC has SOPT5[LPUART1RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC /* SoC has SOPT5[LPUART1TXSRC] */
|
||||
|
||||
# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */
|
||||
@ -976,6 +1308,7 @@
|
||||
# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */
|
||||
# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */
|
||||
# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT8 1 /* SoC has SOPT8 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT 1 /* SoC has SOPT8[FTM0SYNCBIT] */
|
||||
# define KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT 1 /* SoC has SOPT8[FTM1SYNCBIT] */
|
||||
@ -997,11 +1330,13 @@
|
||||
# define KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC 1 /* SoC has SOPT8[FTM3OCH5SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC 1 /* SoC has SOPT8[FTM3OCH6SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC 1 /* SoC has SOPT8[FTM3OCH7SRC] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SOPT9 1 /* SoC has SOPT9 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC 1 /* SoC has SOPT9[TPM1CH0SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC 1 /* SoC has SOPT9[TPM2CH0SRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL 1 /* SoC has SOPT9[TPM1CLKSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL 1 /* SoC has SOPT9[TPM2CLKSEL] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
|
||||
# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */
|
||||
# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
|
||||
@ -1009,18 +1344,27 @@
|
||||
# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */
|
||||
# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */
|
||||
# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_UART5 /* SoC has SCGC1[UART5] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_I2C3 1 /* SoC has SCGC1[I2C3] */
|
||||
# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_LPUART0 1 /* SoC has SCGC2[LPUART0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART1 /* SoC has SCGC2[LPUART1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART2 /* SoC has SCGC2[LPUART2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART3 /* SoC has SCGC2[LPUART3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART4 /* SoC has SCGC2[LPUART4] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_TPM1 1 /* SoC has SCGC2[TPM1] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_TPM2 1 /* SoC has SCGC2[TPM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_DAC1 1 /* SoC has SCGC2[DAC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_QSPI /* SoC has SCGC2[QSPI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_FLEXIO /* SoC has SCGC2[FLEXIO] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_USBHS 1 /* SoC has SCGC3[USBHS] */
|
||||
@ -1029,6 +1373,7 @@
|
||||
# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SPI3 /* SoC has SCGC3[SPI3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
|
||||
@ -1036,34 +1381,42 @@
|
||||
# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_LPTMR1 /* SoC has SCGC5[LPTMR1] */
|
||||
# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FLEXCAN0 1 /* SoC has SCGC6[FLEXCAN0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */
|
||||
|
||||
# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
|
||||
# define KINETIS_SIM_HAS_SCGC7_SDRAMC 1 /* SoC has SCGC7[SDRAMC] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
|
||||
@ -1073,6 +1426,7 @@
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */
|
||||
|
||||
# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
|
||||
# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
|
||||
@ -1080,23 +1434,28 @@
|
||||
# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */
|
||||
# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */
|
||||
# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
|
||||
|
||||
# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
|
||||
# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
|
||||
# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */
|
||||
|
||||
# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
|
||||
# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
|
||||
# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
|
||||
# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV3 1 /* SoC has CLKDIV3 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV 1 /* SoC has CLKDIV3[PLLFLLDIV] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC 1 /* SoC has CLKDIV3[PLLFLLFRAC] */
|
||||
|
||||
# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */
|
||||
# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */
|
||||
# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */
|
||||
# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */
|
||||
|
||||
# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */
|
||||
#else
|
||||
# error "Unsupported Kinetis chip"
|
||||
@ -1178,8 +1537,14 @@
|
||||
# undef KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC /* SoC has SOPT4[TPM2CH0SRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL /* SoC has SOPT4[TPM2CLKSEL] */
|
||||
# define KINETIS_SIM_HAS_SOPT5 /* SoC has SOPT5 Register */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0RXSRC 1 /* SoC has SOPT5[UART0RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART0TXSRC 1 /* SoC has SOPT5[UART0TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1RXSRC 1 /* SoC has SOPT5[UART1RXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT5_UART1TXSRC 1 /* SoC has SOPT5[UART1TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC /* SoC has SOPT5[LPUART1RXSRC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC /* SoC has SOPT5[LPUART1TXSRC] */
|
||||
# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
|
||||
# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
|
||||
@ -1218,8 +1583,15 @@
|
||||
# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART1 /* SoC has SCGC2[LPUART1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART2 /* SoC has SCGC2[LPUART2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART3 /* SoC has SCGC2[LPUART3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_LPUART4 /* SoC has SCGC2[LPUART4] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
|
||||
# define KINETIS_SIM_HAS_SCGC2_DAC1 1 /* SoC has SCGC2[DAC1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_QSPI /* SoC has SCGC2[QSPI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC2_FLEXIO /* SoC has SCGC2[FLEXIO] */
|
||||
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
|
||||
@ -1228,6 +1600,7 @@
|
||||
# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SPI3 /* SoC has SCGC3[SPI3] */
|
||||
# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
|
||||
# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
|
||||
@ -1243,11 +1616,13 @@
|
||||
# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
|
||||
# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has SCGC5 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC5_REGFILE 1 /* SoC has SCGC5[REGFILE] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_LPTMR1 /* SoC has SCGC5[LPTMR1] */
|
||||
# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
|
||||
# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
|
||||
# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
|
||||
# define KINETIS_SIM_HAS_SCGC6_FLEXCAN0 1 /* SoC has SCGC6[FLEXCAN0] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_RNGA /* SoC has SCGC6[RNGA] */
|
||||
# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */
|
||||
|
||||
@ -651,11 +651,18 @@ config KINETIS_TPM2
|
||||
---help---
|
||||
Support TPM module 2
|
||||
|
||||
config KINETIS_LPTIMER
|
||||
bool "Low power timer (LPTIMER)"
|
||||
config KINETIS_LPTMR0
|
||||
bool "Low power timer 0 (LPTMR0)"
|
||||
default n
|
||||
---help---
|
||||
Support the low power timer
|
||||
Support the low power timer 0
|
||||
|
||||
config KINETIS_LPTMR1
|
||||
bool "Low power timer 0 (LPTMR1)"
|
||||
default n
|
||||
depends on KINETIS_HAVE_LPTMR1
|
||||
---help---
|
||||
Support the low power timer 1
|
||||
|
||||
config KINETIS_RTC
|
||||
bool "RTC"
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kinetis/chip/kinetis_mcg.h
|
||||
*
|
||||
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011, 2016-2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kinetis/chip/kinetis_sim.h
|
||||
*
|
||||
* Copyright (C) 2011, 2016, 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011, 2016-2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
@ -58,7 +58,9 @@
|
||||
#if defined(KINETIS_SIM_HAS_USBPHYCTL)
|
||||
# define KINETIS_SIM_USBPHYCTL_OFFSET 0x0008 /* USB PHY Control Register */
|
||||
#endif
|
||||
#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT2)
|
||||
# define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */
|
||||
#endif
|
||||
#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */
|
||||
#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */
|
||||
#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */
|
||||
@ -104,7 +106,9 @@
|
||||
#if defined(KINETIS_SIM_HAS_USBPHYCTL)
|
||||
# define KINETIS_SIM_USBPHYCTL (KINETIS_SIMLP_BASE+KINETIS_SIM_USBPHYCTL_OFFSET)
|
||||
#endif
|
||||
#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET)
|
||||
#if defined(KINETIS_SIM_HAS_SOPT2)
|
||||
# define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET)
|
||||
#endif
|
||||
#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET)
|
||||
#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET)
|
||||
#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET)
|
||||
@ -178,9 +182,9 @@
|
||||
# define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT1CFG)
|
||||
/* SOPT1 Configuration Register */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT1CFG)
|
||||
/* Bits 0-22: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SOPT1CFG_URWE)
|
||||
# define SIM_SOPT1CFG_URWE (1 << 24) /* Bit 24: USB voltage regulator enable write enable */
|
||||
@ -194,10 +198,9 @@
|
||||
/* Bits 27-31: Reserved */
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_USBPHYCTL)
|
||||
/* USB PHY Control Register */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_USBPHYCTL)
|
||||
/* Bits 0-7: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL)
|
||||
# define SIM_USBPHYCTL_USBVREGSEL (1 << 8) /* Bit 8: Selects the default input voltage source */
|
||||
@ -301,23 +304,28 @@
|
||||
# if defined(KINETIS_SIM_HAS_SOPT2_TIMESRC)
|
||||
# define SIM_SOPT2_TIMESRC_SHIFT (20) /* Bit 20-21: IEEE 1588 timestamp clock source select */
|
||||
# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT)
|
||||
# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */
|
||||
# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
|
||||
clock as selected by SOPT2[PLLFLLSEL] */
|
||||
# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */
|
||||
# define SIM_SOPT2_TIMESRC_EXTBYP (3 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */
|
||||
# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */
|
||||
# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
|
||||
clock as selected by SOPT2[PLLFLLSEL] */
|
||||
# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */
|
||||
# define SIM_SOPT2_TIMESRC_EXTBYP (3 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SOPT2_FLEXIOSRC)
|
||||
/* TBD */
|
||||
# define SIM_SOPT2_FLEXIOSRC_SHIFT (22) /* Bits 22-23: FlexIO Module Clock Source Select */
|
||||
# define SIM_SOPT2_FLEXIOSRC_MASK (3 << SIM_SOPT2_FLEXIOSRC_SHIFT)
|
||||
# define SIM_SOPT2_FLEXIOSRC_CORE (0 << SIM_SOPT2_FLEXIOSRC_SHIFT) /* Core/system clock */
|
||||
# define SIM_SOPT2_FLEXIOSRC_PLLSEL (1 << SIM_SOPT2_FLEXIOSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
|
||||
* clock as selected by SOPT2[PLLFLLSEL] */
|
||||
# define SIM_SOPT2_FLEXIOSRC_OSCERCLK (2 << SIM_SOPT2_FLEXIOSRC_SHIFT) /* OSCERCLK clock */
|
||||
# define SIM_SOPT2_FLEXIOSRC_MCGIRCLK (3 << SIM_SOPT2_FLEXIOSRC_SHIFT) /* MCGIRCLK clock */
|
||||
# endif
|
||||
/* Bits 22-23: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SOPT2_USBFSRC)
|
||||
# define SIM_SOPT2_USBFSRC_SHIFT (22) /* Bits 22-23: USB FS clock source select */
|
||||
# define SIM_SOPT2_USBFSRC_MASK (3 << SIM_SOPT2_USBFSRC_SHIFT)
|
||||
# define SIM_SOPT2_USBFSRC_MCGCLK (0 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK clock as selected by SOPT2[PLLFLLSEL] */
|
||||
# define SIM_SOPT2_USBFSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL0CLK clock */
|
||||
# define SIM_SOPT2_USBFSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL1CLK clock */
|
||||
# define SIM_SOPT2_USBFSRC_OCS0ERCLK (3 << SIM_SOPT2_USBFSRC_SHIFT) /* OSC0ERCLK clock */
|
||||
# define SIM_SOPT2_USBFSRC_SHIFT (22) /* Bits 22-23: USB FS clock source select */
|
||||
# define SIM_SOPT2_USBFSRC_MASK (3 << SIM_SOPT2_USBFSRC_SHIFT)
|
||||
# define SIM_SOPT2_USBFSRC_MCGCLK (0 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK clock as selected by SOPT2[PLLFLLSEL] */
|
||||
# define SIM_SOPT2_USBFSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL0CLK clock */
|
||||
# define SIM_SOPT2_USBFSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL1CLK clock */
|
||||
# define SIM_SOPT2_USBFSRC_OCS0ERCLK (3 << SIM_SOPT2_USBFSRC_SHIFT) /* OSC0ERCLK clock */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SOPT2_TPMSRC)
|
||||
# define SIM_SOPT2_TPMSRC_SHIFT (24) /* Bits 24-25: TPM clock source select */
|
||||
@ -374,7 +382,9 @@
|
||||
|
||||
#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */
|
||||
#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */
|
||||
#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT4_FTM0FLT2)
|
||||
# define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */
|
||||
#endif
|
||||
/* Bit 3: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT4_FTM0FLT3)
|
||||
# define SIM_SOPT4_FTM0FLT3 (1 << 3) /* Bit 3: FTM0 Fault 3 Select */
|
||||
@ -406,8 +416,8 @@
|
||||
#endif
|
||||
/* Bits 22-23: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC)
|
||||
/* Bit 23: Reserved */
|
||||
#define SIM_SOPT4_FTM2CH1SRC (1 << 22) /* Bit 22: FTM2 channel 1 input capture source select */
|
||||
/* Bit 23: Reserved */
|
||||
#endif
|
||||
#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */
|
||||
#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */
|
||||
@ -433,26 +443,34 @@
|
||||
|
||||
/* System Options Register 5 */
|
||||
|
||||
#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */
|
||||
#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */
|
||||
# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */
|
||||
# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */
|
||||
#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */
|
||||
#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */
|
||||
# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */
|
||||
# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */
|
||||
#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */
|
||||
#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */
|
||||
# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */
|
||||
# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */
|
||||
#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */
|
||||
#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */
|
||||
# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */
|
||||
# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_UART0TXSRC)
|
||||
# define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */
|
||||
# define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */
|
||||
# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */
|
||||
# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */
|
||||
#endif
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_UART0RXSRC)
|
||||
# define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */
|
||||
# define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */
|
||||
# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */
|
||||
# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */
|
||||
#endif
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_UART1TXSRC)
|
||||
# define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */
|
||||
# define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */
|
||||
# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */
|
||||
# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */
|
||||
#endif
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_UART1RXSRC)
|
||||
# define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */
|
||||
# define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT)
|
||||
# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */
|
||||
# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */
|
||||
# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */
|
||||
#endif
|
||||
/* Bits 8-31: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC)
|
||||
/* Bits 8-15, 18-31: Reserved */
|
||||
@ -472,9 +490,27 @@
|
||||
# define SIM_SOPT5_LPUART0RXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* CMP1 output */
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT6)
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC)
|
||||
/* Bits 8-15, 18-31: Reserved */
|
||||
# define SIM_SOPT5_LPUART1TXSRC_SHIFT (16) /* Bit 16: LPUART1 transmit data source select */
|
||||
# define SIM_SOPT5_LPUART1TXSRC_MASK (3 << SIM_SOPT5_LPUART1TXSRC_SHIFT)
|
||||
# define SIM_SOPT5_LPUART1TXSRC_TX (0 << SIM_SOPT5_LPUART1TXSRC_SHIFT) /* LPUART1_TX pin */
|
||||
# define SIM_SOPT5_LPUART1TXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART1TXSRC_SHIFT) /* LPUART1_TX pin modulated with TPM1 channel 0 output */
|
||||
# define SIM_SOPT5_LPUART1TXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART1TXSRC_SHIFT) /* LPUART1_TX pin modulated with TPM2 channel 0 output */
|
||||
#endif
|
||||
/* Bits 8-15, 18-31: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SOPT5_LPUART1RXSRC)
|
||||
/* Bits 8-15, 20-31: Reserved */
|
||||
# define SIM_SOPT5_LPUART1RXSRC_SHIFT (18) /* Bit 18: LPUART1 receive data source select */
|
||||
# define SIM_SOPT5_LPUART1RXSRC_MASK (3 << SIM_SOPT5_LPUART1RXSRC_SHIFT)
|
||||
# define SIM_SOPT5_LPUART1RXSRC_TX (0 << SIM_SOPT5_LPUART1RXSRC_SHIFT) /* LPUART1_RX pin */
|
||||
# define SIM_SOPT5_LPUART1RXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART1RXSRC_SHIFT) /* CMP0 output */
|
||||
# define SIM_SOPT5_LPUART1RXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART1RXSRC_SHIFT) /* CMP1 output */
|
||||
#endif
|
||||
|
||||
/* System Options Register 6 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT6)
|
||||
/* Bits 0-23: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SOPT6_MCC)
|
||||
/* Bits 16-23: Reserved */
|
||||
@ -660,9 +696,9 @@
|
||||
# define SIM_SOPT7_ADC3ALTTRGEN (1 << 31) /* Bit 31: ADC3 alternate trigger enable */
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT8)
|
||||
/* System Options Register 8 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT8)
|
||||
# if defined(KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT)
|
||||
# define SIM_SOPT8_FTM0SYNCBIT (1 << 0) /* Bit 0: FTM0 Hardware Trigger 0 Software Synchronization */
|
||||
# endif
|
||||
@ -726,9 +762,9 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT9)
|
||||
/* System Options Register 9 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SOPT9)
|
||||
/* Bits 0-17: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC)
|
||||
# define SIM_SOPT9_TPM1CH0SRC_SHIFT (18) /* Bits 18-19: TPM1 channel 0 input capture source select */
|
||||
@ -773,20 +809,20 @@
|
||||
# define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */
|
||||
# define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT)
|
||||
# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */
|
||||
# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */
|
||||
# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */
|
||||
# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */
|
||||
# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */
|
||||
# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */
|
||||
# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */
|
||||
# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */
|
||||
# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT) /* K20 */
|
||||
# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT) /* K30 */
|
||||
# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT) /* K40 */
|
||||
# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT) /* K60 */
|
||||
# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT) /* K70 */
|
||||
# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT) /* K50 and K52 */
|
||||
# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT) /* K51 and K53 */
|
||||
# else
|
||||
# define SIM_SDID_FAMID_K1X (0 << SIM_SDID_FAMID_SHIFT) /* K1X */
|
||||
# define SIM_SDID_FAMID_K2X (1 << SIM_SDID_FAMID_SHIFT)) /* K2X */
|
||||
# define SIM_SDID_FAMID_K3X (2 << SIM_SDID_FAMID_SHIFT)) /* K3X */
|
||||
# define SIM_SDID_FAMID_K4X (3 << SIM_SDID_FAMID_SHIFT)) /* K4X */
|
||||
# define SIM_SDID_FAMID_K6X (4 << SIM_SDID_FAMID_SHIFT)) /* K6X */
|
||||
# define SIM_SDID_FAMID_K7X (5 << SIM_SDID_FAMID_SHIFT)) /* K7X */
|
||||
# define SIM_SDID_FAMID_K2X (1 << SIM_SDID_FAMID_SHIFT) /* K2X */
|
||||
# define SIM_SDID_FAMID_K3X (2 << SIM_SDID_FAMID_SHIFT) /* K3X */
|
||||
# define SIM_SDID_FAMID_K4X (3 << SIM_SDID_FAMID_SHIFT) /* K4X */
|
||||
# define SIM_SDID_FAMID_K6X (4 << SIM_SDID_FAMID_SHIFT) /* K6X */
|
||||
# define SIM_SDID_FAMID_K7X (5 << SIM_SDID_FAMID_SHIFT) /* K7X */
|
||||
# endif
|
||||
#endif
|
||||
/* Bits 7-11: Reserved */
|
||||
@ -860,15 +896,24 @@
|
||||
/* Bits 12-31: Reserved */
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC2)
|
||||
/* System Clock Gating Control Register 2 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC2)
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_ENET) && defined(KINETIS_NENET) && KINETIS_NENET > 0
|
||||
# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_LPUART0)
|
||||
# define SIM_SCGC2_LPUART0 (1 << 4) /* Bit 4: LPUART0 Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_LPUART1)
|
||||
# define SIM_SCGC2_LPUART1 (1 << 5) /* Bit 5: LPUART1 Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_LPUART2)
|
||||
# define SIM_SCGC2_LPUART2 (1 << 6) /* Bit 6: LPUART2 Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_LPUART3)
|
||||
# define SIM_SCGC2_LPUART3 (1 << 7) /* Bit 7: LPUART3 Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_TPM1)
|
||||
# define SIM_SCGC2_TPM1 (1 << 9) /* Bit 9: TPM1 Clock Gate Control */
|
||||
# endif
|
||||
@ -876,15 +921,28 @@
|
||||
# define SIM_SCGC2_TPM2 (1 << 10) /* Bit 10: TPM2 Clock Gate Control */
|
||||
# endif
|
||||
# define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */
|
||||
# define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */
|
||||
/* Bits 14-31: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_DAC1)
|
||||
# define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */
|
||||
# endif
|
||||
/* Bits 14-21: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_LPUART4)
|
||||
# define SIM_SCGC2_LPUART4 (1 << 22) /* Bit 22: LPUART4 Clock Gate Control */
|
||||
# endif
|
||||
/* Bits 23-25: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_QSPI)
|
||||
# define SIM_SCGC2_QSPI (1 << 26) /* Bit 26: QSPI Clock Gate Control */
|
||||
# endif
|
||||
/* Bits 27-30: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC2_FLEXIO)
|
||||
# define SIM_SCGC2_FLEXIO (1 << 31) /* Bit 31: FlexIO Clock Gate Control */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC3)
|
||||
/* System Clock Gating Control Register 3 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC3)
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_RNGA) && defined(KINETIS_NRNG) && KINETIS_NRNG > 0
|
||||
# define SIM_SCGC3_RNGA (1 << 0) /* Bit 0: RNGB Clock Gate Control */
|
||||
# define SIM_SCGC3_RNGA (1 << 0) /* Bit 0: TRNG/RNGA Clock Gate Control */
|
||||
# endif
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_USBHS)
|
||||
# define SIM_SCGC3_USBHS (1 << 1) /* Bit 1: USBHS Clock Gate Control */
|
||||
@ -905,9 +963,12 @@
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_SPI2)
|
||||
# define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */
|
||||
# endif
|
||||
/* Bits 13-14: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_SPI3)
|
||||
# define SIM_SCGC3_SPI3 (1 << 13) /* Bit 13: SPI3 Clock Gate Control */
|
||||
# endif
|
||||
/* Bit 14: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_SAI1)
|
||||
# define SIM_SCGC3_SAI1 (1 << 15) /* Bit 15: SAI1 clock Gate control */
|
||||
# define SIM_SCGC3_SAI1 (1 << 15) /* Bit 15: I2S1/SAI1 clock Gate control */
|
||||
# endif
|
||||
/* Bit 16: Reserved */
|
||||
# if defined(KINETIS_SIM_HAS_SCGC3_SDHC)
|
||||
@ -967,11 +1028,14 @@
|
||||
|
||||
/* System Clock Gating Control Register 5 */
|
||||
|
||||
#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */
|
||||
#define SIM_SCGC5_LPTMR0 (1 << 0) /* Bit 0: Low Power Timer 0 Clock Gate Control */
|
||||
#if defined(KINETIS_SIM_HAS_SCGC5_REGFILE)
|
||||
# define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */
|
||||
#endif
|
||||
/* Bits 2-4: Reserved */
|
||||
/* Bits 2-3: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SCGC5_LPTMR1)
|
||||
# define SIM_SCGC5_LPTMR1 (1 << 4) /* Bit 4: Low Power Timer 1 Clock Gate Control */
|
||||
#endif
|
||||
#if defined(KINETIS_SIM_HAS_SCGC5_TSI)
|
||||
# define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */
|
||||
#endif
|
||||
@ -985,7 +1049,9 @@
|
||||
# define SIM_SCGC5_PORTF (1 << 14) /* Bit 14: Port F Clock Gate Control */
|
||||
#endif
|
||||
/* Bits 14-31: Reserved */
|
||||
|
||||
/* System Clock Gating Control Register 6 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC6_FTFL)
|
||||
# define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */
|
||||
#endif
|
||||
@ -994,7 +1060,9 @@
|
||||
#if defined(KINETIS_SIM_HAS_SCGC6_DMAMUX1)
|
||||
# define SIM_SCGC6_DMAMUX1 (1 << 2) /* Bit 2: DMA Mux 1 Clock Gate Control */
|
||||
#endif
|
||||
#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */
|
||||
#if defined(KINETIS_SIM_HAS_SCGC6_FLEXCAN0)
|
||||
# define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */
|
||||
#endif
|
||||
/* Bits 5-9: Reserved */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC6_RNGA)
|
||||
@ -1004,7 +1072,7 @@
|
||||
#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */
|
||||
#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */
|
||||
/* Bit 14: Reserved */
|
||||
#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */
|
||||
#define SIM_SCGC6_I2S0 (1 << 15) /* Bit 15: I2S0 Clock Gate Control */
|
||||
/* Bits 16-17: Reserved */
|
||||
#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */
|
||||
/* Bits 19-20: Reserved */
|
||||
@ -1016,7 +1084,6 @@
|
||||
#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */
|
||||
#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */
|
||||
#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */
|
||||
/* Bit 26: Reserved */
|
||||
#if defined(KINETIS_SIM_HAS_SCGC6_FTM2)
|
||||
# define SIM_SCGC6_FTM2 (1 << 26) /* Bit 26: FTM2 Clock Gate Control */
|
||||
#endif
|
||||
@ -1031,9 +1098,9 @@
|
||||
# define SIM_SCGC6_DAC0 (1 << 31) /* Bit 31: RTC Clock Gate Control */
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC7)
|
||||
/* System Clock Gating Control Register 7 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_SCGC7)
|
||||
# if defined(KINETIS_SIM_HAS_SCGC7_FLEXBUS)
|
||||
# define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */
|
||||
# endif
|
||||
@ -1216,28 +1283,36 @@
|
||||
# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */
|
||||
# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */
|
||||
# endif
|
||||
# if defined(KINETIS_K64) || defined(KINETIS_K66)
|
||||
# if defined(KINETIS_K28) || defined(KINETIS_K64) || defined(KINETIS_K66)
|
||||
# define SIM_FCFG1_PFSIZE_32KB (3 << SIM_FCFG1_PFSIZE_SHIFT) /* 32 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_64KB (5 << SIM_FCFG1_PFSIZE_SHIFT) /* 64 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 2048 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB of program flash memory */
|
||||
# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 2048 KB of program flash memory */
|
||||
# endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_FCFG1_NVMSIZE)
|
||||
# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size */
|
||||
# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT)
|
||||
# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */
|
||||
# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */
|
||||
# if defined(KINETIS_K28)
|
||||
# define SIM_FCFG1_NVMSIZE_32KB (3 << SIM_FCFG1_NVMSIZE_SHIFT) /* 32KB FlexNVM */
|
||||
# define SIM_FCFG1_NVMSIZE_64KB (5 << SIM_FCFG1_NVMSIZE_SHIFT) /* 64KB FlexNVM */
|
||||
# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM */
|
||||
# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM */
|
||||
# define SIM_FCFG1_NVMSIZE_512KB (11 << SIM_FCFG1_NVMSIZE_SHIFT) /* 512KB FlexNVM */
|
||||
# else
|
||||
# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */
|
||||
# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
|
||||
# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Flash Configuration Register 2 */
|
||||
/* Bits 0-15: Reserved */
|
||||
#if (KINETIS_SIM_HAS_FCFG2_MAXADDR1)
|
||||
#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR1)
|
||||
# define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-[21|22]: Max address block 1 */
|
||||
# define SIM_FCFG2_MAXADDR1_MASK (KINETIS_SIM_FCFG2_MAXADDR1_MASK << SIM_FCFG2_MAXADDR1_SHIFT)
|
||||
# define SIM_FCFG2_MAXADDR1(n) (((n) & KINETIS_SIM_FCFG2_MAXADDR1_MASK) << SIM_FCFG2_MAXADDR1_SHIFT)
|
||||
@ -1275,9 +1350,10 @@
|
||||
# define SIM_CLKDIV3_PLLFLLDIV(n) ((((n)-1) & 7) << SIM_CLKDIV3_PLLFLLDIV_SHIFT) /* n=1..8 */
|
||||
# endif
|
||||
#endif
|
||||
#if defined(KINETIS_SIM_HAS_CLKDIV4)
|
||||
|
||||
/* System Clock Divider Register 4 */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_CLKDIV4)
|
||||
# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC)
|
||||
# define SIM_CLKDIV4_TRACEFRAC_SHIFTS (0) /* Bit 0: Trace clock divider fraction */
|
||||
# define SIM_CLKDIV4_TRACEFRAC_MASK (1 << SIM_CLKDIV4_TRACEFRAC_SHIFTS)
|
||||
@ -1300,9 +1376,9 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_MCR)
|
||||
/* Misc Control Register */
|
||||
|
||||
#if defined(KINETIS_SIM_HAS_MCR)
|
||||
/* Bits 0-28: Reserved */
|
||||
# define SIM_MCR_PDBLOOP (1<< 29) /* Bit 29: PDB Loop Mode */
|
||||
/* Bit 30: Reserved */
|
||||
|
||||
@ -144,8 +144,7 @@
|
||||
|
||||
/* SDHC pull-up resistors **********************************************************/
|
||||
|
||||
/*
|
||||
* Kinetis does not have pullups on their Freedom-K28F board
|
||||
/* Kinetis does not have pullups on their Freedom-K28F board
|
||||
* So allow the board config to enable them.
|
||||
*/
|
||||
|
||||
@ -159,7 +158,7 @@
|
||||
* SDCLK frequency = (base clock) / (prescaler * divisor)
|
||||
*
|
||||
* The SDHC module is always configure configured so that the core clock is the base
|
||||
* clock. Possible values for presscaler and divisor are:
|
||||
* clock. Possible values for prescaler and divisor are:
|
||||
*
|
||||
* SDCLKFS: {2, 4, 8, 16, 32, 63, 128, 256}
|
||||
* DVS: {1..16}
|
||||
|
||||
@ -747,7 +747,7 @@ Freedom K64F Configuration Options
|
||||
CONFIG_KINETIS_FTM0 -- Support FlexTimer 0
|
||||
CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
|
||||
CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
|
||||
CONFIG_KINETIS_LPTIMER -- Support the low power timer
|
||||
CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
|
||||
CONFIG_KINETIS_RTC -- Support RTC
|
||||
CONFIG_KINETIS_SLCD -- Support the segment LCD (K3x, K4x, and K5x only)
|
||||
CONFIG_KINETIS_EWM -- Support the external watchdog
|
||||
|
||||
@ -753,7 +753,7 @@ Freedom K66F Configuration Options
|
||||
CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
|
||||
CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
|
||||
CONFIG_KINETIS_FTM3 -- Support FlexTimer 3
|
||||
CONFIG_KINETIS_LPTIMER -- Support the low power timer
|
||||
CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
|
||||
CONFIG_KINETIS_RTC -- Support RTC
|
||||
CONFIG_KINETIS_SLCD -- Support the segment LCD (K3x, K4x, and K5x only)
|
||||
CONFIG_KINETIS_EWM -- Support the external watchdog
|
||||
|
||||
@ -145,8 +145,7 @@
|
||||
|
||||
/* SDHC pull-up resistors **********************************************************/
|
||||
|
||||
/*
|
||||
* Kinetis does not have pullups on their Freedom-K66F board
|
||||
/* Kinetis does not have pullups on their Freedom-K66F board
|
||||
* So allow the board config to enable them.
|
||||
*/
|
||||
|
||||
@ -159,7 +158,7 @@
|
||||
* SDCLK frequency = (base clock) / (prescaler * divisor)
|
||||
*
|
||||
* The SDHC module is always configure configured so that the core clock is the base
|
||||
* clock. Possible values for presscaler and divisor are:
|
||||
* clock. Possible values for prescaler and divisor are:
|
||||
*
|
||||
* SDCLKFS: {2, 4, 8, 16, 32, 63, 128, 256}
|
||||
* DVS: {1..16}
|
||||
|
||||
@ -239,7 +239,7 @@ KwikStik-K40-specific Configuration Options
|
||||
CONFIG_KINETIS_FTM0 -- Support FlexTimer 0
|
||||
CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
|
||||
CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
|
||||
CONFIG_KINETIS_LPTIMER -- Support the low power timer
|
||||
CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
|
||||
CONFIG_KINETIS_RTC -- Support RTC
|
||||
CONFIG_KINETIS_SLCD -- Support the segment LCD (K40 only)
|
||||
CONFIG_KINETIS_EWM -- Support the external watchdog
|
||||
|
||||
@ -378,7 +378,7 @@ TWR-K60N512-specific Configuration Options
|
||||
CONFIG_KINETIS_FTM0 -- Support FlexTimer 0
|
||||
CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
|
||||
CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
|
||||
CONFIG_KINETIS_LPTIMER -- Support the low power timer
|
||||
CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
|
||||
CONFIG_KINETIS_RTC -- Support RTC
|
||||
CONFIG_KINETIS_SLCD -- Support the segment LCD (K60 only)
|
||||
CONFIG_KINETIS_EWM -- Support the external watchdog
|
||||
|
||||
@ -503,7 +503,7 @@ TWR-K64F120M-specific Configuration Options
|
||||
CONFIG_KINETIS_FTM0 -- Support FlexTimer 0
|
||||
CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
|
||||
CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
|
||||
CONFIG_KINETIS_LPTIMER -- Support the low power timer
|
||||
CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
|
||||
CONFIG_KINETIS_RTC -- Support RTC
|
||||
CONFIG_KINETIS_SLCD -- Support the segment LCD (K60 only)
|
||||
CONFIG_KINETIS_EWM -- Support the external watchdog
|
||||
|
||||
Loading…
Reference in New Issue
Block a user