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Add interrupt control logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2733 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-06 17:11:15 +00:00
parent d95cc990e0
commit 0f2e501caa
7 changed files with 827 additions and 19 deletions
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1
arch/arm/include/lpc17xx/irq.h
View File

@ -157,6 +157,7 @@
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_NEXTINT (35)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs

6
arch/arm/src/lpc17xx/Make.defs
View File

@ -51,13 +51,17 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
# Required LPC17xx files
CHIP_ASRCS =
CHIP_CSRCS = lpc17_gpio.c lpc17_start.c
CHIP_CSRCS = lpc17_irq.c lpc17_gpio.c lpc17_start.c
#CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \
# lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_serial.c \
# lpc17_start.c lpc17_timerisr.c
# Configuration-dependent LPC17xx files
ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += lpc17_gpioint.c
endif
ifeq ($(CONFIG_DEBUG),y)
CHIP_CSRCS += lpc17_gpiodbg.c
endif

10
arch/arm/src/lpc17xx/chip.h
View File

@ -168,6 +168,16 @@
#include "lpc17_memorymap.h"
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
/************************************************************************************
* Public Types
************************************************************************************/

16
arch/arm/src/lpc17xx/lpc17_gpio.c
View File

@ -73,8 +73,8 @@
*/
#ifdef CONFIG_GPIO_IRQ
static uint64_t g_intedge0;
static uint64_t g_intedge2;
uint64_t g_intedge0;
atic uint64_t g_intedge2;
#endif
/****************************************************************************
@ -84,6 +84,17 @@ static uint64_t g_intedge2;
* lpc17_gpiodbg.c
*/
/* We have to remember the configured interrupt setting.. PINs are not
* actually set up to interrupt until the interrupt is enabled.
*/
#ifdef CONFIG_GPIO_IRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
/* FIO register base addresses */
const uint32_t g_fiobase[GPIO_NPORTS] =
{
LPC17_FIO0_BASE,
@ -298,6 +309,7 @@ static int lpc17_setintedge(unsigned int port, unsigned int pin, unsigned int va
/* Set the requested value in the PINSEL register */
shift = pin << 1;
*intedge &= ~(3 << shift);
*intedge |= (value << shift);
}

319
arch/arm/src/lpc17xx/lpc17_gpioint.c Executable file
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@ -0,0 +1,319 @@
/****************************************************************************
* arch/arm/src/lpc17xx/lpc17_gpioint.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "chip.h"
#include "lpc17_gpio.h"
#include "lpc17_pinconn.h"
#include "lpc17_internal.h"
#ifdef CONFIG_GPIO_IRQ
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/* We have to remember the configured interrupt setting.. PINs are not
* actually set up to interrupt until the interrupt is enabled.
*/
#ifdef CONFIG_GPIO_IRQ
uint64_t g_intedge0;
atic uint64_t g_intedge2;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* These tables have global scope because they are also used in
* lpc17_gpiodbg.c
*/
/* We have to remember the configured interrupt setting.. PINs are not
* actually set up to interrupt until the interrupt is enabled.
*/
#ifdef CONFIG_GPIO_IRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
/* FIO register base addresses */
const uint32_t g_fiobase[GPIO_NPORTS] =
{
LPC17_FIO0_BASE,
LPC17_FIO1_BASE,
LPC17_FIO2_BASE,
LPC17_FIO3_BASE,
LPC17_FIO4_BASE
};
/* Port 0 and Port 2 can provide a single interrupt for any combination of
* port pins
*/
const uint32_t g_intbase[GPIO_NPORTS] =
{
LPC17_GPIOINT0_OFFSET,
0,
LPC17_GPIOINT2_OFFSET,
0,
0
};
const uint32_t g_lopinsel[GPIO_NPORTS] =
{
LPC17_PINCONN_PINSEL0,
LPC17_PINCONN_PINSEL2,
LPC17_PINCONN_PINSEL4,
0,
0
};
const uint32_t g_hipinsel[GPIO_NPORTS] =
{
LPC17_PINCONN_PINSEL1,
LPC17_PINCONN_PINSEL3,
0,
LPC17_PINCONN_PINSEL7,
LPC17_PINCONN_PINSEL9
};
const uint32_t g_lopinmode[GPIO_NPORTS] =
{
LPC17_PINCONN_PINMODE0,
LPC17_PINCONN_PINMODE2,
LPC17_PINCONN_PINMODE4,
0,
0
};
const uint32_t g_hipinmode[GPIO_NPORTS] =
{
LPC17_PINCONN_PINMODE1,
LPC17_PINCONN_PINMODE3,
0,
LPC17_PINCONN_PINMODE7,
LPC17_PINCONN_PINMODE9
};
const uint32_t g_odmode[GPIO_NPORTS] =
{
LPC17_PINCONN_ODMODE0,
LPC17_PINCONN_ODMODE1,
LPC17_PINCONN_ODMODE2,
LPC17_PINCONN_ODMODE3,
LPC17_PINCONN_ODMODE4
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: lpc17_getintedge
*
* Description:
* Get the stored interrupt edge configuration.
*
****************************************************************************/
static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin)
{
const uint64_t *intedge;
/* Which word to we use? */
if (port == 0)
{
intedge = g_intedge0;
}
else if (port == 2)
{
intedge = g_intedge2;
}
else
{
return 0;
}
/* Return the value for the PINSEL */
return (unsigned int)((*intedge & (3 << (pin << 1))) >> shift);
}
/****************************************************************************
* Name: lpc17_setintedge
*
* Description:
* Set the edge interrupt enabled bits for this pin.
*
****************************************************************************/
static void lpc17_setintedge(uint32_t intbase, unsigned int pin, unsigned int edges)
{
int regval;
/* Set/clear the rising edge enable bit */
regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
if ((edges & 2) != 0)
{
regval |= GPIOINT(pin);
}
else
{
regval &= ~GPIOINT(pin);
}
endif
putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
/* Set/clear the rising edge enable bit */
regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
if ((edges & 1) != 0)
{
regval |= GPIOINT(pin);
}
else
{
regval &= ~GPIOINT(pin);
}
endif
putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
}
/****************************************************************************
* Name: lpc17_irq2port
*
* Description:
* Get the stored interrupt edge configuration.
*
****************************************************************************/
static int lpc17_irq2port(int irq)
{
/****************************************************************************
* Global Functions
****************************************************************************/
/************************************************************************************
* Name: lpc17_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
void lpc17_gpioirqenable(int irq)
{
/* Map the IRQ number to a port number */
int port = lpc17_irq2port(irq);
if (port >= 0)
{
/* The IRQ number does correspond to an interrupt port. Now get the base
* address of the GPIOINT registers for the port.
*/
uint32_t intbase = g_intbase[GPIO_NPORTS];
if (intabase != 0)
{
/* And get the pin number associated with the port */
unsigned int pin = g_irq2pin(irq);
unsigned int edges = lpc17_getintedge(port, pin);
lpc17_setintedge(intbase, pin, edges);
}
}
}
/************************************************************************************
* Name: lpc17_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
void lpc17_gpioirqdisable(int irq)
{
/* Map the IRQ number to a port number */
int port = lpc17_irq2port(irq);
if (port >= 0)
{
/* The IRQ number does correspond to an interrupt port. Now get the base
* address of the GPIOINT registers for the port.
*/
uint32_t intbase = g_intbase[GPIO_NPORTS];
if (intabase != 0)
{
/* And get the pin number associated with the port */
unsigned int pin = g_irq2pin(irq);
lpc17_setintedge(intbase, pin, 0);
}
}
}
#warning "Still needs initialization, interrupt handling and decoding logic"
#endif /* CONFIG_GPIO_IRQ */

23
arch/arm/src/lpc17xx/lpc17_internal.h
View File

@ -355,10 +355,15 @@ extern "C" {
#define EXTERN extern
#endif
/* These tables have global scope only because they are shared between lpc_gpio.c
* and lpc17_gpiodbg.c
/* These tables have global scope only because they are shared between lpc17_gpio.c,
* lpc17_gpioint.c, and lpc17_gpiodbg.c
*/
#ifdef CONFIG_GPIO_IRQ
extern uint64_t g_intedge0;
extern uint64_t g_intedge2;
#endif
extern const uint32_t g_fiobase[GPIO_NPORTS];
extern const uint32_t g_intbase[GPIO_NPORTS];
extern const uint32_t g_lopinsel[GPIO_NPORTS];
@ -439,20 +444,6 @@ EXTERN void lpc17_gpiowrite(uint16_t pinset, bool value);
EXTERN bool lpc17_gpioread(uint16_t pinset);
/************************************************************************************
* Name: lpc17_gpioirq
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
************************************************************************************/
#ifdef CONFIG_GPIO_IRQ
EXTERN void lpc17_gpioirq(uint16_t pinset);
#else
# define lpc17_gpioirq(pinset)
#endif
/************************************************************************************
* Name: lpc17_gpioirqenable
*

471
arch/arm/src/lpc17xx/lpc17_irq.c Executable file
View File

@ -0,0 +1,471 @@
/****************************************************************************
* arch/arm/src/lpc17/lpc17_irq.c
* arch/arm/src/chip/lpc17_irq.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "nvic.h"
#include "up_arch.h"
#include "os_internal.h"
#include "up_internal.h"
#include "lpc17_internal.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* Enable NVIC debug features that are probably only desireable during
* bringup
*/
#undef LPC17_IRQ_DEBUG
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Public Data
****************************************************************************/
uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: lpc17_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(LPC17_IRQ_DEBUG) && defined (CONFIG_DEBUG)
static void lpc17_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = irqsave();
slldbg("NVIC (%s, irq=%d):\n", msg, irq);
slldbg(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
slldbg(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
slldbg(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
slldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
slldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqrestore(flags);
}
#else
# define lpc17_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: lpc17_nmi, lpc17_mpu, lpc17_busfault, lpc17_usagefault, lpc17_pendsv,
* lpc17_dbgmonitor, lpc17_pendsv, lpc17_reserved
*
* Description:
* Handlers for various execptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG
static int lpc17_nmi(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! NMI received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_busfault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Bus fault recived\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_usagefault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Usage fault received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_pendsv(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! PendSV received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_dbgmonitor(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Debug Monitor receieved\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_reserved(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Reserved interrupt\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
#endif
/****************************************************************************
* Name: lpc17_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int lpc17_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
DEBUGASSERT(irq >= LPC17_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= LPC17_IRQ_EXTINT)
{
if (irq < LPC17_IRQ_NIRQS)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - LPC17_IRQ_EXTINT);
}
if (irq < LPC17_IRQ_NIRQS)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (irq - LPC17_IRQ_EXTINT - 32);
}
else
{
return ERROR; /* Invalid interrupt */
}
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LPC17_IRQ_MPU)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == LPC17_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == LPC17_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == LPC17_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
/* Set all interrrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(LPC17_IRQ_SVCALL, up_svcall);
irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
irq_attach(LPC17_IRQ_MPU, lpc17_mpu);
irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);
irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault);
irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv);
irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor);
irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved);
#endif
lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize FIQs */
#ifdef CONFIG_ARCH_FIQ
up_fiqinitialize();
#endif
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_GPIO_IRQ
lpc17_gpioirqinitialize();
#endif
/* And finally, enable interrupts */
setbasepri(NVIC_SYSH_PRIORITY_MAX);
irqrestore(0);
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uint32_t regaddr;
uint32_t regval;
uint32_t bit;
if (lpc17_irqinfo(irq, &regaddr, &bit) == 0)
{
/* Clear the appropriate bit in the register to enable the interrupt */
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
#ifdef CONFIG_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
lpc17_gpioirqdisable(irq);
}
#endif
lpc17_dumpnvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uint32_t regaddr;
uint32_t regval;
uint32_t bit;
if (lpc17_irqinfo(irq, &regaddr, &bit) == 0)
{
/* Set the appropriate bit in the register to enable the interrupt */
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
#ifdef CONFIG_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
lpc17_gpioirqenable(irq);
}
#endif
lpc17_dumpnvic("enable", irq);
}
/****************************************************************************
* Name: up_maskack_irq
*
* Description:
* Mask the IRQ and acknowledge it
*
****************************************************************************/
void up_maskack_irq(int irq)
{
up_disable_irq(irq);
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= LPC17_IRQ_MPU && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < LPC17_IRQ_EXTINT)
{
irq -= 4;
regaddr = NVIC_SYSH_PRIORITY(irq);
}
else
{
irq -= LPC17_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
lpc17_dumpnvic("prioritize", irq);
return OK;
}
#endif