TMS570: Correct a few problems introduced in previous commits
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@ -86,7 +86,7 @@
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#define TMS570_ESM_IECR1 (TMS570_ESM_BASE+TMS570_ESM_IECR1_OFFSET)
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#define TMS570_ESM_ILSR1 (TMS570_ESM_BASE+TMS570_ESM_ILSR1_OFFSET)
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#define TMS570_ESM_ILCR1 (TMS570_ESM_BASE+TMS570_ESM_ILCR1_OFFSET)
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#define TMS570_ESM_SR1(n) (TMS570_ESM_BASE+TMS570_ESM_SR_OFFSET(n))
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#define TMS570_ESM_SR(n) (TMS570_ESM_BASE+TMS570_ESM_SR_OFFSET(n))
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# define TMS570_ESM_SR1 (TMS570_ESM_BASE+TMS570_ESM_SR1_OFFSET)
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# define TMS570_ESM_SR2 (TMS570_ESM_BASE+TMS570_ESM_SR2_OFFSET)
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# define TMS570_ESM_SR3 (TMS570_ESM_BASE+TMS570_ESM_SR3_OFFSET)
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@ -161,7 +161,7 @@
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#define ESM_EKR_MASK 0x0000000f /* Bits 0-3: Error key value */
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# define ESM_EKR_NORMAL 0x00000000 /* Activates normal mode */
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# define ESM_EKR_ERROR 0x00000005 /* nERROR set high when LTC completes */
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# define ESM_EKR_NORMAL 0x0000000a /* Forces error on nERROR pin */
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# define ESM_EKR_FORCE 0x0000000a /* Forces error on nERROR pin */
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/* ESM Status Shadow Register 2 */
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@ -56,9 +56,12 @@
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#include "arm.h"
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#include "cache.h"
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#include "fpu.h"
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#include "sctlr.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip/tms570_esm.h"
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#include "tms570_clockconfig.h"
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#include "tms570_boot.h"
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/****************************************************************************
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@ -185,7 +188,7 @@ static inline void tms570_event_export(void)
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{
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uint32_t pmcr = cp15_rdpmcr();
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pmcr |= PCMR_X;
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cp15_wrpmcr(pmcr)
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cp15_wrpmcr(pmcr);
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}
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/****************************************************************************
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