From 0faf8612562d4bd416180c8ba578b545f25a6ae8 Mon Sep 17 00:00:00 2001 From: Sara Souza Date: Tue, 6 Oct 2020 16:31:02 -0300 Subject: [PATCH] xtensa/esp32: Added Timer Support --- arch/xtensa/include/esp32/irq.h | 5 +- arch/xtensa/src/esp32/Kconfig | 28 +- arch/xtensa/src/esp32/Make.defs | 7 + arch/xtensa/src/esp32/esp32_cpuint.c | 10 +- arch/xtensa/src/esp32/esp32_cpuint.h | 2 +- arch/xtensa/src/esp32/esp32_tim.c | 917 ++++++++++++++++++ arch/xtensa/src/esp32/esp32_tim.h | 127 +++ arch/xtensa/src/esp32/esp32_tim_lowerhalf.c | 640 ++++++++++++ arch/xtensa/src/esp32/esp32_tim_lowerhalf.h | 42 + arch/xtensa/src/esp32/hardware/esp32_soc.h | 1 + arch/xtensa/src/esp32/hardware/esp32_tim.h | 889 +++++++++++++++++ .../esp32/esp32-core/configs/timer/defconfig | 54 ++ boards/xtensa/esp32/esp32-core/src/Makefile | 6 + .../xtensa/esp32/esp32-core/src/esp32-core.h | 11 + .../esp32/esp32-core/src/esp32_bringup.c | 64 ++ .../xtensa/esp32/esp32-core/src/esp32_timer.c | 58 ++ include/nuttx/timers/timer.h | 2 +- 17 files changed, 2842 insertions(+), 21 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_tim.c create mode 100644 arch/xtensa/src/esp32/esp32_tim.h create mode 100644 arch/xtensa/src/esp32/esp32_tim_lowerhalf.c create mode 100644 arch/xtensa/src/esp32/esp32_tim_lowerhalf.h create mode 100644 arch/xtensa/src/esp32/hardware/esp32_tim.h create mode 100644 boards/xtensa/esp32/esp32-core/configs/timer/defconfig create mode 100644 boards/xtensa/esp32/esp32-core/src/esp32_timer.c diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 6c31d2c788..b2d1c9e964 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -181,8 +181,9 @@ * 0x03c0 Double exception * * REVISIT: In more architectures supported by NuttX, exception errors - * tie into the normal interrupt handling via special IRQ numbers. I - * is still to be determined what will be done for the ESP32. + * tie into the normal interrupt handling via special IRQ numbers. + * It is still to be determined what will be done for the ESP32. + * */ /* IRQ numbers for internal interrupts that are dispatched like peripheral diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index a441b5e709..96b8234d6c 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -31,6 +31,10 @@ config ESP32_UART bool default n +config ESP32_TIMER + bool + default n + config ESP32_BT bool "Bluetooth" default n @@ -160,32 +164,32 @@ config XTENSA_TIMER2 default n config ESP32_TIMER0 - bool "64-bit Timer 0" + bool "64-bit Timer 0 (Group 0 Timer 0)" default n - depends on EXPERIMENTAL + select ESP32_TIMER ---help--- - No yet implemented + Enables Timer config ESP32_TIMER1 - bool "64-bit Timer 1" + bool "64-bit Timer 1 (Group 0 Timer 1)" default n - depends on EXPERIMENTAL + select ESP32_TIMER ---help--- - No yet implemented + Enables Timer config ESP32_TIMER2 - bool "64-bit Timer 2" + bool "64-bit Timer 2 (Group 1 Timer 0)" default n - depends on EXPERIMENTAL + select ESP32_TIMER ---help--- - No yet implemented + Enables Timer config ESP32_TIMER3 - bool "64-bit Timer 3" + bool "64-bit Timer 3 (Group 1 Timer 1)" default n - depends on EXPERIMENTAL + select ESP32_TIMER ---help--- - No yet implemented + Enables Timer config ESP32_MWDT0 bool "Timer 0 Watchdog" diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index abc9f7fc3a..55d2229aba 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -138,6 +138,13 @@ ifeq ($(CONFIG_ESP32_RNG),y) CMN_CSRCS += esp32_rng.c endif +ifeq ($(CONFIG_ESP32_TIMER),y) +CHIP_CSRCS += esp32_tim.c +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += esp32_tim_lowerhalf.c +endif +endif + ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y) CHIP_CSRCS += esp32_modtext.c CMN_ASRCS += xtensa_loadstore.S diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index aa41b1d4ed..718d7376f9 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_irq.c + * arch/xtensa/src/esp32/esp32_cpuint.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -242,7 +242,7 @@ static int esp32_alloc_cpuint(uint32_t intmask) int cpuint; int ret = -ENOMEM; - /* Check if there are is CPU interrupts with the requested properties + /* Check if there are CPU interrupts with the requested properties * available. */ @@ -416,7 +416,7 @@ void up_disable_irq(int cpuint) * Name: up_enable_irq * * Description: - * Ensable the CPU interrupt specified by 'cpuint' + * Enable the CPU interrupt specified by 'cpuint' * ****************************************************************************/ @@ -504,7 +504,7 @@ int esp32_alloc_edgeint(int priority) * Name: esp32_free_cpuint * * Description: - * Free a previoulsy allocated CPU interrupt + * Free a previously allocated CPU interrupt * * Input Parameters: * The CPU interrupt number to be freed @@ -551,7 +551,7 @@ void esp32_free_cpuint(int cpuint) * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned to + * periphid - The peripheral number from irq.h to be assigned to * a CPU interrupt. * cpuint - The CPU interrupt to receive the peripheral interrupt * assignment. diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index cd602fc735..afe08ccffb 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -144,7 +144,7 @@ void esp32_free_cpuint(int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned to + * periphid - The peripheral number from irq.h to be assigned to * a CPU interrupt. * cpuint - The CPU interrupt to receive the peripheral interrupt * assignment. diff --git a/arch/xtensa/src/esp32/esp32_tim.c b/arch/xtensa/src/esp32/esp32_tim.c new file mode 100644 index 0000000000..55e926280c --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tim.c @@ -0,0 +1,917 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_tim.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "xtensa.h" + +#include "hardware/esp32_tim.h" + +#include "esp32_tim.h" +#include "esp32_cpuint.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32_tim_priv_s +{ + FAR struct esp32_tim_ops_s *ops; + uint32_t base; /* Timer register base address */ + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* Interrupt ID */ + int cpuint; /* CPU interrupt assigned to this timer */ + bool inuse; /* Flag indicating if the timer is in use */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* TIM registers access *****************************************************/ + +static uint32_t esp32_tim_getreg(FAR struct esp32_tim_dev_s *dev, + uint32_t offset); +static void esp32_tim_putreg(FAR struct esp32_tim_dev_s *dev, + uint32_t offset, + uint32_t value); +static void esp32_tim_modifyreg32(FAR struct esp32_tim_dev_s *dev, + uint32_t offset, + uint32_t clearbits, + uint32_t setbits); + +/* TIM helpers **************************************************************/ + +/* TIM operations ***********************************************************/ + +static int esp32_tim_start(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_stop(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_clear(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_configure(FAR struct esp32_tim_dev_s *dev, uint16_t pre, + uint8_t mode, uint64_t counter_value, + uint64_t alarm_value, bool alarm, + bool autoreload); +static int esp32_tim_setmode(FAR struct esp32_tim_dev_s *dev, uint8_t mode); +static int esp32_tim_setpre(FAR struct esp32_tim_dev_s *dev, uint16_t pre); +static int esp32_tim_getconfig(FAR struct esp32_tim_dev_s *dev, + uint32_t *value); +static int esp32_tim_getcounter(FAR struct esp32_tim_dev_s *dev, + uint64_t *value); +static int esp32_tim_setcounter(FAR struct esp32_tim_dev_s *dev, + uint64_t value); +static int esp32_tim_getalarmvalue(FAR struct esp32_tim_dev_s *dev, + uint64_t *value); +static int esp32_tim_setalarmvalue(FAR struct esp32_tim_dev_s *dev, + uint64_t value); +static int esp32_tim_setalarm(FAR struct esp32_tim_dev_s *dev, bool enable); +static int esp32_tim_setautoreload(FAR struct esp32_tim_dev_s *dev, + bool enable); +static int esp32_tim_setisr(FAR struct esp32_tim_dev_s *dev, xcpt_t handler, + FAR void * arg); +static int esp32_tim_enableint(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_disableint(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_checkint(FAR struct esp32_tim_dev_s *dev); +static int esp32_tim_ackint(FAR struct esp32_tim_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ESP32 TIM ops */ + +struct esp32_tim_ops_s esp32_tim_ops = +{ + .start = esp32_tim_start, + .stop = esp32_tim_stop, + .clear = esp32_tim_clear, + .configure = esp32_tim_configure, + .setmode = esp32_tim_setmode, + .getcounter = esp32_tim_getcounter, + .setpre = esp32_tim_setpre, + .getconfig = esp32_tim_getconfig, + .setcounter = esp32_tim_setcounter, + .getalarmvalue = esp32_tim_getalarmvalue, + .setalarmvalue = esp32_tim_setalarmvalue, + .setalarm = esp32_tim_setalarm, + .setautoreload = esp32_tim_setautoreload, + .setisr = esp32_tim_setisr, + .enableint = esp32_tim_enableint, + .disableint = esp32_tim_disableint, + .checkint = esp32_tim_checkint, + .ackint = esp32_tim_ackint +}; + +#ifdef CONFIG_ESP32_TIMER0 +/* TIMER0 */ + +struct esp32_tim_priv_s g_esp32_tim0_priv = +{ + .ops = &esp32_tim_ops, + .base = TIMG_T0CONFIG_REG(0), + .periph = ESP32_PERIPH_TG_T0_LEVEL, /* Peripheral ID */ + .irq = ESP32_IRQ_TG_T0_LEVEL, /* Interrupt ID */ + .cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */ + .inuse = false, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER1 +/* TIMER1 */ + +struct esp32_tim_priv_s g_esp32_tim1_priv = +{ + .ops = &esp32_tim_ops, + .base = TIMG_T1CONFIG_REG(0), + .periph = ESP32_PERIPH_TG_T1_LEVEL, /* Peripheral ID */ + .irq = ESP32_IRQ_TG_T1_LEVEL, /* Interrupt ID */ + .cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */ + .inuse = false, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER2 +/* TIMER2 */ + +struct esp32_tim_priv_s g_esp32_tim2_priv = +{ + .ops = &esp32_tim_ops, + .base = TIMG_T0CONFIG_REG(1), + .periph = ESP32_PERIPH_TG1_T0_LEVEL, /* Peripheral ID */ + .irq = ESP32_IRQ_TG1_T0_LEVEL, /* Interrupt ID */ + .cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */ + .inuse = false, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER3 +/* TIMER3 */ + +struct esp32_tim_priv_s g_esp32_tim3_priv = +{ + .ops = &esp32_tim_ops, + .base = TIMG_T1CONFIG_REG(1), + .periph = ESP32_PERIPH_TG1_T1_LEVEL, /* Peripheral ID */ + .irq = ESP32_IRQ_TG1_T1_LEVEL, /* Interrupt ID */ + .cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */ + .inuse = false, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_tim_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static uint32_t esp32_tim_getreg(FAR struct esp32_tim_dev_s *dev, + uint32_t offset) +{ + DEBUGASSERT(dev); + + return getreg32(((struct esp32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: esp32_tim_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static void esp32_tim_putreg(FAR struct esp32_tim_dev_s *dev, + uint32_t offset, + uint32_t value) +{ + DEBUGASSERT(dev); + + putreg32(value, ((struct esp32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: esp32_tim_modifyreg32 + * + * Description: + * Modify a reg of 32 bits + * + ****************************************************************************/ + +static void esp32_tim_modifyreg32(FAR struct esp32_tim_dev_s *dev, + uint32_t offset, + uint32_t clearbits, + uint32_t setbits) +{ + DEBUGASSERT(dev); + + modifyreg32(((struct esp32_tim_priv_s *)dev)->base + offset, + clearbits, setbits); +} + +/**************************************************************************** + * Name: esp32_tim_start + * + * Description: + * Releases the counter + * + ****************************************************************************/ + +static int esp32_tim_start(FAR struct esp32_tim_dev_s *dev) +{ + DEBUGASSERT(dev); + + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, 0, TIMG_T0_EN); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_stop + * + * Description: + * Halts the counter + * + ****************************************************************************/ + +static int esp32_tim_stop(FAR struct esp32_tim_dev_s *dev) +{ + DEBUGASSERT(dev); + + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_EN, 0); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_clear + * + * Description: + * Set the counter to zero instantly + * + ****************************************************************************/ + +static int esp32_tim_clear(FAR struct esp32_tim_dev_s *dev) +{ + uint32_t clear_value = 0; + + DEBUGASSERT(dev); + + esp32_tim_putreg(dev, TIM_LOAD_LO_OFFSET, clear_value); + esp32_tim_putreg(dev, TIM_LOAD_HI_OFFSET, clear_value); + + /* Dummy value to trigger reload the counter with the previous value */ + + esp32_tim_putreg(dev, TIM_LOAD_OFFSET, BIT(0)); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_configure + * + * Description: + * Configure prescaler divider, counter mode (up/down), counter value, + * Reload Event + * and alarm trigger value. + * + ****************************************************************************/ + +static int esp32_tim_configure(FAR struct esp32_tim_dev_s *dev, uint16_t pre, + uint8_t mode, uint64_t counter_value, + uint64_t alarm_value, bool alarm, + bool autoreload) +{ + int ret = OK; + + DEBUGASSERT(dev); + + /* Change the prescaler divider with the timer enabled can lead to + * unpredictable results, so it is disabled before configuring + */ + + ret = esp32_tim_stop(dev); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER prescaler */ + + ret = esp32_tim_setpre(dev, pre); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER mode */ + + ret = esp32_tim_setmode(dev, mode); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER counter value */ + + ret = esp32_tim_setcounter(dev, counter_value); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER alarm value */ + + ret = esp32_tim_setalarmvalue(dev, counter_value); + if (ret != OK) + { + goto errout; + } + + /* Enable TIMER alarm */ + + ret = esp32_tim_setalarm(dev, alarm); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER auto-reload */ + + ret = esp32_tim_setautoreload(dev, autoreload); + if (ret != OK) + { + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_tim_setmode + * + * Description: + * Set counter mode (up/down) + * + ****************************************************************************/ + +static int esp32_tim_setmode(FAR struct esp32_tim_dev_s *dev, uint8_t mode) +{ + int ret = OK; + + DEBUGASSERT(dev); + + switch (mode) + { + case ESP32_TIM_MODE_DOWN: + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_INCREASE, 0); + break; + } + + case ESP32_TIM_MODE_UP: + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, 0, TIMG_T0_INCREASE); + break; + } + + default: + { + tmrerr("ERROR: unsupported TIMER mode %d\n", mode); + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_tim_setpre + * + * Description: + * Set prescaler divider (2 - 65356) + * 0 = 65536 + * 1,2 = 2 + * + ****************************************************************************/ + +static int esp32_tim_setpre(FAR struct esp32_tim_dev_s *dev, uint16_t pre) +{ + uint32_t mask = (uint32_t)pre << TIMG_T0_DIVIDER_S; + + DEBUGASSERT(dev); + + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_DIVIDER_M, mask); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_getconfig + * + * Description: + * Get the current configuration from config reg + * + ****************************************************************************/ + +static int esp32_tim_getconfig(FAR struct esp32_tim_dev_s *dev, + uint32_t *value) +{ + DEBUGASSERT(dev); + + /* Read value */ + + *value = esp32_tim_getreg(dev, TIM_CONFIG_OFFSET); /* High 32 bits */ + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_getcounter + * + * Description: + * Get the current counter value + * + ****************************************************************************/ + +static int esp32_tim_getcounter(FAR struct esp32_tim_dev_s *dev, + uint64_t *value) +{ + uint32_t value_32; + + DEBUGASSERT(dev); + + *value = 0; + + /* Dummy value to latch the counter value to read it */ + + esp32_tim_putreg(dev, TIM_UPDATE_OFFSET, BIT(0)); + + /* Read value */ + + value_32 = esp32_tim_getreg(dev, TIM_HI_OFFSET); /* High 32 bits */ + + *value |= (uint64_t)value_32; + + *value <<= SHIFT_32; + + value_32 = esp32_tim_getreg(dev, TIM_LO_OFFSET); /* Low 32 bits */ + + *value |= (uint64_t)value_32; + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_setcounter + * + * Description: + * Set the value to be loaded to the counter + * It may be loaded at an alarm or instantly + * + ****************************************************************************/ + +static int esp32_tim_setcounter(FAR struct esp32_tim_dev_s *dev, + uint64_t value) +{ + uint64_t low_64 = value & LOW_32_MASK; + uint64_t high_64 = (value >> SHIFT_32) & LOW_32_MASK; + + DEBUGASSERT(dev); + + /* Set the counter value */ + + esp32_tim_putreg(dev, TIM_LOAD_LO_OFFSET, (uint32_t)low_64); + esp32_tim_putreg(dev, TIM_LOAD_HI_OFFSET, (uint32_t)high_64); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_getalarmvalue + * + * Description: + * Get the alarm value. + * + ****************************************************************************/ + +static int esp32_tim_getalarmvalue(FAR struct esp32_tim_dev_s *dev, + uint64_t *value) +{ + uint32_t value_32; + + DEBUGASSERT(dev); + + *value = 0; + + /* Read value */ + + value_32 = esp32_tim_getreg(dev, TIMG_ALARM_HI_OFFSET); /* High 32 bits */ + + *value |= (uint64_t)value_32; + + *value <<= SHIFT_32; + + value_32 = esp32_tim_getreg(dev, TIMG_ALARM_LO_OFFSET); /* Low 32 bits */ + + *value |= (uint64_t)value_32; + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_setalarmvalue + * + * Description: + * Set the value that will trigger an alarm when the + * counter value matches this value. + * + ****************************************************************************/ + +static int esp32_tim_setalarmvalue(FAR struct esp32_tim_dev_s *dev, + uint64_t value) +{ + uint64_t low_64 = value & LOW_32_MASK; + uint64_t high_64 = (value >> SHIFT_32) & LOW_32_MASK; + + DEBUGASSERT(dev); + + /* Set an alarm value */ + + esp32_tim_putreg(dev, TIMG_ALARM_LO_OFFSET, (uint32_t)low_64); + esp32_tim_putreg(dev, TIMG_ALARM_HI_OFFSET, (uint32_t)high_64); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_setalarm + * + * Description: + * Enables/Disables the alarm. + * + ****************************************************************************/ + +static int esp32_tim_setalarm(FAR struct esp32_tim_dev_s *dev, bool enable) +{ + DEBUGASSERT(dev); + + if (enable) + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, 0, TIMG_T0_ALARM_EN); + } + else + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_ALARM_EN, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_setautoreload + * + * Description: + * Enable or disabales the auto reload. If is set the counter auto + * reloads when it matches the alarm value, otherwise, the counter + * continues to increment or decrement after the alarm. The alarm also + * needs to be enabled to trigger a reload event. + * + ****************************************************************************/ + +static int esp32_tim_setautoreload(FAR struct esp32_tim_dev_s *dev, + bool enable) +{ + DEBUGASSERT(dev); + + if (enable) + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, 0, TIMG_T0_AUTORELOAD); + } + else + { + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_AUTORELOAD, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_setisr + * + * Description: + * Allocates an Edge CPU Interrupt, connects the peripheral source to this + * Interrupt, register the callback and enables the Interruption. It does + * opposite if the handler and arg are NULL. + * + ****************************************************************************/ + +static int esp32_tim_setisr(FAR struct esp32_tim_dev_s *dev, xcpt_t handler, + FAR void *arg) +{ + FAR struct esp32_tim_priv_s *tim = NULL; + int ret = OK; + uint8_t cpu; + + DEBUGASSERT(dev); + + tim = (FAR struct esp32_tim_priv_s *)dev; + + /* Disable interrupt when callback is removed */ + + if (handler == NULL) + { + /* If a CPU Interrupt was previously allocated, then deallocate it */ + + if (tim->cpuint >= 0) + { + /* Disable CPU Interrupt, free a previously allocated + * CPU Interrupt + */ + + up_disable_irq(tim->cpuint); + cpu = up_cpu_index(); + esp32_detach_peripheral(cpu, tim->periph, tim->cpuint); + esp32_free_cpuint(tim->cpuint); + irq_detach(tim->irq); + } + + ret = OK; + goto errout; + } + + /* Otherwise set callback and enable interrupt */ + + /* Verify the available CPU Interrupt */ + + tim->cpuint = esp32_alloc_levelint(1); + if (tim->cpuint < 0) + { + tmrerr("ERROR: No CPU Interrupt available"); + ret = tim->cpuint; + goto errout; + } + + /* Disable the provided CPU Interrupt to configure it */ + + up_disable_irq(tim->cpuint); + + /* Attach a peripheral interrupt to the available CPU interrupt in + * the current core + */ + + cpu = up_cpu_index(); + esp32_attach_peripheral(cpu, tim->periph, tim->cpuint); + + /* Associate an IRQ Number (from the timer) to an ISR */ + + ret = irq_attach(tim->irq, handler, arg); + + if (ret != OK) + { + esp32_detach_peripheral(cpu, tim->periph, tim->cpuint); + esp32_free_cpuint(tim->cpuint); + tmrerr("ERROR: Failed to associate an IRQ Number"); + goto errout; + } + + /* Enable the CPU Interrupt that is linked to the timer */ + + up_enable_irq(tim->cpuint); + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_tim_enableint + * + * Description: + * Enables an Edge Interrupt at the alarm if it is set. + * + ****************************************************************************/ + +static int esp32_tim_enableint(FAR struct esp32_tim_dev_s *dev) +{ + DEBUGASSERT(dev); + + /* Set the edge interrupt bit */ + + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, 0, TIMG_T0_LEVEL_INT_EN); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_disableint + * + * Description: + * Disables an Edge Interrupt at the alarm if it is set. + * + ****************************************************************************/ + +static int esp32_tim_disableint(FAR struct esp32_tim_dev_s *dev) +{ + DEBUGASSERT(dev); + + esp32_tim_modifyreg32(dev, TIM_CONFIG_OFFSET, TIMG_T0_LEVEL_INT_EN, 0); + + return OK; +} + +/**************************************************************************** + * Name: esp32_tim_checkint + * + * Description: + * Check the interrupt status bit. + * + ****************************************************************************/ + +static int esp32_tim_checkint(FAR struct esp32_tim_dev_s *dev) +{ + int ret = 0; + uint32_t reg_value; + + DEBUGASSERT(dev); + + /* Timer 0 from group 0 or 1 */ + + if (((struct esp32_tim_priv_s *)dev)->base == TIMG_T0CONFIG_REG(0) || + ((struct esp32_tim_priv_s *)dev)->base == TIMG_T0CONFIG_REG(1)) + { + reg_value = esp32_tim_getreg(dev, TIM0_INT_ST_OFFSET); + if (reg_value & TIMG_T0_INT_ST) + { + ret = 1; + } + } + + /* Timer 1 from group 0 or 1 */ + + else + { + reg_value = esp32_tim_getreg(dev, TIM1_INT_ST_OFFSET); + if (reg_value & TIMG_T1_INT_ST) + { + ret = 1; + } + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_tim_ackint + * + * Description: + * Acknowledges an interrupt + * + ****************************************************************************/ + +static int esp32_tim_ackint(FAR struct esp32_tim_dev_s *dev) +{ + DEBUGASSERT(dev); + + /* Timer 0 from group 0 or 1 */ + + if (((struct esp32_tim_priv_s *)dev)->base == TIMG_T0CONFIG_REG(0) || + ((struct esp32_tim_priv_s *)dev)->base == TIMG_T0CONFIG_REG(1)) + { + esp32_tim_putreg(dev, TIM0_CLR_OFFSET, TIMG_T0_INT_CLR); + } + + /* Timer 1 from group 0 or 1 */ + + else + { + esp32_tim_putreg(dev, TIM1_CLR_OFFSET, TIMG_T1_INT_CLR); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_tim_init + * + * Description: + * Initialize TIMER device + * + ****************************************************************************/ + +FAR struct esp32_tim_dev_s *esp32_tim_init(int timer) +{ + FAR struct esp32_tim_priv_s *tim = NULL; + + /* Get timer instance */ + + switch (timer) + { +#ifdef CONFIG_ESP32_TIMER0 + case 0: + { + tim = &g_esp32_tim0_priv; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER1 + case 1: + { + tim = &g_esp32_tim1_priv; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER2 + case 2: + { + tim = &g_esp32_tim2_priv; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER3 + case 3: + { + tim = &g_esp32_tim3_priv; + break; + } +#endif + + default: + { + tmrerr("ERROR: unsupported TIMER %d\n", timer); + goto errout; + } + } + + if (tim->inuse == true) + { + tmrerr("ERROR: TIMER %d is already in use\n", timer); + tim = NULL; + } + + errout: + return (FAR struct esp32_tim_dev_s *)tim; +} + +/**************************************************************************** + * Name: esp32_tim_deinit + * + * Description: + * Deinit TIMER device + * + ****************************************************************************/ + +int esp32_tim_deinit(FAR struct esp32_tim_dev_s *dev) +{ + FAR struct esp32_tim_priv_s *tim = NULL; + + DEBUGASSERT(dev); + + tim = (FAR struct esp32_tim_priv_s *)dev; + + tim->inuse = false; + + return OK; +} diff --git a/arch/xtensa/src/esp32/esp32_tim.h b/arch/xtensa/src/esp32/esp32_tim.h new file mode 100644 index 0000000000..c92c7a126e --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tim.h @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define ESP32_TIM_START(d) ((d)->ops->start(d)) +#define ESP32_TIM_STOP(d) ((d)->ops->stop(d)) +#define ESP32_TIM_CLEAR(d) ((d)->ops->clear(d)) +#define ESP32_TIM_CONFIGURE(d, p, m, c, av, a, ar) ((d)->ops->configure(d, m, c, av, a, ar)) +#define ESP32_TIM_SETMODE(d, m) ((d)->ops->setmode(d, m)) +#define ESP32_TIM_SETPRE(d, p) ((d)->ops->setpre(d, p)) +#define ESP32_TIM_GETCONFIG(d, v) ((d)->ops->getconfig(d, v)) +#define ESP32_TIM_GETCTR(d, v) ((d)->ops->getcounter(d, v)) +#define ESP32_TIM_SETCTR(d, v) ((d)->ops->setcounter(d, v)) +#define ESP32_TIM_GETALRVL(d, v) ((d)->ops->getalarmvalue(d, v)) +#define ESP32_TIM_SETALRVL(d, v) ((d)->ops->setalarmvalue(d, v)) +#define ESP32_TIM_SETALRM(d, e) ((d)->ops->setalarm(d, e)) +#define ESP32_TIM_SETARLD(d, e) ((d)->ops->setautoreload(d, e)) +#define ESP32_TIM_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg)) +#define ESP32_TIM_ENABLEINT(d) ((d)->ops->enableint(d)) +#define ESP32_TIM_DISABLEINT(d) ((d)->ops->disableint(d)) +#define ESP32_TIM_CHECKINT(d) ((d)->ops->checkint(d)) +#define ESP32_TIM_ACKINT(d) ((d)->ops->ackint(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Timer mode */ + +enum esp32_tim_mode_e +{ + ESP32_TIM_MODE_DOWN, + ESP32_TIM_MODE_UP, +}; + +/* ESP32 TIM device */ + +struct esp32_tim_dev_s +{ + struct esp32_tim_ops_s *ops; +}; + +/* ESP32 TIM ops */ + +/* This is a struct containing the pointers to the timer operations */ + +struct esp32_tim_ops_s +{ + /* Timer tasks */ + + CODE int (*start)(FAR struct esp32_tim_dev_s *dev); + CODE int (*stop)(FAR struct esp32_tim_dev_s *dev); + CODE int (*clear)(FAR struct esp32_tim_dev_s *dev); + + /* Timer configuration */ + + CODE int (*configure)(FAR struct esp32_tim_dev_s *dev, uint16_t pre, + uint8_t mode, uint64_t counter_value, + uint64_t alarm_value, bool alarm, + bool autoreload); + + /* Timer operations */ + + CODE int (*setmode)(FAR struct esp32_tim_dev_s *dev, uint8_t mode); + CODE int (*setpre)(FAR struct esp32_tim_dev_s *dev, uint16_t pre); + CODE int (*getconfig)(FAR struct esp32_tim_dev_s *dev, uint32_t *value); + CODE int (*getcounter)(FAR struct esp32_tim_dev_s *dev, uint64_t *value); + CODE int (*setcounter)(FAR struct esp32_tim_dev_s *dev, uint64_t value); + CODE int (*getalarmvalue)(FAR struct esp32_tim_dev_s *dev, + uint64_t *value); + CODE int (*setalarmvalue)(FAR struct esp32_tim_dev_s *dev, uint64_t value); + CODE int (*setalarm)(FAR struct esp32_tim_dev_s *dev, bool enable); + CODE int (*setautoreload)(FAR struct esp32_tim_dev_s *dev, bool enable); + + /* Timer interrupts */ + + CODE int (*setisr)(FAR struct esp32_tim_dev_s *dev, xcpt_t handler, + FAR void * arg); + CODE int (*enableint)(FAR struct esp32_tim_dev_s *dev); + CODE int (*disableint)(FAR struct esp32_tim_dev_s *dev); + CODE int (*checkint)(FAR struct esp32_tim_dev_s *dev); + CODE int (*ackint)(FAR struct esp32_tim_dev_s *dev); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +FAR struct esp32_tim_dev_s *esp32_tim_init(int timer); +int esp32_tim_deinit(FAR struct esp32_tim_dev_s *dev); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H */ diff --git a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c new file mode 100644 index 0000000000..58b815d379 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c @@ -0,0 +1,640 @@ +/**************************************************************************** + * arch/arm/src/esp32/esp32_tim_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "xtensa.h" +#include "hardware/esp32_soc.h" +#include "esp32_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TIMER configuration */ + +/* Lowest divider, Highest Frequency Best Resolution */ +#define ESP32_TIMER_PRESCALER 2 +/* Number of cycles to complete 1 microsecond */ +#define ESP32_1USECOND ((TB_CLK_FREQ/ESP32_TIMER_PRESCALER)/1000000) +#define ESP32_INIT_CNTR_VALUE 0 /* Initial counter value */ +#define ESP32_TIMER_MAX_USECOND 0xffffffff +#define ESP32_TIMER_MAX (ESP32_1USECOND*ESP32_TIMER_MAX_USECOND) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32_timer_lowerhalf_s +{ + FAR const struct timer_ops_s *ops; /* Lower half operations */ + FAR struct esp32_tim_dev_s *tim; /* esp32 timer driver */ + tccb_t callback; /* Current user interrupt callback */ + FAR void *arg; /* Argument passed to upper half callback */ + bool started; /* True: Timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int esp32_timer_handler(int irq, void *context, void *arg); + +/* "Lower half" driver methods **********************************************/ + +static int esp32_timer_start(FAR struct timer_lowerhalf_s *lower); +static int esp32_timer_stop(FAR struct timer_lowerhalf_s *lower); +static int esp32_timer_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s *status); +static int esp32_timer_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout); +static int esp32_timer_maxtimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t *timeout); +static void esp32_timer_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct timer_ops_s g_esp32_timer_ops = +{ + .start = esp32_timer_start, + .stop = esp32_timer_stop, + .getstatus = esp32_timer_getstatus, + .settimeout = esp32_timer_settimeout, + .setcallback = esp32_timer_setcallback, + .maxtimeout = esp32_timer_maxtimeout, + .ioctl = NULL, +}; + +#ifdef CONFIG_ESP32_TIMER0 +/* TIMER0 lower-half */ + +static struct esp32_timer_lowerhalf_s g_esp32_timer0_lowerhalf = +{ + .ops = &g_esp32_timer_ops, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER1 +/* TIMER1 lower-half */ + +static struct esp32_timer_lowerhalf_s g_esp32_timer1_lowerhalf = +{ + .ops = &g_esp32_timer_ops, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER2 +/* TIMER2 lower-half */ + +static struct esp32_timer_lowerhalf_s g_esp32_timer2_lowerhalf = +{ + .ops = &g_esp32_timer_ops, +}; +#endif + +#ifdef CONFIG_ESP32_TIMER3 +/* TIMER3 lower-half */ + +static struct esp32_timer_lowerhalf_s g_esp32_timer3_lowerhalf = +{ + .ops = &g_esp32_timer_ops, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_timer_handler + * + * Description: + * Timer interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int esp32_timer_handler(int irq, void *context, void *arg) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)arg; + uint32_t next_interval_us = 0; + + /* Clear Interrupt Bits */ + + if (priv->callback(&next_interval_us, priv->arg)) + { + if (next_interval_us > 0) + { + /* Set a value to the alarm */ + + ESP32_TIM_SETALRVL(priv->tim, next_interval_us*ESP32_1USECOND); + } + } + else + { + esp32_timer_stop((struct timer_lowerhalf_s *)priv); + } + + ESP32_TIM_SETALRM(priv->tim, true); /* Re-enables the alarm */ + ESP32_TIM_CLEAR(priv->tim); /* Reset the counter */ + ESP32_TIM_ACKINT(priv->tim); /* Clear the Interrupt */ + return OK; +} + +/**************************************************************************** + * Name: esp32_timer_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32_timer_start(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)lower; + int ret = OK; + irqstate_t flags; + + DEBUGASSERT(priv); + + if (priv->started == true) + { + /* Return EBUSY to indicate that the timer was already running */ + + ret = -EBUSY; + goto errout; + } + + /* Change the prescaler divider with the timer enabled can lead to + * unpredictable results, so it is disabled before configuring + */ + + ret = ESP32_TIM_STOP(priv->tim); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER prescaler */ + + ret = ESP32_TIM_SETPRE(priv->tim, ESP32_TIMER_PRESCALER); + if (ret != OK) + { + goto errout; + } + + /* Configure TIMER mode */ + + ret = ESP32_TIM_SETMODE(priv->tim, ESP32_TIM_MODE_UP); + if (ret != OK) + { + goto errout; + } + + /* Clear TIMER counter value */ + + ret = ESP32_TIM_CLEAR(priv->tim); + if (ret != OK) + { + goto errout; + } + + /* Enable TIMER alarm */ + + ret = ESP32_TIM_SETALRM(priv->tim, true); + if (ret != OK) + { + goto errout; + } + + /* Clear Interrupt Bits Status */ + + ESP32_TIM_ACKINT(priv->tim); + + /* Configure callback */ + + if (priv->callback != NULL) + { + flags = enter_critical_section(); + + ESP32_TIM_SETISR(priv->tim, esp32_timer_handler, priv); + ESP32_TIM_ENABLEINT(priv->tim); + + leave_critical_section(flags); + } + + /* Finally, start the TIMER */ + + ret = ESP32_TIM_START(priv->tim); + if (ret != OK) + { + goto errout; + } + + priv->started = true; + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_timer_stop + * + * Description: + * Stop the timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32_timer_stop(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)lower; + int ret = OK; + + DEBUGASSERT(priv); + + if (priv->started == false) + { + /* Return ENODEV to indicate that the timer was not running */ + + ret = -ENODEV; + goto errout; + } + + ESP32_TIM_DISABLEINT(priv->tim); + ESP32_TIM_SETISR(priv->tim, NULL, NULL); + ESP32_TIM_STOP(priv->tim); + + priv->started = false; + priv->callback = NULL; + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_timer_getstatus + * + * Description: + * get timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * status - The location to return the status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32_timer_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s *status) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)lower; + int ret = OK; + uint64_t current_counter_value; + uint64_t alarm_value; + + DEBUGASSERT(priv); + DEBUGASSERT(status); + + /* Return the status bit */ + + status->flags = 0; + + if (priv->started == true) + { + /* TIMER is running */ + + status->flags |= TCFLAGS_ACTIVE; + } + + if (priv->callback != NULL) + { + /* TIMER has a user callback function to be called when + * expiration happens + */ + + status->flags |= TCFLAGS_HANDLER; + } + + /* Get the current counter value */ + + ret = ESP32_TIM_GETCTR(priv->tim, ¤t_counter_value); + if (ret != OK) + { + goto errout; + } + + /* Get the current configured timeout */ + + ret = ESP32_TIM_GETALRVL(priv->tim, &alarm_value); + if (ret != OK) + { + goto errout; + } + + status->timeout = (uint32_t)(alarm_value / ESP32_1USECOND); + status->timeleft = (uint32_t)((alarm_value - current_counter_value) + / ESP32_1USECOND); + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_timer_settimeout + * + * Description: + * Set a new timeout value (and reset the timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * timeout - The new timeout value in microseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32_timer_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)lower; + int ret = OK; + uint64_t timeout_64; + + DEBUGASSERT(priv); + + /* Verify if it is already running (set timeout must be called + * before start) + */ + + if (priv->started == true) + { + ret = -EPERM; + goto errout; + } + + /* Set the timeout */ + + timeout_64 = timeout*ESP32_1USECOND; + ret = ESP32_TIM_SETALRVL(priv->tim, timeout_64); + if (ret != OK) + { + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: esp32_timer_maxtimeout + * + * Description: + * Get the maximum timeout value + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * maxtimeout - A pointer to the variable that will store the max timeout. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32_timer_maxtimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t *max_timeout) +{ + DEBUGASSERT(priv); + + *max_timeout = ESP32_TIMER_MAX_USECOND; + + return OK; +} + +/**************************************************************************** + * Name: esp32_setcallback + * + * Description: + * Call this user provided timeout handler. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument that will be provided in the callback + * + * Returned Value: + * The previous timer expiration function pointer or NULL is there was + * no previous function pointer. + * + ****************************************************************************/ + +static void esp32_timer_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) +{ + FAR struct esp32_timer_lowerhalf_s *priv = + (FAR struct esp32_timer_lowerhalf_s *)lower; + irqstate_t flags; + + DEBUGASSERT(priv); + + flags = enter_critical_section(); + + /* Save the new callback */ + + priv->callback = callback; + priv->arg = arg; + + /* There is a user callback and the timer has already been started */ + + if (callback != NULL && priv->started == true) + { + ESP32_TIM_SETISR(priv->tim, esp32_timer_handler, priv); + ESP32_TIM_ENABLEINT(priv->tim); + } + else + { + ESP32_TIM_DISABLEINT(priv->tim); + ESP32_TIM_SETISR(priv->tim, NULL, NULL); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - the timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32_timer_initialize(FAR const char *devpath, uint8_t timer) +{ + struct esp32_timer_lowerhalf_s *lower = NULL; + FAR void *drvr = NULL; + int ret = OK; + + DEBUGASSERT(devpath); + + switch (timer) + { +#ifdef CONFIG_ESP32_TIMER0 + case 0: + { + lower = &g_esp32_timer0_lowerhalf; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER1 + case 1: + { + lower = &g_esp32_timer1_lowerhalf; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER2 + case 2: + { + lower = &g_esp32_timer2_lowerhalf; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER3 + case 3: + { + lower = &g_esp32_timer3_lowerhalf; + break; + } +#endif + +#ifdef CONFIG_ESP32_TIMER4 + case 4: + { + lower = &g_esp32_timer4_lowerhalf; + break; + } +#endif + + default: + { + ret = -ENODEV; + goto errout; + } + } + + /* Initialize the elements of lower half state structure */ + + lower->started = false; + lower->callback = NULL; + lower->tim = esp32_tim_init(timer); + + if (lower->tim == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Register the timer driver as /dev/timerX. The returned value from + * timer_register is a handle that could be used with timer_unregister(). + * REVISIT: The returned handle is discarded here. + */ + + drvr = timer_register(devpath, (FAR struct timer_lowerhalf_s *)lower); + if (drvr == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the timer driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + ret = -EEXIST; + goto errout; + } + +errout: + return ret; +} diff --git a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.h b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.h new file mode 100644 index 0000000000..57f12f59e4 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_tim_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_timer_initialize + ****************************************************************************/ + +int esp32_timer_initialize(FAR const char *devpath, uint8_t timer); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 6bee44c22d..cd3cb7a1d2 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -198,6 +198,7 @@ #define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 26 /* CPU is 80MHz */ +#define TB_CLK_FREQ APB_CLK_FREQ #define DR_REG_DPORT_BASE 0x3ff00000 #define DR_REG_UART_BASE 0x3ff40000 diff --git a/arch/xtensa/src/esp32/hardware/esp32_tim.h b/arch/xtensa/src/esp32/hardware/esp32_tim.h new file mode 100644 index 0000000000..e032252368 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_tim.h @@ -0,0 +1,889 @@ +/************************************************************************************ + * arch/xtensa/src/esp32/hardware/esp32_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ************************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_TIM_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_TIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "hardware/esp32_soc.h" + +/* Offsets relative to each timer instance memory base */ + +#define TIM_CONFIG_OFFSET 0x00 +#define TIM_LOAD_LO_OFFSET 0x0018 +#define TIM_LOAD_HI_OFFSET 0x001c +#define TIM_LOAD_OFFSET 0x0020 +#define TIMG_ALARM_LO_OFFSET 0x0010 +#define TIMG_ALARM_HI_OFFSET 0x0014 +#define TIM_UPDATE_OFFSET 0x000c +#define TIM_LO_OFFSET 0x0004 +#define TIM_HI_OFFSET 0x0008 +#define SHIFT_32 32 +#define TIM0_CLR_OFFSET 0x00a4 +#define TIM1_CLR_OFFSET 0x0080 +#define TIM0_INT_ST_OFFSET 0x00A0 +#define TIM1_INT_ST_OFFSET 0x007c +#define LOW_32_MASK 0xffffffff + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt + * registers + */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */ +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) + +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; + *description: When set timer 0 time-base counter is enabled + */ + +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; + * description: When set timer 0 time-base counter increment. When cleared timer + * 0 time-base counter decrement. + */ + +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; + * description: When set timer 0 auto-reload at alarming is enabled + */ + +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; + *description: Timer 0 clock (T0_clk) prescale value. + */ + +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 +/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; + * description: When set edge type interrupt will be generated during alarm + */ + +#define TIMG_T0_EDGE_INT_EN (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_V 0x1 +#define TIMG_T0_EDGE_INT_EN_S 12 +/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; + * description: When set level type interrupt will be generated during alarm + */ + +#define TIMG_T0_LEVEL_INT_EN (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_V 0x1 +#define TIMG_T0_LEVEL_INT_EN_S 11 +/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; + * description: When set alarm is enabled + */ + +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Register to store timer 0 time-base counter current + * value lower 32 bits. + */ + +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Register to store timer 0 time-base counter current value + * higher 32 bits. + */ + +#define TIMG_T0_HI 0xFFFFFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0xFFFFFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Write any value will trigger a timer 0 time-base counter value + * update (timer 0 current value will be stored in registers above) + */ + +#define TIMG_T0_UPDATE 0xFFFFFFFF +#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S)) +#define TIMG_T0_UPDATE_V 0xFFFFFFFF +#define TIMG_T0_UPDATE_S 0 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: Timer 0 time-base counter value lower 32 bits that + * will trigger the alarm + */ + +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: Timer 0 time-base counter value higher 32 bits that + * will trigger the alarm + */ + +#define TIMG_T0_ALARM_HI 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: Lower 32 bits of the value that will load into timer 0 + * time-base counter + */ + +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: higher 32 bits of the value that will load into timer 0 + * time-base counter + */ + +#define TIMG_T0_LOAD_HI 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Write any value will trigger timer 0 time-base counter reload + */ + +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) +/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; + *description: When set timer 1 time-base counter is enabled + */ + +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (BIT(31)) +#define TIMG_T1_EN_V 0x1 +#define TIMG_T1_EN_S 31 +/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; + * description: When set timer 1 time-base counter increment. When cleared timer + * 1 time-base counter decrement. + */ + +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (BIT(30)) +#define TIMG_T1_INCREASE_V 0x1 +#define TIMG_T1_INCREASE_S 30 +/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; + * description: When set timer 1 auto-reload at alarming is enabled + */ + +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (BIT(29)) +#define TIMG_T1_AUTORELOAD_V 0x1 +#define TIMG_T1_AUTORELOAD_S 29 +/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; + * description: Timer 1 clock (T1_clk) prescale value. + */ + +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) +#define TIMG_T1_DIVIDER_V 0xFFFF +#define TIMG_T1_DIVIDER_S 13 +/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; + * description: When set edge type interrupt will be generated during alarm + */ + +#define TIMG_T1_EDGE_INT_EN (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_V 0x1 +#define TIMG_T1_EDGE_INT_EN_S 12 +/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; + * description: When set level type interrupt will be generated during alarm + */ + +#define TIMG_T1_LEVEL_INT_EN (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_V 0x1 +#define TIMG_T1_LEVEL_INT_EN_S 11 +/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; + * description: When set alarm is enabled + */ + +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (BIT(10)) +#define TIMG_T1_ALARM_EN_V 0x1 +#define TIMG_T1_ALARM_EN_S 10 + +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) +/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Register to store timer 1 time-base counter current + * value lower 32 bits. + */ + +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) +/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Register to store timer 1 time-base counter current value + * higher 32 bits. + */ + +#define TIMG_T1_HI 0xFFFFFFFF +#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) +#define TIMG_T1_HI_V 0xFFFFFFFF +#define TIMG_T1_HI_S 0 + +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) +/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Write any value will trigger a timer 1 time-base counter value + * update (timer 1 current value will be stored in registers above) + */ + +#define TIMG_T1_UPDATE 0xFFFFFFFF +#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S)) +#define TIMG_T1_UPDATE_V 0xFFFFFFFF +#define TIMG_T1_UPDATE_S 0 + +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) +/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + *description: Timer 1 time-base counter value lower 32 bits that will + *trigger the alarm + */ + +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) +/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: Timer 1 time-base counter value higher 32 bits that will + * trigger the alarm + */ + +#define TIMG_T1_ALARM_HI 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) +#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_S 0 + +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) +/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: Lower 32 bits of the value that will load into + * timer 1 time-base counter + */ + +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) +/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: higher 32 bits of the value that will load into timer 1 + * time-base counter + */ + +#define TIMG_T1_LOAD_HI 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) +#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_S 0 + +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) +/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Write any value will trigger timer 1 time-base counter reload + */ + +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; + * description: When set SWDT is enabled + */ + +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; + * description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: + * reset system + */ + +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; + * description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: + * reset system + */ + +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; + * description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: + * reset system + */ + +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; + * description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: + * reset system + */ + +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 +/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; + * description: When set edge type interrupt generation is enabled + */ + +#define TIMG_WDT_EDGE_INT_EN (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_M (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_V 0x1 +#define TIMG_WDT_EDGE_INT_EN_S 22 +/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; + * description: When set level type interrupt generation is enabled + */ + +#define TIMG_WDT_LEVEL_INT_EN (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_V 0x1 +#define TIMG_WDT_LEVEL_INT_EN_S 21 +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; + * description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns + * 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us + */ + +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; + * description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns + * 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us + */ + +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; + * description: When set flash boot protection is enabled + */ + +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; + * description: SWDT clock prescale value. Period = 12.5ns * value stored in + * this register + */ + +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; + *description: Stage 0 timeout value in SWDT clock cycles + */ + +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; + * description: Stage 1 timeout value in SWDT clock cycles + */ + +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; + *description: Stage 2 timeout value in SWDT clock cycles + */ + +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; + * description: Stage 3 timeout value in SWDT clock cycles + */ + +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: Write any value will feed SWDT + */ + +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; + *description: If change its value from default then write + * protection is on. + */ + +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; + * description: + */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; + * description: + */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; + * description: + */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 + +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; + * description: + */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; + * description: + */ + +#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) +/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; + * description: + */ +#define TIMG_LACT_EN (BIT(31)) +#define TIMG_LACT_EN_M (BIT(31)) +#define TIMG_LACT_EN_V 0x1 +#define TIMG_LACT_EN_S 31 +/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; + * description: + */ + +#define TIMG_LACT_INCREASE (BIT(30)) +#define TIMG_LACT_INCREASE_M (BIT(30)) +#define TIMG_LACT_INCREASE_V 0x1 +#define TIMG_LACT_INCREASE_S 30 +/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; + * description: + */ + +#define TIMG_LACT_AUTORELOAD (BIT(29)) +#define TIMG_LACT_AUTORELOAD_M (BIT(29)) +#define TIMG_LACT_AUTORELOAD_V 0x1 +#define TIMG_LACT_AUTORELOAD_S 29 +/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; + *description: + */ + +#define TIMG_LACT_DIVIDER 0x0000FFFF +#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) +#define TIMG_LACT_DIVIDER_V 0xFFFF +#define TIMG_LACT_DIVIDER_S 13 +/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_EDGE_INT_EN (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_M (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_V 0x1 +#define TIMG_LACT_EDGE_INT_EN_S 12 +/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_LEVEL_INT_EN (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_V 0x1 +#define TIMG_LACT_LEVEL_INT_EN_S 11 +/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_ALARM_EN (BIT(10)) +#define TIMG_LACT_ALARM_EN_M (BIT(10)) +#define TIMG_LACT_ALARM_EN_V 0x1 +#define TIMG_LACT_ALARM_EN_S 10 +/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; + * description: + */ + +#define TIMG_LACT_LAC_EN (BIT(9)) +#define TIMG_LACT_LAC_EN_M (BIT(9)) +#define TIMG_LACT_LAC_EN_V 0x1 +#define TIMG_LACT_LAC_EN_S 9 +/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; + * description: + */ + +#define TIMG_LACT_CPST_EN (BIT(8)) +#define TIMG_LACT_CPST_EN_M (BIT(8)) +#define TIMG_LACT_CPST_EN_V 0x1 +#define TIMG_LACT_CPST_EN_S 8 +/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_RTC_ONLY (BIT(7)) +#define TIMG_LACT_RTC_ONLY_M (BIT(7)) +#define TIMG_LACT_RTC_ONLY_V 0x1 +#define TIMG_LACT_RTC_ONLY_S 7 + +#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) +/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; + * description: + */ + +#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) +#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_S 6 + +#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) +/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_LO 0xFFFFFFFF +#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) +#define TIMG_LACT_LO_V 0xFFFFFFFF +#define TIMG_LACT_LO_S 0 + +#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) +/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_HI 0xFFFFFFFF +#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) +#define TIMG_LACT_HI_V 0xFFFFFFFF +#define TIMG_LACT_HI_S 0 + +#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) +/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_UPDATE 0xFFFFFFFF +#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) +#define TIMG_LACT_UPDATE_V 0xFFFFFFFF +#define TIMG_LACT_UPDATE_S 0 + +#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) +/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_ALARM_LO 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) +#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_S 0 + +#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) +/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_ALARM_HI 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) +#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_S 0 + +#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) +/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_LOAD_LO 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) +#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_S 0 + +#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) +/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_LOAD_HI 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) +#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_S 0 + +#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) +/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; + * description: + */ + +#define TIMG_LACT_LOAD 0xFFFFFFFF +#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) +#define TIMG_LACT_LOAD_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) +/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_INT_ENA (BIT(3)) +#define TIMG_LACT_INT_ENA_M (BIT(3)) +#define TIMG_LACT_INT_ENA_V 0x1 +#define TIMG_LACT_INT_ENA_S 3 +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; + * description: Interrupt when an interrupt stage timeout + */ + +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (BIT(2)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 2 +/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; + *description: interrupt when timer1 alarm + */ + +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (BIT(1)) +#define TIMG_T1_INT_ENA_V 0x1 +#define TIMG_T1_INT_ENA_S 1 +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; + *description: interrupt when timer0 alarm + */ + +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) +/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; + *description: + */ + +#define TIMG_LACT_INT_RAW (BIT(3)) +#define TIMG_LACT_INT_RAW_M (BIT(3)) +#define TIMG_LACT_INT_RAW_V 0x1 +#define TIMG_LACT_INT_RAW_S 3 +/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; + *description: Interrupt when an interrupt stage timeout + */ + +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (BIT(2)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 2 +/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; + *description: interrupt when timer1 alarm + */ + +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (BIT(1)) +#define TIMG_T1_INT_RAW_V 0x1 +#define TIMG_T1_INT_RAW_S 1 +/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; + * description: interrupt when timer0 alarm + */ + +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) +/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; + *description: + */ + +#define TIMG_LACT_INT_ST (BIT(3)) +#define TIMG_LACT_INT_ST_M (BIT(3)) +#define TIMG_LACT_INT_ST_V 0x1 +#define TIMG_LACT_INT_ST_S 3 +/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; + * description: Interrupt when an interrupt stage timeout + */ + +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (BIT(2)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 2 +/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; + * description: interrupt when timer1 alarm + */ + +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (BIT(1)) +#define TIMG_T1_INT_ST_V 0x1 +#define TIMG_T1_INT_ST_S 1 +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; + * description: interrupt when timer0 alarm + */ + +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) +/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; + * description: + */ + +#define TIMG_LACT_INT_CLR (BIT(3)) +#define TIMG_LACT_INT_CLR_M (BIT(3)) +#define TIMG_LACT_INT_CLR_V 0x1 +#define TIMG_LACT_INT_CLR_S 3 +/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; + *description: Interrupt when an interrupt stage timeout + */ + +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (BIT(2)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 2 +/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; + *description: interrupt when timer1 alarm + */ + +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (BIT(1)) +#define TIMG_T1_INT_CLR_V 0x1 +#define TIMG_T1_INT_CLR_S 1 +/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; + * description: interrupt when timer0 alarm + */ + +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; + * description: Version of this regfile + */ + +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; + *description: Force clock enable for this regfile + */ + +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_TIM_H */ diff --git a/boards/xtensa/esp32/esp32-core/configs/timer/defconfig b/boards/xtensa/esp32/esp32-core/configs/timer/defconfig new file mode 100644 index 0000000000..9c63edecd5 --- /dev/null +++ b/boards/xtensa/esp32/esp32-core/configs/timer/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-core" +CONFIG_ARCH_BOARD_ESP32CORE=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_TIMER0=y +CONFIG_ESP32_TIMER1=y +CONFIG_ESP32_TIMER2=y +CONFIG_ESP32_TIMER3=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_TIMER_ARCH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32/esp32-core/src/Makefile b/boards/xtensa/esp32/esp32-core/src/Makefile index 6b08aec80c..6c51a74c1c 100644 --- a/boards/xtensa/esp32/esp32-core/src/Makefile +++ b/boards/xtensa/esp32/esp32-core/src/Makefile @@ -60,6 +60,12 @@ ifeq ($(CONFIG_ESP32_SPIFLASH),y) CSRCS += esp32_spiflash.c endif +ifeq ($(CONFIG_TIMER),y) +ifeq ($(CONFIG_ESP32_TIMER),y) +CSRCS += esp32_timer.c +endif +endif + SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template.ld SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32_out.ld diff --git a/boards/xtensa/esp32/esp32-core/src/esp32-core.h b/boards/xtensa/esp32/esp32-core/src/esp32-core.h index 5f0a4c1389..b7b678f962 100644 --- a/boards/xtensa/esp32/esp32-core/src/esp32-core.h +++ b/boards/xtensa/esp32/esp32-core/src/esp32-core.h @@ -95,6 +95,17 @@ int esp32_mmcsd_initialize(int minor); ****************************************************************************/ int esp32_spiflash_init(void); +/**************************************************************************** + * Name: esp32_timer_driver_setup + * + * Description: + * Initialize TIMER driver. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int esp32_timer_driver_setup(FAR const char *devpath, int timer); +#endif #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_XTENSA_ESP32_ESP32_CORE_SRC_ESP32_CORE_H */ diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c index 57aa5d7631..567d382956 100644 --- a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c @@ -42,6 +42,11 @@ #include #include #include +#include + +#ifdef CONFIG_TIMER +# include +#endif #include "esp32-core.h" @@ -49,6 +54,22 @@ * Pre-processor Definitions ****************************************************************************/ +#ifdef CONFIG_ESP32_TIMER0 +#define ESP32_TIMER0 (0) +#endif + +#ifdef CONFIG_ESP32_TIMER1 +#define ESP32_TIMER1 (1) +#endif + +#ifdef CONFIG_ESP32_TIMER2 +#define ESP32_TIMER2 (2) +#endif + +#ifdef CONFIG_ESP32_TIMER3 +#define ESP32_TIMER3 (3) +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -94,6 +115,49 @@ int esp32_bringup(void) ret = esp32_spiflash_init(); #endif +#ifdef CONFIG_TIMER + /* Configure TIMER driver */ +#ifdef CONFIG_ESP32_TIMER0 + ret = esp32_timer_driver_setup("/dev/timer0", ESP32_TIMER0); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ESP32_TIMER1 + ret = esp32_timer_driver_setup("/dev/timer1", ESP32_TIMER1); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ESP32_TIMER2 + ret = esp32_timer_driver_setup("/dev/timer2", ESP32_TIMER2); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ESP32_TIMER3 + ret = esp32_timer_driver_setup("/dev/timer3", ESP32_TIMER3); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_timer.c b/boards/xtensa/esp32/esp32-core/src/esp32_timer.c new file mode 100644 index 0000000000..8918740e3d --- /dev/null +++ b/boards/xtensa/esp32/esp32-core/src/esp32_timer.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * boards/xtensa/esp32/esp32-core/src/esp32_timer.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "esp32_tim_lowerhalf.h" + +#include "esp32-core.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timerX + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32_timer_driver_setup(FAR const char *devpath, int timer) +{ + return esp32_timer_initialize(devpath, timer); +} diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index b1c087156e..138973fd39 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -235,7 +235,7 @@ extern "C" * initialization. * * Input Parameters: - * dev path - The full path to the driver to be registers in the NuttX + * dev path - The full path to the driver to be registered in the NuttX * pseudo-filesystem. The recommended convention is to name all timer * drivers as "/dev/timer0", "/dev/timer1", etc. where the driver * path differs only in the "minor" number at the end of the device name.