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Merged nuttx/arch into master

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This commit is contained in:
Pierre-noel Bouteville 2015-09-03 12:06:38 +02:00
commit 0fb41dd4e7
146 changed files with 12747 additions and 824 deletions
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1
arch/arm/Kconfig
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@ -227,6 +227,7 @@ config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
---help---
MoxART family

2
arch/arm/include/lpc43xx/chip.h
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@ -566,7 +566,7 @@
#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN
#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT
#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR
#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_STEP
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most

5
arch/arm/include/moxart/irq.h
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@ -81,7 +81,8 @@ extern "C"
#define IRQ_SYSTIMER 19
#define NR_IRQS 32
#define VIRQ_START 32
#define NR_IRQS (VIRQ_START+2)
#endif /* __ARCH_ARM_INCLUDE_MOXART_IRQ_H */

53
arch/arm/include/sama5/chip.h
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@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/include/sama5/chip.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -45,6 +45,49 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* SAMA5D2 Family
*
* SAMA5D21 SAMA5D22 SAMA5D23 SAMA5D24 SAMA5D26 SAMA5D27 SAMA5D28
* ------------------------- --------- --------- --------- --------- --------- --------- ---------
* Pin Count 196 196 196 256 289 289 289
* Max. Operating Frequency 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz
* CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5
* Max I/O Pins 72 72 72 105 128 128 128
* USB Transceiver 1 1 1 1 1 1 1
* USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed
* USB Interface 2 2 2 3 3 3 3
* SPI 6 6 6 7 7 7 7
* QuadSPI 2 2 2 2 2 2 2
* TWIHS (I2C) 6 6 6 7 7 7 7
* UART 9 9 9 10 10 10 10
* CAN - 1 1 - - 2 2
* SDIO/SD/MMC 1 1 1 2 2 2 2
* I2SC 2 2 2 2 2 2 2
* SSC 2 2 2 2 2 2 2
* Class D 1 1 1 2 2 2 2
* PDMIC 1 1 1 2 2 2 2
* Camera Interface 1 1 1 1 1 1 1
* ADC Inputs 5 5 5 12 12 12 12
* AESB - 1 1 1 - 1 1
* SRAM (Kbytes) 128 128 128 128 128 128 128
* DDR Bus 16-bit 16-bit 16-bit 16/32-bit 16/32-bit 16/32-bit 16/32-bit
* Timers 6 6 6 6 6 6 6
* Tamper pins 6 6 6 2 8 8 8
* Packages BGA196 BGA196 BGA196 BGA256 BGA289 BGA289 BGA289
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D21) || defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || defined(CONFIG_ARCH_CHIP_ATSAMA5D23) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D24) || defined(CONFIG_ARCH_CHIP_ATSAMA5D26) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D27) || defined(CONFIG_ARCH_CHIP_ATSAMA5D28)
# define ATSAMA5D2 1 /* SAMA5D2 family */
# undef ATSAMA5D3 /* Not SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) XDMA controllers */
# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
/* SAMA5D3 Family
*
* ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 ATSAMA5D36
@ -91,7 +134,8 @@
* Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@ -99,6 +143,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@ -106,6 +151,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@ -113,6 +159,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@ -120,6 +167,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D36)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@ -141,6 +189,7 @@
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D43) || defined(CONFIG_ARCH_CHIP_ATSAMA5D44)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# undef ATSAMA5D3 /* Not SAMA5D3 family */
# define ATSAMA5D4 1 /* SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */

4
arch/arm/include/sama5/irq.h
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@ -53,7 +53,9 @@
/* Chip-Specific External interrupts */
#if defined(ATSAMA5D3)
#if defined(ATSAMA5D2)
# include <arch/sama5/sama5d2_irq.h>
#elif defined(ATSAMA5D3)
# include <arch/sama5/sama5d3_irq.h>
#elif defined(ATSAMA5D4)
# include <arch/sama5/sama5d4_irq.h>

424
arch/arm/include/sama5/sama5d2_irq.h Normal file
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@ -0,0 +1,424 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d2_irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAMA5D3 Peripheral Identifiers */
#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
/* 2 Reserved */
#define SAM_PID_ARM (2) /* Performance Monitor Unit */
#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
#define SAM_PID_EMAC0 (5) /* Ethernet MAC 0 */
#define SAM_PID_XDMAC0 (6) /* DMA Controller 0 */
#define SAM_PID_XDMAC1 (7) /* DMA Controller 1 */
#define SAM_PID_ICM (8) /* Integrity Check Monitor */
#define SAM_PID_AES (9) /* Advanced Encryption Standard */
#define SAM_PID_AESB (10) /* AES bridge */
#define SAM_PID_TDES (11) /* Triple Data Encryption Standard */
#define SAM_PID_SHA (12) /* Secure Hash Algorithm */
#define SAM_PID_MPDDRC (13) /* MPDDR controller */
#define SAM_PID_MATRIX1 (14) /* H32MX, 32-bit AHB Matrix */
#define SAM_PID_MATRIX0 (15) /* H64MX, 64-bit AHB Matrix */
#define SAM_PID_SECUMOD (16) /* Secure Module */
#define SAM_PID_HSMC (17) /* Multi-bit ECC Interrupt */
#define SAM_PID_PIOA (18) /* Parallel I/O Controller A */
#define SAM_PID_FLEXCOM0 (19) /* FLEXCOM 0 */
#define SAM_PID_FLEXCOM1 (20) /* FLEXCOM 1 */
#define SAM_PID_FLEXCOM2 (21) /* FLEXCOM 2 */
#define SAM_PID_FLEXCOM3 (22) /* FLEXCOM 3 */
#define SAM_PID_FLEXCOM4 (23) /* FLEXCOM 4 */
#define SAM_PID_UART0 (24) /* UART 0 */
#define SAM_PID_UART1 (25) /* UART 1 */
#define SAM_PID_UART2 (26) /* UART 2 */
#define SAM_PID_UART3 (27) /* UART 3 */
#define SAM_PID_UART4 (28) /* UART 4 */
#define SAM_PID_TWI0 (29) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (30) /* Two-Wire Interface 1 */
#define SAM_PID_SDMMC0 (31) /* Secure Data Memory Card Controller 0 */
#define SAM_PID_SDMMC1 (32) /* Secure Data Memory Card Controller 1 */
#define SAM_PID_SPI0 (33) /* Serial Peripheral Interface 0 */
#define SAM_PID_SPI1 (34) /* Serial Peripheral Interface 1 */
#define SAM_PID_TC0 (35) /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_PID_TC1 (36) /* Timer Counter 1 (ch. 3, 4, 5) */
/* 37 Reserved */
#define SAM_PID_PWM (38) /* Pulse Width Modulation Controller */
/* 39 Reserved */
#define SAM_PID_ADC (40) /* Touch Screen ADC Controller */
#define SAM_PID_UHPHS (41) /* USB Host High Speed */
#define SAM_PID_UDPHS (42) /* USB Device High Speed */
#define SAM_PID_SSC0 (43) /* Synchronous Serial Controller 0 */
#define SAM_PID_SSC1 (44) /* Synchronous Serial Controller 1 */
#define SAM_PID_LCDC (45) /* LCD Controller */
#define SAM_PID_ISC (46) /* Image Sensor Controller */
#define SAM_PID_TRNG (47) /* True Random Number Generator */
#define SAM_PID_PDMIC (48) /* Pulse Density Modulation Interface Controller */
#define SAM_PID_IRQID (49) /* IRQ Interrupt ID */
#define SAM_PID_SFC (50) /* Fuse Controller */
#define SAM_PID_SECURAM (51) /* Secured RAM */
#define SAM_PID_QSPI0 (52) /* QuadSPI 0 */
#define SAM_PID_QSPI1 (53) /* QuadSPI 1 */
#define SAM_PID_I2SC0 (54) /* Inter-IC Sound Controller 0 */
#define SAM_PID_I2SC1 (55) /* Inter-IC Sound Controller 1 */
#define SAM_PID_MCAN00 (56) /* MCAN controller 0, Interrupt 0 */
#define SAM_PID_MCAN10 (57) /* MCAN controller 1, Interrupt 0 */
/* 58 Reserved */
#define SAM_PID_CLASSD (59) /* Audio Class D Amplifier */
#define SAM_PID_SFR (60) /* Special Function Register */
#define SAM_PID_SAIC (61) /* Secured Advanced Interrupt Controller */
#define SAM_PID_AIC (62) /* Advanced Interrupt Controller */
#define SAM_PID_L2CC (63) /* L2 Cache Controller */
#define SAM_PID_MCAN01 (64) /* MCAN controller 0, Interrupt 1 */
#define SAM_PID_MCAN11 (65) /* MCAN controller 1, Interrupt 1 */
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
#define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */
#define SAM_PID_PIOB (68) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (69) /* Parallel I/O Controller C */
#define SAM_PID_PIOD (70) /* Parallel I/O Controller D */
#define SAM_PID_SDMMC0T (71) /* Secure Data Memory Card Controller 0 */
#define SAM_PID_SDMMC1T (72) /* Secure Data Memory Card Controller 1 */
/* 73 Reserved */
#define SAM_PID_SYS (74) /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_PID_ACC (75) /* Analog Comparator */
#define SAM_PID_RXLP (76) /* UART Low-Power */
#define SAM_PID_SFRBU (77) /* Special Function Register BackUp */
#define SAM_PID_CHIPID (78) /* Chip ID */
#define SAM_NPIDS (79)
/* External interrupts vectors numbers (same as peripheral ID) */
#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */
#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */
#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */
#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */
#define SAM_IRQ_EMAC0 SAM_PID_EMAC0 /* Ethernet MAC 0 */
#define SAM_IRQ_XDMAC0 SAM_PID_XDMAC0 /* DMA Controller 0 */
#define SAM_IRQ_XDMAC1 SAM_PID_XDMAC1 /* DMA Controller 1 */
#define SAM_IRQ_ICM SAM_PID_ICM /* Integrity Check Monitor */
#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */
#define SAM_IRQ_AESB SAM_PID_AESB /* AES bridge */
#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */
#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */
#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */
#define SAM_IRQ_MATRIX1 SAM_PID_MATRIX1 /* H32MX, 32-bit AHB Matrix */
#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
#define SAM_IRQ_SECUMOD SAM_PID_SECUMOD /* Secure Module */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
#define SAM_IRQ_FLEXCOM0 SAM_PID_FLEXCOM0 /* FLEXCOM 0 */
#define SAM_IRQ_FLEXCOM1 SAM_PID_FLEXCOM1 /* FLEXCOM 1 */
#define SAM_IRQ_FLEXCOM2 SAM_PID_FLEXCOM2 /* FLEXCOM 2 */
#define SAM_IRQ_FLEXCOM3 SAM_PID_FLEXCOM3 /* FLEXCOM 3 */
#define SAM_IRQ_FLEXCOM4 SAM_PID_FLEXCOM4 /* FLEXCOM 4 */
#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */
#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */
#define SAM_IRQ_UART2 SAM_PID_UART2 /* UART 2 */
#define SAM_IRQ_UART3 SAM_PID_UART3 /* UART 3 */
#define SAM_IRQ_UART4 SAM_PID_UART4 /* UART 4 */
#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */
#define SAM_IRQ_SDMMC0 SAM_PID_SDMMC0 /* Secure Data Memory Card Controller 0 */
#define SAM_IRQ_SDMMC1 SAM_PID_SDMMC1 /* Secure Data Memory Card Controller 1 */
#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */
#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */
#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */
#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
#define SAM_IRQ_ISC SAM_PID_ISC /* Image Sensor Controller */
#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */
#define SAM_IRQ_PDMIC SAM_PID_PDMIC /* Pulse Density Modulation Interface Controller */
#define SAM_IRQ_IRQID SAM_PID_IRQID /* IRQ Interrupt ID */
#define SAM_IRQ_SFC SAM_PID_SFC /* Fuse Controller */
#define SAM_IRQ_SECURAM SAM_PID_SECURAM /* Secured RAM */
#define SAM_IRQ_QSPI0 SAM_PID_QSPI0 /* QuadSPI 0 */
#define SAM_IRQ_QSPI1 SAM_PID_QSPI1 /* QuadSPI 1 */
#define SAM_IRQ_I2SC0 SAM_PID_I2SC0 /* Inter-IC Sound Controller 0 */
#define SAM_IRQ_I2SC1 SAM_PID_I2SC1 /* Inter-IC Sound Controller 1 */
#define SAM_IRQ_MCAN00 SAM_PID_MCAN00 /* MCAN controller 0, Interrupt 0 */
#define SAM_IRQ_MCAN10 SAM_PID_MCAN10 /* MCAN controller 1, Interrupt 0 */
#define SAM_IRQ_CLASSD SAM_PID_CLASSD /* Audio Class D Amplifier */
/* Special Function Register (no interrupt) */
/* Secured Advanced Interrupt Controller (no interrupt) */
/* Advanced Interrupt Controller (no interrupt) */
#define SAM_IRQ_L2CC SAM_PID_L2CC /* L2 Cache Controller */
#define SAM_IRQ_MCAN01 SAM_PID_MCAN01 /* MCAN controller 0, Interrupt 1 */
#define SAM_IRQ_MCAN11 SAM_PID_MCAN11 /* MCAN controller 1, Interrupt 1 */
#define SAM_IRQ_EMACQ1 SAM_PID_EMACQ1 /* EMAC Queue 1 Interrupt */
#define SAM_IRQ_EMACQ2 SAM_PID_EMACQ2 /* EMAC Queue 2 Interrupt */
#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */
#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */
#define SAM_IRQ_SDMMC0T SAM_PID_SDMMC0T /* Secure Data Memory Card Controller 0 */
#define SAM_IRQ_SDMMC1T SAM_PID_SDMMC1T /* Secure Data Memory Card Controller 1 */
#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_IRQ_ACC SAM_PID_ACC /* Analog Comparator */
#define SAM_IRQ_RXLP SAM_PID_RXLP /* UART Low-Power */
/* Special Function Register BackUp (no interrupt) */
/* Chip ID (no interrupt) */
#define SAM_IRQ_NINT (SAM_PID_RXLP + 1)
/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
#ifdef CONFIG_SAMA5_PIOA_IRQ
# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT)
# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */
# define SAM_NPIOAIRQS 32
#else
# define SAM_NPIOAIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */
# define SAM_NPIOBIRQS 32
#else
# define SAM_NPIOBIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */
# define SAM_NPIOCIRQS 32
#else
# define SAM_NPIOCIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \
SAM_NPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */
# define SAM_NPIODIRQS 32
#else
# define SAM_NPIODIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (SAM_IRQ_NINT + \
SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \
SAM_NPIODIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H */

8
arch/arm/include/sama5/sama5d4_irq.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d4x_irq.h
* arch/arm/include/sama5/sama5d4_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -37,8 +37,8 @@
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H
/****************************************************************************************
* Included Files
@ -436,4 +436,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H */

4
arch/arm/include/samv7/chip.h
View File

@ -86,7 +86,7 @@
# define SAMV7_NTCCHIO 36 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
@ -142,7 +142,7 @@
# define SAMV7_NTCCHIO 9 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */

120
arch/arm/include/stm32/chip.h
View File

@ -1212,6 +1212,86 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 25 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@ -1292,6 +1372,46 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 4 /* (4) SPI1-4 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 3 /* (2) I2C1-3 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-F */
# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */

2
arch/arm/src/armv7-a/arm_copyarmstate.c
View File

@ -76,7 +76,7 @@ void up_copyarmstate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the Cortex-M3 model, the state is copied from the stack to the TCB,
/* In the Cortex-M model, the state is copied from the stack to the TCB,
* but only a reference is passed to get the state from the TCB. So the
* following check avoids copying the TCB save area onto itself:
*/

17
arch/arm/src/armv7-m/up_ramvec_initialize.c
View File

@ -56,6 +56,21 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Alignment ****************************************************************/
/* Per the ARMv7M Architecture reference manual, the NVIC vector table
* requires 7-bit address alignment (i.e, bits 0-6 of the address of the
* vector table must be zero). In this case alignment to a 128 byte address
* boundary is sufficient.
*
* Some parts, such as the LPC17xx family, require alignment to a 256 byte
* address boundary. Any other unusual alignment requirements for the vector
* can be specified for a given architecture be redefining
* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
* appropriate mask.
*/
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the interrupt
* config. NOTE: that only lldbg types are used so that the output is
@ -91,7 +106,7 @@
*/
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
/****************************************************************************
* Private Variables

2
arch/arm/src/calypso/calypso_serial.c
View File

@ -377,7 +377,7 @@ static inline void up_setrate(struct up_dev_s *priv, unsigned int rate)
break;
}
#if UART_DIV_BIT_RATE_OFFS
#ifdef UART_DIV_BIT_RATE_OFFS
up_serialout(priv, UART_DIV_BIT_RATE_OFFS, div_bit_rate);
#else
up_serialout(priv, UART_DIV_LOW_OFFS, div_bit_rate);

7
arch/arm/src/common/up_initialize.c
View File

@ -44,6 +44,7 @@
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/fs/fs.h>
#include <nuttx/net/loopback.h>
#include <nuttx/syslog/ramlog.h>
#include <nuttx/syslog/syslog_console.h>
#include <nuttx/crypto/crypto.h>
@ -254,6 +255,12 @@ void up_initialize(void)
up_netinitialize();
#endif
#ifdef CONFIG_NETDEV_LOOPBACK
/* Initialize the local loopback device */
(void)localhost_initialize();
#endif
/* Initialize USB -- device and/or host */
up_usbinitialize();

5
arch/arm/src/common/up_internal.h
View File

@ -124,10 +124,11 @@
/* If the floating point unit is present and enabled, then save the
* floating point registers as well as normal ARM registers. This only
* applies if "lazy" floating point register save/restore is used
* (i.e., not CONFIG_ARMV7M_CMNVECTOR).
* (i.e., not CONFIG_ARMV7M_CMNVECTOR=y with CONFIG_ARMV7M_LAZYFPU=n).
*/
# if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_ARMV7M_CMNVECTOR)
# if defined(CONFIG_ARCH_FPU) && (!defined(CONFIG_ARMV7M_CMNVECTOR) || \
defined(CONFIG_ARMV7M_LAZYFPU))
# define up_savestate(regs) up_copyarmstate(regs, (uint32_t*)current_regs)
# else
# define up_savestate(regs) up_copyfullstate(regs, (uint32_t*)current_regs)

2
arch/arm/src/efm32/Make.defs
View File

@ -87,6 +87,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif

21
arch/arm/src/efm32/efm32_irq.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_irq.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -79,8 +79,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@ -363,6 +373,15 @@ void up_irqinitialize(void)
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.

4
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -683,7 +683,7 @@ static const struct usbdev_ops_s g_devops =
.pullup = efm32_pullup,
};
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@ -725,7 +725,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/

2
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -1171,7 +1171,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do

8
arch/arm/src/kinetis/kinetis_enet.c
View File

@ -191,14 +191,14 @@ struct kinetis_driver_s
#endif
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
uint8_t desc[NENET_NBUFFERS * sizeof(struct enet_desc_s) + 16];
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
@ -1338,7 +1338,7 @@ static inline void kinetis_initphy(struct kinetis_driver_s *priv)
* configuration and the auto negotiation results.
*/
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
rcr = ENET_RCR_MII_MODE | ENET_RCR_CRCFWD |
CONFIG_NET_ETH_MTU << ENET_RCR_MAX_FL_SHIFT;
#else
@ -1527,7 +1527,7 @@ int kinetis_netinitialize(int intf)
/* Configure all ENET/MII pins */
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
kinetis_pinconfig(PIN_MII0_MDIO);
kinetis_pinconfig(PIN_MII0_MDC);
kinetis_pinconfig(PIN_MII0_RXDV);

23
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/kinetis_irq.c
*
* Copyright (C) 2011, 2013-14 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -75,8 +75,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@ -341,11 +351,20 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#endif

10
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -65,7 +65,7 @@
#include "kinetis_sim.h"
#include "kinetis_sdhc.h"
#if CONFIG_KINETIS_SDHC
#ifdef CONFIG_KINETIS_SDHC
/****************************************************************************
* Pre-processor Definitions
@ -102,7 +102,7 @@
* and divider values.
*/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
# ifndef CONFIG_KINETIS_IDMODE_FREQ
# define CONFIG_KINETIS_IDMODE_FREQ 400000 /* 400 KHz, ID mode */
# endif
@ -287,7 +287,7 @@ static int kinetis_lock(FAR struct sdio_dev_s *dev, bool lock);
static void kinetis_reset(FAR struct sdio_dev_s *dev);
static uint8_t kinetis_status(FAR struct sdio_dev_s *dev);
static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool enable);
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency);
#endif
static void kinetis_clock(FAR struct sdio_dev_s *dev,
@ -1387,7 +1387,7 @@ static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool wide)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
{
uint32_t sdclkfs;
@ -1523,7 +1523,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
uint32_t frequency;

2
arch/arm/src/lpc17xx/Make.defs
View File

@ -100,6 +100,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif

4
arch/arm/src/lpc17xx/lpc176x_rtc.c
View File

@ -250,7 +250,7 @@ static int rtc_resume(void)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
#warning "Missing logic"
@ -285,7 +285,7 @@ int up_rtcinitialize(void)
/* Attach the RTC interrupt handler */
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt);
if (ret == OK)
{

25
arch/arm/src/lpc17xx/lpc17_allocateheap.c
View File

@ -155,15 +155,23 @@
/* Sanity checking */
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) && !defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 0
#elif defined(CONFIG_LPC17_EXTDRAMHEAP) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 2
#else
# define LPC17_EXT_MM_REGIONS 1
#endif
#ifdef LPC17_AHB_HEAPBASE
# if CONFIG_MM_REGIONS < 2
# if CONFIG_MM_REGIONS < 2 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS < 2: Available AHB SRAM Bank(s) not included in HEAP"
# endif
# if CONFIG_MM_REGIONS > 2
# if (CONFIG_MM_REGIONS > 2 + LPC17_EXT_MM_REGIONS)
# warning "CONFIG_MM_REGIONS > 2: Are additional regions handled by application?"
# endif
#else
# if CONFIG_MM_REGIONS > 1
# if CONFIG_MM_REGIONS > 1 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS > 1: This configuration has no available AHB SRAM Bank0/1"
# warning "CONFIG_MM_REGIONS > 1: Are additional regions handled by application?"
# endif
@ -340,5 +348,16 @@ void up_addregion(void)
kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
#if CONFIG_MM_REGIONS >= 3
#if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP)
kmm_addregion((FAR void*)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE);
#endif
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4)
#if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
kmm_addregion((FAR void*)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE);
#endif
#endif
#endif
}
#endif

14
arch/arm/src/lpc17xx/lpc17_can.c
View File

@ -750,7 +750,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
irqstate_t flags;
int ret = OK;
canvdbg("CAN%d ID: %d DLC: %d\n", priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
canvdbg("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
if (msg->cm_hdr.ch_rtr)
{
@ -971,12 +972,15 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Construct the CAN header */
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_error = 0;
#ifdef CONFIG_CAN_EXTID
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
#else
hdr.ch_unused = 0;
if ((rfs & CAN_RFS_FF) != 0)
{
canlldbg("ERROR: Received message with extended identifier. Dropped\n");

2
arch/arm/src/lpc17xx/lpc17_ethernet.c
View File

@ -1564,7 +1564,7 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv)
if (considx != prodidx)
{
#if CONFIG_NET_NOINTS
#ifdef CONFIG_NET_NOINTS
work_queue(HPWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work,
priv, 0);

2
arch/arm/src/lpc17xx/lpc17_gpdma.h
View File

@ -60,7 +60,7 @@ typedef FAR void *DMA_HANDLE;
* function is called at the completion of the DMA transfer. 'arg' is the
* same 'arg' value that was provided when lpc17_dmastart() was called and
* result indicates the result of the transfer: Zero indicates a successful
* tranfers. On failure, a negated errno is returned indicating the general
* transfers. On failure, a negated errno is returned indicating the general
* nature of the DMA faiure.
*/

27
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/lpc17_irq.c
*
* Copyright (C) 2010-2011, 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2010-2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -76,11 +76,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
@ -313,8 +319,21 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*
* But even in this case NVIC_VECTAB has to point to the initial table
* because up_ramvec_initialize() initializes RAM table from table
* pointed by NVIC_VECTAB register.
*/
#ifdef CONFIG_ARCH_RAMVECTORS

2
arch/arm/src/lpc17xx/lpc17_lcd.c
View File

@ -565,7 +565,7 @@ int up_fbinitialize(void)
/* TFT panel */
#if CONFIG_LPC17_LCD_TFTPANEL
#ifdef CONFIG_LPC17_LCD_TFTPANEL
regval |= LCD_CTRL_LCDTFT;
#endif

2
arch/arm/src/lpc17xx/lpc17_sdcard.c
View File

@ -67,7 +67,7 @@
#include "chip/lpc17_syscon.h"
#include "chip/lpc17_pinconfig.h"
#if CONFIG_LPC17_SDCARD
#ifdef CONFIG_LPC17_SDCARD
/****************************************************************************
* Pre-processor Definitions

4
arch/arm/src/lpc17xx/lpc17_usbdev.c
View File

@ -2088,7 +2088,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_INT_ERRINT) != 0)
@ -2457,7 +2457,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN);

6
arch/arm/src/lpc214x/lpc214x_usbdev.c
View File

@ -212,7 +212,7 @@
/* USB RAM ********************************************************************
*
* UBS_UDCA is is list of 32 pointers to DMA desciptors located at the
* UBS_UDCA is is list of 32 pointers to DMA descriptors located at the
* beginning of USB RAM. Each pointer points to a DMA descriptor with
* assocated DMA buffer.
*/
@ -2052,7 +2052,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_DEVINT_EPRINT))
@ -2422,7 +2422,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC214X_USBDEV_EPDMAEN);

145
arch/arm/src/lpc43xx/Kconfig
View File

@ -163,6 +163,151 @@ config LPC43_ETHERNET
bool "Ethernet"
default n
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
config LPC43_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config LPC43_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it can be used.
This may include such things as configuring GPIOs, resetting the PHY, etc. If
LPC43_PHYINIT is defined in the configuration then the board specific logic must
provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call this function
one time before it first uses the PHY.
config LPC43_MII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface.
config LPC43_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
config LPC43_ETHFD
bool "Full duplex"
default n
depends on !LPC43_AUTONEG
---help---
If LPC43_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
config LPC43_ETH100MBPS
bool "100 Mbps"
default n
depends on !LPC43_AUTONEG
---help---
If LPC43_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config LPC43_PHYSR
int "PHY Status Register Address (decimal)"
depends on LPC43_AUTONEG
---help---
This must be provided if LPC43_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config LPC43_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on LPC43_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config LPC43_PHYSR_SPEED
hex "PHY Speed Mask"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config LPC43_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config LPC43_PHYSR_MODE
hex "PHY Mode Mask"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config LPC43_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config LPC43_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config LPC43_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config LPC43_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config LPC43_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config LPC43_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
config LPC43_RMII
bool
default y if !LPC43_MII
config LPC43_ETHERNET_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu
endif
config LPC43_EVNTMNTR
bool "Event Monitor"
default n

8
arch/arm/src/lpc43xx/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/lpc43xx/Make.defs
#
# Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
# Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -84,6 +84,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
@ -116,6 +118,10 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += lpc43_gpioint.c
endif
ifeq ($(CONFIG_LPC43_ETHERNET),y)
CHIP_CSRCS += lpc43_ethernet.c
endif
ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c
endif

2
arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
View File

@ -73,7 +73,7 @@
#define LPC43_EEPROM_RWSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_RWSTATE_OFFSET)
#define LPC43_EEPROM_AUTOPROG (LPC43_EEPROMC_BASE+LPC43_EEPROM_AUTOPROG_OFFSET)
#define LPC43_EEPROM_WSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_WSTATE_OFFSET)
# LPC43_EEPROM_CLKDIV (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET)
#define LPC43_EEPROM_CLKDIV (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET)
#define LPC43_EEPROM_PWRDWN (LPC43_EEPROMC_BASE+LPC43_EEPROM_PWRDWN_OFFSET)
/* EEPROM interrupt registers */

32
arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
View File

@ -181,7 +181,8 @@
/* MAC frame filter register */
#define ETH_MACFFLT_PR (1 << 0) /* Bit 0: Promiscuous mode */
/* Bits 1-2: Reserved */
#define ETH_MACFFLT_HUC (1 << 1) /* Bit 1: Hash Unicast */
#define ETH_MACFFLT_HMC (1 << 2) /* Bit 2: Hash Multicast */
#define ETH_MACFFLT_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */
#define ETH_MACFFLT_PM (1 << 4) /* Bit 4: Pass all multicast */
#define ETH_MACFFLT_DBF (1 << 5) /* Bit 5: Disable Broadcast Frames */
@ -191,9 +192,9 @@
# define ETH_MACFFLT_PCF_PAUSE (1 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all except Pause control frames */
# define ETH_MACFFLT_PCF_ALL (2 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all control frames */
# define ETH_MACFFLT_PCF_FILTER (3 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all that pass address filter */
#define ETH_MACFFLT_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */
#define ETH_MACFFLT_SAF (1 << 9) /* Bit 9: Source address filter */
/* Bits 10-30: Reserved */
/* Bit 8-9: Reserved */
#define ETH_MACFFLT_HPF (1 << 10) /* Bit 10: Hash or perfect filter */
/* Bits 11-30: Reserved */
#define ETH_MACFFLT_RA (1 << 31) /* Bit 31: Receive all */
/* MAC hash table high/low register (32-bit values) */
@ -208,7 +209,7 @@
# define ETH_MACMIIA_CR_100_150 (1 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
# define ETH_MACMIIA_CR_20_35 (2 << ETH_MACMIIA_CR_SHIFT) /* 20-35 MHz CLK_M4_ETHERNET/16 */
# define ETH_MACMIIA_CR_35_60 (3 << ETH_MACMIIA_CR_SHIFT) /* 35-60 MHz CLK_M4_ETHERNET/26 */
# define ETH_MACMIIA_CR_150_168 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-168 MHz CLK_M4_ETHERNET/102 */
# define ETH_MACMIIA_CR_150_250 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-250 MHz CLK_M4_ETHERNET/102 */
# define ETH_MACMIIA_CR_250_300 (5 << ETH_MACMIIA_CR_SHIFT) /* 250-300 MHz CLK_M4_ETHERNET/124 */
# define ETH_MACMIIA_CR_DIV42 (8 << ETH_MACMIIA_CR_SHIFT) /* 60-100 MHz CLK_M4_ETHERNET/42 */
# define ETH_MACMIIA_CR_DIV62 (9 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
@ -314,7 +315,7 @@
/* Bits 4-8: Reserved */
#define ETH_MACIM_TSIM (1 << 9) /* Bit 9: Time stamp interrupt mask */
/* Bits 10-31: Reserved */
#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSTIM)
#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSIM)
/* MAC address 0 high register */
@ -499,9 +500,9 @@
#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT)
#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
#define ETH_TDES0_LC (1 << 9) /* Bit 9: Late collision */
#define ETH_TDES0_LCL (1 << 9) /* Bit 9: Late collision */
#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */
#define ETH_TDES0_LC (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TDES0_LCR (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
@ -536,7 +537,7 @@
#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
#define ETH_RDES0_DE (1 << 2) /* Bit 2: Dribble bit error */
#define ETH_RDES0_DRE (1 << 2) /* Bit 2: Dribble bit error */
#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */
#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */
@ -548,7 +549,7 @@
#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */
#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
#define ETH_RDES0_DS (1 << 14) /* Bit 14: Descriptor error */
#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT)
@ -584,12 +585,12 @@
* transparent clock) */
# define ETH_RDES4_MT_PDELREQMM (6 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp (in peer-to-peer
* transparent clock) */
# define ETH_RDES4_MT_PDELREQFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
# define ETH_RDES4_MT_PDELRESFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
* peer-to-peer transparent clock) */
# define ETH_RDES4_MT_PDELREQFUS (8 << ETH_RDES4_MT_SHIFT) /* Announce */
# define ETH_RDES4_MT_PDELREQFUS (9 << ETH_RDES4_MT_SHIFT) /* Management */
# define ETH_RDES4_MT_PDELREQFUS (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
# define ETH_RDES4_MT_PDELREQFUS (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
# define ETH_RDES4_MT_ANNOUNCE (8 << ETH_RDES4_MT_SHIFT) /* Announce */
# define ETH_RDES4_MT_MANAGEMENT (9 << ETH_RDES4_MT_SHIFT) /* Management */
# define ETH_RDES4_MT_SIGNALING (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
# define ETH_RDES4_MT_PTP (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
#define ETH_RDES4_PTPTYPE (1 << 12) /* Bit 12: PTP frame type */
#define ETH_RDES4_PTPVERSION (1 << 13) /* Bit 13: PTP version */
/* Bits 14-31: Reserved */
@ -662,6 +663,5 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* LPC43_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */

4008
arch/arm/src/lpc43xx/lpc43_ethernet.c Normal file
View File

File diff suppressed because it is too large Load Diff

93
arch/arm/src/lpc43xx/lpc43_ethernet.h Normal file
View File

@ -0,0 +1,93 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_eth.h
*
* Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
#define __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/lpc43_ethernet.h"
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Function: lpc43_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be used.
* This may include such things as configuring GPIOs, resetting the PHY, etc. If
* CONFIG_LPC43_PHYINIT is defined in the configuration then the board specific
* logic must provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call
* this function one time before it first uses the PHY.
*
* Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
************************************************************************************/
#ifdef CONFIG_LPC43_PHYINIT
int lpc43_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H */

23
arch/arm/src/lpc43xx/lpc43_irq.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_irq.c
*
* Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -77,11 +77,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the vector table */
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern unsigned _vectors[];
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
@ -316,15 +322,16 @@ void up_irqinitialize(void)
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */

31
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -54,8 +54,7 @@
#include "up_arch.h"
#include "chip.h"
#include "lpc43_syscon.h"
#include "lpc43_pinconn.h"
#include "lpc43_pinconfig.h"
#include "lpc43_spi.h"
#ifdef CONFIG_LPC43_SPI
@ -93,7 +92,6 @@
* use the CCLK undivided to get the SPI_CLOCK.
*/
#define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
#define SPI_CLOCK LPC43_CCLK
/****************************************************************************
@ -545,36 +543,19 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
FAR struct spi_dev_s *lpc43_spiinitialize(int port)
{
FAR struct lpc43_spidev_s *priv = &g_spidev;
irqstate_t flags;
uint32_t regval;
/* Configure multiplexed pins as connected on the board. Chip select
* pins must be configured by board-specific logic. All SPI pins and
* one SPI1 pin (SCK) have multiple, alternative pin selection.
* one SPI1 pin (SCK) have multiple, alternative pin selections.
* Definitions in the board.h file must be provided to resolve the
* board-specific pin configuration like:
*
* #define GPIO_SPI_SCK GPIO_SPI_SCK_1
* #define PINCONF_SPI_SCK PINCONF_SPI_SCK_1
*/
flags = irqsave();
lpc43_configgpio(GPIO_SPI_SCK);
lpc43_configgpio(GPIO_SPI_MISO);
lpc43_configgpio(GPIO_SPI_MOSI);
/* Configure clocking */
regval = getreg32(LPC43_SYSCON_PCLKSEL0);
regval &= ~SYSCON_PCLKSEL0_SPI_MASK;
regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT);
putreg32(regval, LPC43_SYSCON_PCLKSEL0);
/* Enable peripheral clocking to SPI and SPI1 */
regval = getreg32(LPC43_SYSCON_PCONP);
regval |= SYSCON_PCONP_PCSPI;
putreg32(regval, LPC43_SYSCON_PCONP);
irqrestore(flags);
lpc43_pin_config(PINCONF_SPI_SCK);
lpc43_pin_config(PINCONF_SPI_MISO);
lpc43_pin_config(PINCONF_SPI_MOSI);
/* Configure 8-bit SPI mode and master mode */

2
arch/arm/src/lpc43xx/lpc43_spifi.c
View File

@ -1093,7 +1093,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
fvdbg(" blksize: %08x\n", priv->blksize);
fvdbg(" nblocks: %d\n", priv->nblocks);
#if CONFIG_SPIFI_SECTOR512
#ifdef CONFIG_SPIFI_SECTOR512
DEBUGASSERT(log2 > 9);
#endif

1
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -63,6 +63,7 @@
#include <nuttx/init.h>
#include <arch/board/board.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "up_internal.h"

15
arch/arm/src/lpc43xx/lpc43_uart.c
View File

@ -192,23 +192,18 @@ void up_lowputc(char ch)
* as possible.
*
* The USART0/2/3 and UART1 peripherals are configured using the following registers:
* 1. Power: In the PCONP register, set bits PCUSART0/1/2/3.
* On reset, USART0 and UART 1 are enabled (PCUSART0 = 1 and PCUART1 = 1)
* and USART2/3 are disabled (PCUART1 = 0 and PCUSART3 = 0).
* 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_USART0 and
* PCLK_UART1; in the PCLKSEL1 register, select PCLK_USART2 and PCLK_USART3.
* 3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* 1. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* to registers DLL and DLM for setting the baud rate. Also, if needed,
* set the fractional baud rate in the fractional divider
* 4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
* 2. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
* enable FIFO.
* 5. Pins: Select UART pins through the PINSEL registers and pin modes
* 3. Pins: Select UART pins through the PINSEL registers and pin modes
* through the PINMODE registers. UART receive pins should not have
* pull-down resistors enabled.
* 6. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
* 4. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
* register. This enables access to IER. Interrupts are enabled
* in the NVIC using the appropriate Interrupt Set Enable register.
* 7. DMA: UART transmit and receive functions can operate with the
* 5. DMA: UART transmit and receive functions can operate with the
* GPDMA controller.
*
**************************************************************************/

9
arch/arm/src/moxart/Kconfig
View File

@ -7,3 +7,12 @@ comment "MoxART Configuration Options"
config UART_MOXA_MODE_REG
hex "16550 UART mode register address"
default 0x982000E0
config UART_MOXA_IRQ_STATUS_REG
hex "16550 UART shared IRQ status register address"
default 0x982000C0
config UART_MOXA_SHARED_IRQ
int "16550 UART shared IRQ number"
default 31

30
arch/arm/src/moxart/moxart_16550.c
View File

@ -67,6 +67,30 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset, uart_datawidth_t va
*((volatile uart_addrwidth_t *)base + offset) = value;
}
void uart_decodeirq(int irq, FAR void *context)
{
int i;
uint32_t status;
static int os = 0;
status = *((volatile uart_addrwidth_t *)CONFIG_UART_MOXA_IRQ_STATUS_REG);
if ((status & 0x3f) == 0x3f)
{
return;
}
i = 0;
do
{
if (!(status & 0x1)) {
irq_dispatch(VIRQ_START + i, context);
}
status >>= 1;
}
while (++i <= 4);
}
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
{
@ -109,9 +133,12 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Update mode register with requested mode */
vmode = getreg32(CONFIG_UART_MOXA_MODE_REG);
putreg32(CONFIG_UART_MOXA_MODE_REG, (vmode & ~(OP_MODE_MASK << 2 * bitm_off)) | ((opmode << 2 * bitm_off) & 0xffff));
putreg32(vmode & ~(OP_MODE_MASK << 2 * bitm_off), CONFIG_UART_MOXA_MODE_REG);
vmode = opmode << 2 * bitm_off;
putreg32(getreg32(CONFIG_UART_MOXA_MODE_REG) | vmode, CONFIG_UART_MOXA_MODE_REG);
irqrestore(flags);
ret = OK;
break;
}
@ -126,6 +153,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
irqrestore(flags);
*(unsigned long *)arg = opmode;
ret = OK;
break;
}
}

13
arch/arm/src/moxart/moxart_irq.c
View File

@ -81,6 +81,8 @@ volatile uint32_t *current_regs;
* Public Functions
****************************************************************************/
extern void uart_decodeirq(int irq, uint32_t *regs);
/****************************************************************************
* Name: up_irqinitialize
*
@ -93,6 +95,10 @@ void up_irqinitialize(void)
{
/* Prepare hardware */
*(volatile int *)0x98700000 |= 0x3f;
/* PMU setup */
(*(volatile uint32_t *)0x98100008) &= ~0x9;
while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; }
@ -101,6 +107,8 @@ void up_irqinitialize(void)
(*(volatile uint32_t *)0x98800100) = 0xDFF8003F;
/* Check board type */
/* Mask all interrupts off */
putreg32(0, IRQ_REG(IRQ__MASK));
@ -119,6 +127,11 @@ void up_irqinitialize(void)
current_regs = NULL;
/* Setup UART shared interrupt */
irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq);
up_enable_irq(CONFIG_UART_MOXA_SHARED_IRQ);
/* And finally, enable interrupts */
#if 1

3
arch/arm/src/moxart/moxart_timer.c
View File

@ -132,9 +132,6 @@ void up_timer_initialize(void)
uint32_t tmp;
// up_disable_irq(IRQ_SYSTIMER);
*(volatile int *)0x98700000 = 0x3f;
putreg32(0, TM1_ADDR + CNTL_TIMER);
putreg32(0, TM1_ADDR + INTR_STATE_TIMER);
putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER);

2
arch/arm/src/nuc1xx/chip/nuc_gcr.h
View File

@ -356,7 +356,7 @@
# define GCR_REGWRPROT_2 (0x16)
# define GCR_REGWRPROT_3 (0x88)
/* Read: */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protection disable index */
/********************************************************************************************
* Public Types

2
arch/arm/src/sam34/Make.defs
View File

@ -91,6 +91,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif

2
arch/arm/src/sam34/sam4l_clockconfig.c
View File

@ -1293,7 +1293,7 @@ void sam_clockconfig(void)
* OSC32: Might be source clock for DFLL0
*/
#if NEED_OSC0
#ifdef NEED_OSC0
/* Enable OSC0 using the settings in board.h */
sam_enableosc0();

2
arch/arm/src/sam34/sam_dmac.c
View File

@ -1225,7 +1225,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach)
* Additionally, the CTRLA DONE bit is asserted when the buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the descriptor
* (DSCR bits) registers at the final buffer tranfer.
* (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them

2
arch/arm/src/sam34/sam_hsmci.c
View File

@ -80,7 +80,7 @@
# include "chip/sam_pdc.h"
#endif
#if CONFIG_SAM34_HSMCI
#ifdef CONFIG_SAM34_HSMCI
/****************************************************************************
* Pre-processor Definitions

26
arch/arm/src/sam34/sam_irq.c
View File

@ -78,7 +78,16 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
@ -378,16 +387,21 @@ void up_irqinitialize(void)
}
#endif
/* Set up the vector table address.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */

6
arch/arm/src/sam34/sam_rtc.c
View File

@ -254,7 +254,7 @@ static int rtc_bcd2bin(uint32_t value)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static void rtc_worker(FAR void *arg)
{
/* Sample once (atomically) */
@ -287,7 +287,7 @@ static void rtc_worker(FAR void *arg)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
int ret;
@ -414,7 +414,7 @@ int up_rtcinitialize(void)
#endif
#if defined(CONFIG_RTC_HIRES) && defined (CONFIG_SAM34_RTT)
#if defined(CONFIG_RTC_HIRES) && defined(CONFIG_SAM34_RTT)
/* Using the RTT for subsecond ticks. */
sam_rtt_enableclk();

4
arch/arm/src/sam34/sam_timerisr.c
View File

@ -85,7 +85,7 @@
#undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */
#if CONFIG_SAM34_SYSTICK_HCLKd8
#ifdef CONFIG_SAM34_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1)
@ -152,7 +152,7 @@ void up_timer_initialize(void)
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#if CONFIG_SAM34_SYSTICK_HCLKd8
#ifdef CONFIG_SAM34_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;

4
arch/arm/src/sam34/sam_udp.c
View File

@ -500,7 +500,7 @@ static const struct usb_epdesc_s g_ep0desc =
.interval = 0
};
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@ -540,7 +540,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/

64
arch/arm/src/sama5/Kconfig
View File

@ -73,6 +73,10 @@ config SAMA5_HAVE_HSMCI2
bool
default n
config SAMA5_HAVE_PIOE
bool
default n
config SAMA5_HAVE_SAIC
bool
default n
@ -115,10 +119,30 @@ config SAMA5_HAVE_VDEC
# Chip Selection
config ARCH_CHIP_SAMA5D2
bool
default n
select SAMA5_HAVE_AESB
select ARCH_NAND_HWECC
select SAMA5_HAVE_EMACB
select SAMA5_HAVE_ICM
select SAMA5_HAVE_LCDC
select SAMA5_HAVE_UART0
select SAMA5_HAVE_UART1
select SAMA5_HAVE_USART4
select SAMA5_HAVE_QSPI
select SAMA5_HAVE_XDMA
select SAMA5_HAVE_SAIC
select SAMA5_HAVE_SFC
select SAMA5_HAVE_SPI2
select SAMA5_HAVE_TC1
select SAMA5_HAVE_TRUSTZONE
config ARCH_CHIP_SAMA5D3
bool
default n
select SAMA5_HAVE_DMA
select SAMA5_HAVE_PIOE
config ARCH_CHIP_SAMA5D4
bool
@ -134,6 +158,7 @@ config ARCH_CHIP_SAMA5D4
select SAMA5_HAVE_UART1
select SAMA5_HAVE_USART4
select SAMA5_HAVE_XDMA
select SAMA5_HAVE_PIOE
select SAMA5_HAVE_SAIC
select SAMA5_HAVE_SBM
select SAMA5_HAVE_SFC
@ -147,6 +172,44 @@ choice
prompt "Atmel AT91SAMA5 Chip Selection"
default ARCH_CHIP_ATSAMA5D33
config ARCH_CHIP_ATSAMA5D21
bool "Atmel ATSAMA5D21"
select ARCH_CHIP_SAMA5D2
config ARCH_CHIP_ATSAMA5D22
bool "Atmel ATSAMA5D22"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_CAN0
config ARCH_CHIP_ATSAMA5D23
bool "Atmel ATSAMA5D23"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_CAN0
config ARCH_CHIP_ATSAMA5D24
bool "Atmel ATSAMA5D24"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_DDR32
config ARCH_CHIP_ATSAMA5D26
bool "Atmel ATSAMA5D26"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_DDR32
config ARCH_CHIP_ATSAMA5D27
bool "Atmel ATSAMA5D27"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_CAN0
select SAMA5_HAVE_CAN1
select SAMA5_HAVE_DDR32
config ARCH_CHIP_ATSAMA5D28
bool "Atmel ATSAMA5D28"
select ARCH_CHIP_SAMA5D2
select SAMA5_HAVE_CAN0
select SAMA5_HAVE_CAN1
select SAMA5_HAVE_DDR32
config ARCH_CHIP_ATSAMA5D31
bool "Atmel ATSAMA5D31"
select ARCH_CHIP_SAMA5D3
@ -572,6 +635,7 @@ config SAMA5_PIOD_IRQ
config SAMA5_PIOE_IRQ
bool "PIOE interrupts"
default n
depends on SAMA5_HAVE_PIOE
endif # PIO_IRQ

6
arch/arm/src/sama5/chip/sam_memorymap.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_memorymap.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -43,7 +43,9 @@
#include <nuttx/config.h>
#include <arch/sama5/chip.h>
#if defined(ATSAMA5D3)
#if defined(ATSAMA5D2)
# include "chip/sama5d2x_memorymap.h"
#elif defined(ATSAMA5D3)
# include "chip/sama5d3x_memorymap.h"
#elif defined(ATSAMA5D4)
# include "chip/sama5d4x_memorymap.h"

4
arch/arm/src/sama5/sam_adc.c
View File

@ -1577,10 +1577,10 @@ static void sam_adc_offset(struct sam_adc_s *priv)
* used for all channel.
*/
#if CONFIG_SAMA5_ADC_OFFSET
#ifdef CONFIG_SAMA5_ADC_OFFSET
regval |= ADC_COR_OFF0;
#endif
#if CONFIG_SAMA5_ADC_DIFFMODE
#ifdef CONFIG_SAMA5_ADC_DIFFMODE
regval |= ADC_COR_DIFF0;
#endif
#endif

26
arch/arm/src/sama5/sam_can.c
View File

@ -733,7 +733,10 @@ static int can_recvsetup(FAR struct sam_can_s *priv)
canvdbg("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
config->port, mbno, mbndx, priv->rxmbset);
/* Set up the message ID and filter mask */
/* Set up the message ID and filter mask
* REVISIT: This logic should be capable of setting up standard
* filters when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx),
@ -1125,14 +1128,16 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
canvdbg("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
/* Set up the ID and mask, standard 11-bit or extended 29-bit. */
/* Set up the ID and mask, standard 11-bit or extended 29-bit.
* REVISIT: This logic should be capable of sending standard messages
* when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
DEBUGASSERT(msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_EXTID(msg->cm_hdr.ch_id));
#else
DEBUGASSERT(!msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_STDID(msg->cm_hdr.ch_id));
#endif
@ -1309,24 +1314,27 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
mid = can_getreg(priv, SAM_CAN_MnID_OFFSET(mbndx));
/* Format the CAN header */
/* Format the CAN header.
* REVISIT: This logic should be capable of receiving standard messages
* when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
/* Save the extended ID of the newly received message */
hdr.ch_id = (mid & CAN_MAM_EXTID_MASK) >> CAN_MAM_EXTID_SHIFT;
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_extid = true;
hdr.ch_unused = 0;
#else
/* Save the standard ID of the newly received message */
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_id = (mid & CAN_MAM_STDID_MASK) >> CAN_MAM_STDID_SHIFT;
#endif
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_error = 0;
hdr.ch_unused = 0;
/* And provide the CAN message to the upper half logic */
ret = can_receive(dev, &hdr, (FAR uint8_t *)md);

4
arch/arm/src/sama5/sam_dmac.c
View File

@ -1721,7 +1721,7 @@ static inline int sam_multiple(struct sam_dmach_s *dmach)
* buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the
* descriptor (DSCR bits) registers at the final buffer tranfer.
* descriptor (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them
@ -2309,7 +2309,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
dmach->callback = callback;
dmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (dmach->llhead == dmach->lltail)
{

6
arch/arm/src/sama5/sam_periphclks.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/sama5/sam_periphclks.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -47,7 +47,9 @@
/* Include the correctly logic for the configured chip */
#if defined(ATSAMA5D3)
#if defined(ATSAMA5D2)
# include "sama5d2x_periphclks.h"
#elif defined(ATSAMA5D3)
# include "sama5d3x_periphclks.h"
#elif defined(ATSAMA5D4)
# include "sama5d4x_periphclks.h"

4
arch/arm/src/sama5/sam_rtc.c
View File

@ -245,7 +245,7 @@ static int rtc_bcd2bin(uint32_t value)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static void rtc_worker(FAR void *arg)
{
/* Sample once (atomically) */
@ -278,7 +278,7 @@ static void rtc_worker(FAR void *arg)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
int ret;

2
arch/arm/src/sama5/sam_tsd.c
View File

@ -1552,7 +1552,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv)
sam_adc_getreg(priv->adc, SAM_ADC_XPOSR);
sam_adc_getreg(priv->adc, SAM_ADC_YPOSR);
#if CONFIG_SAMA5_TSD_4WIRE
#ifdef CONFIG_SAMA5_TSD_4WIRE
sam_adc_getreg(priv->adc, SAM_ADC_PRESSR);
#endif

10
arch/arm/src/sama5/sam_udphs.c
View File

@ -555,7 +555,7 @@ static const struct usb_epdesc_s g_ep0desc =
#ifdef CONFIG_SAMA5_UDPHS_SCATTERGATHER
#ifdef CONFIG_SAMA5_UDPHS_PREALLOCATE
/* This is a properly aligned pool of preallocated DMA transfer desciptors */
/* This is a properly aligned pool of preallocated DMA transfer descriptors */
static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS]
__attribute__ ((aligned(16)));
@ -563,7 +563,7 @@ static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS]
#endif
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@ -604,7 +604,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
@ -1280,7 +1280,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When a request is queued, the request 'len' is the number of bytes
* to transfer and 'xfrd' and 'inflight' must be zero.
*
* When this function starts a tranfer it will update the request
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
@ -1547,7 +1547,7 @@ static void sam_req_rddisable(uint8_t epno)
* - When receiving data via DMA, then data has already been transferred
* and this function is called on the terminating event. The transfer
* is complete and we just need to check for end of request events and
* if we need to setup the tranfer for the next request.
* if we need to setup the transfer for the next request.
* - When receiving via the FIFO, the transfer is not complete. The
* data is in the FIFO and must be transferred from the FIFO to the
* request buffer. No setup is needed for the next transfer other than

2
arch/arm/src/sama5/sam_xdmac.c
View File

@ -2355,7 +2355,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
xdmach->callback = callback;
xdmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (xdmach->llhead == xdmach->lltail)
{

303
arch/arm/src/sama5/sama5d2x_periphclks.h Normal file
View File

@ -0,0 +1,303 @@
/************************************************************************************
* arch/arm/src/sama5/sama5d2x_periphclks.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "chip/sam_pmc.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
#define sam_fiq_enableclk() /* No peripheral clock */
#define sam_arm_enableclk() /* No peripheral clock */
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_emac0_enableclk() sam_enableperiph0(SAM_PID_EMAC0)
#define sam_xdmac0_enableclk() sam_enableperiph0(SAM_PID_XDMAC0)
#define sam_xdmac1_enableclk() sam_enableperiph0(SAM_PID_XDMAC1)
#define sam_icm_enableclk() sam_enableperiph0(SAM_PID_ICM)
#define sam_aes_enableclk() sam_enableperiph0(SAM_PID_AES)
#define sam_aesb_enableclk() sam_enableperiph0(SAM_PID_AESB)
#define sam_tdes_enableclk() sam_enableperiph0(SAM_PID_TDES)
#define sam_sha_enableclk() sam_enableperiph0(SAM_PID_SHA)
#define sam_mpddrc_enableclk() sam_enableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_enableclk() sam_enableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_enableclk() sam_enableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM4)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
#define sam_uart2_enableclk() sam_enableperiph0(SAM_PID_UART2)
#define sam_uart3_enableclk() sam_enableperiph0(SAM_PID_UART3)
#define sam_uart4_enableclk() sam_enableperiph0(SAM_PID_UART4)
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
#define sam_sdmmc0_enableclk() sam_enableperiph0(SAM_PID_SDMMC0)
#define sam_sdmmc1_enableclk() sam_enableperiph1(SAM_PID_SDMMC1)
#define sam_spi0_enableclk() sam_enableperiph1(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
#define sam_tc0_enableclk() sam_enableperiph1(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph1(SAM_PID_TC1)
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
#define sam_isc_enableclk() sam_enableperiph1(SAM_PID_ISC)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_pdmic_enableclk() sam_enableperiph1(SAM_PID_PDMIC)
#define sam_irqid_enableclk() sam_enableperiph1(SAM_PID_IRQID)
#define sam_sfc_enableclk() sam_enableperiph1(SAM_PID_SFC)
#define sam_securam_enableclk() sam_enableperiph1(SAM_PID_SECURAM)
#define sam_qspi0_enableclk() sam_enableperiph1(SAM_PID_QSPI0)
#define sam_qspi1_enableclk() sam_enableperiph1(SAM_PID_QSPI1)
#define sam_i2sc0_enableclk() sam_enableperiph1(SAM_PID_I2SC0)
#define sam_i2sc1_enableclk() sam_enableperiph1(SAM_PID_I2SC1)
#define sam_mcan0_enableclk() sam_enableperiph1(SAM_PID_MCAN00)
#define sam_mcan1_enableclk() sam_enableperiph1(SAM_PID_MCAN10)
#define sam_classd_enableclk() sam_enableperiph1(SAM_PID_CLASSD)
#define sam_sfr_enableclk() sam_enableperiph1(SAM_PID_SFR)
#define sam_saic_enableclk() sam_enableperiph1(SAM_PID_SAIC)
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
#define sam_piob_enableclk() /* No peripheral clock */
#define sam_pioc_enableclk() /* No peripheral clock */
#define sam_piod_enableclk() /* No peripheral clock */
#define sam_sys_enableclk() /* No peripheral clock */
#define sam_acc_enableclk() /* No peripheral clock */
#define sam_rxlp_enableclk() /* No peripheral clock */
#define sam_sfrbu_enableclk() /* No peripheral clock */
#define sam_chipid_enableclk() /* No peripheral clock */
#define sam_fiq_disableclk() /* No peripheral clock */
#define sam_arm_disableclk() /* No peripheral clock */
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_emac0_disableclk() sam_disableperiph0(SAM_PID_EMAC0)
#define sam_xdmac0_disableclk() sam_disableperiph0(SAM_PID_XDMAC0)
#define sam_xdmac1_disableclk() sam_disableperiph0(SAM_PID_XDMAC1)
#define sam_icm_disableclk() sam_disableperiph0(SAM_PID_ICM)
#define sam_aes_disableclk() sam_disableperiph0(SAM_PID_AES)
#define sam_aesb_disableclk() sam_disableperiph0(SAM_PID_AESB)
#define sam_tdes_disableclk() sam_disableperiph0(SAM_PID_TDES)
#define sam_sha_disableclk() sam_disableperiph0(SAM_PID_SHA)
#define sam_mpddrc_disableclk() sam_disableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_disableclk() sam_disableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_disableclk() sam_disableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM4)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
#define sam_uart2_disableclk() sam_disableperiph0(SAM_PID_UART2)
#define sam_uart3_disableclk() sam_disableperiph0(SAM_PID_UART3)
#define sam_uart4_disableclk() sam_disableperiph0(SAM_PID_UART4)
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
#define sam_sdmmc0_disableclk() sam_disableperiph0(SAM_PID_SDMMC0)
#define sam_sdmmc1_disableclk() sam_disableperiph1(SAM_PID_SDMMC1)
#define sam_spi0_disableclk() sam_disableperiph1(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
#define sam_tc0_disableclk() sam_disableperiph1(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph1(SAM_PID_TC1)
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
#define sam_isc_disableclk() sam_disableperiph1(SAM_PID_ISC)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_pdmic_disableclk() sam_disableperiph1(SAM_PID_PDMIC)
#define sam_irqid_disableclk() sam_disableperiph1(SAM_PID_IRQID)
#define sam_sfc_disableclk() sam_disableperiph1(SAM_PID_SFC)
#define sam_securam_disableclk() sam_disableperiph1(SAM_PID_SECURAM)
#define sam_qspi0_disableclk() sam_disableperiph1(SAM_PID_QSPI0)
#define sam_qspi1_disableclk() sam_disableperiph1(SAM_PID_QSPI1)
#define sam_i2sc0_disableclk() sam_disableperiph1(SAM_PID_I2SC0)
#define sam_i2sc1_disableclk() sam_disableperiph1(SAM_PID_I2SC1)
#define sam_mcan0_disableclk() sam_disableperiph1(SAM_PID_MCAN00)
#define sam_mcan1_disableclk() sam_disableperiph1(SAM_PID_MCAN10)
#define sam_classd_disableclk() sam_disableperiph1(SAM_PID_CLASSD)
#define sam_sfr_disableclk() sam_disableperiph1(SAM_PID_SFR)
#define sam_saic_disableclk() sam_disableperiph1(SAM_PID_SAIC)
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
#define sam_piob_disableclk() /* No peripheral clock */
#define sam_pioc_disableclk() /* No peripheral clock */
#define sam_piod_disableclk() /* No peripheral clock */
#define sam_sys_disableclk() /* No peripheral clock */
#define sam_acc_disableclk() /* No peripheral clock */
#define sam_rxlp_disableclk() /* No peripheral clock */
#define sam_sfrbu_disableclk() /* No peripheral clock */
#define sam_chipid_disableclk() /* No peripheral clock */
#define sam_fiq_isenabled() (false) /* No peripheral clock */
#define sam_arm_isenabled() (false) /* No peripheral clock */
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
#define sam_emac0_isenabled() sam_isenabled0(SAM_PID_EMAC0)
#define sam_xdmac0_isenabled() sam_isenabled0(SAM_PID_XDMAC0)
#define sam_xdmac1_isenabled() sam_isenabled0(SAM_PID_XDMAC1)
#define sam_icm_isenabled() sam_isenabled0(SAM_PID_ICM)
#define sam_aes_isenabled() sam_isenabled0(SAM_PID_AES)
#define sam_aesb_isenabled() sam_isenabled0(SAM_PID_AESB)
#define sam_tdes_isenabled() sam_isenabled0(SAM_PID_TDES)
#define sam_sha_isenabled() sam_isenabled0(SAM_PID_SHA)
#define sam_mpddrc_isenabled() sam_isenabled0(SAM_PID_MPDDRC)
#define sam_matrix1_isenabled() sam_isenabled0(SAM_PID_MATRIX1)
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
#define sam_secumod_isenabled() sam_isenabled0(SAM_PID_SECUMOD)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_flexcom0_isenabled() sam_isenabled0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_isenabled() sam_isenabled0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_isenabled() sam_isenabled0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_isenabled() sam_isenabled0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_isenabled() sam_isenabled0(SAM_PID_FLEXCOM4)
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
#define sam_uart2_isenabled() sam_isenabled0(SAM_PID_UART2)
#define sam_uart3_isenabled() sam_isenabled0(SAM_PID_UART3)
#define sam_uart4_isenabled() sam_isenabled0(SAM_PID_UART4)
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
#define sam_sdmmc0_isenabled() sam_isenabled0(SAM_PID_SDMMC0)
#define sam_sdmmc1_isenabled() sam_isenabled1(SAM_PID_SDMMC1)
#define sam_spi0_isenabled() sam_isenabled1(SAM_PID_SPI0)
#define sam_spi1_isenabled() sam_isenabled1(SAM_PID_SPI1)
#define sam_tc0_isenabled() sam_isenabled1(SAM_PID_TC0)
#define sam_tc1_isenabled() sam_isenabled1(SAM_PID_TC1)
#define sam_pwm_isenabled() sam_isenabled1(SAM_PID_PWM)
#define sam_adc_isenabled() sam_isenabled1(SAM_PID_ADC)
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
#define sam_isc_isenabled() sam_isenabled1(SAM_PID_ISC)
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
#define sam_pdmic_isenabled() sam_isenabled1(SAM_PID_PDMIC)
#define sam_irqid_isenabled() sam_isenabled1(SAM_PID_IRQID)
#define sam_sfc_isenabled() sam_isenabled1(SAM_PID_SFC)
#define sam_securam_isenabled() sam_isenabled1(SAM_PID_SECURAM)
#define sam_qspi0_isenabled() sam_isenabled1(SAM_PID_QSPI0)
#define sam_qspi1_isenabled() sam_isenabled1(SAM_PID_QSPI1)
#define sam_i2sc0_isenabled() sam_isenabled1(SAM_PID_I2SC0)
#define sam_i2sc1_isenabled() sam_isenabled1(SAM_PID_I2SC1)
#define sam_mcan0_isenabled() sam_isenabled1(SAM_PID_MCAN00)
#define sam_mcan1_isenabled() sam_isenabled1(SAM_PID_MCAN10)
#define sam_classd_isenabled() sam_isenabled1(SAM_PID_CLASSD)
#define sam_sfr_isenabled() sam_isenabled1(SAM_PID_SFR)
#define sam_saic_isenabled() sam_isenabled1(SAM_PID_SAIC)
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
#define sam_piob_isenabled() (false) /* No peripheral clock */
#define sam_pioc_isenabled() (false) /* No peripheral clock */
#define sam_piod_isenabled() (false) /* No peripheral clock */
#define sam_sys_isenabled() (false) /* No peripheral clock */
#define sam_acc_isenabled() (false) /* No peripheral clock */
#define sam_rxlp_isenabled() (false) /* No peripheral clock */
#define sam_sfrbu_isenabled() (false) /* No peripheral clock */
#define sam_chipid_isenabled() (false) /* No peripheral clock */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H */

2
arch/arm/src/samdl/chip/saml_eic.h
View File

@ -106,7 +106,7 @@
# define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NVMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NVMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detectino mode */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */
/* Non-maskable interrupt flas status and clear register */

17
arch/arm/src/samdl/sam_lowputc.c
View File

@ -296,6 +296,9 @@ sam_pad_configure(const struct sam_usart_config_s * const config)
#ifdef SAMDL_HAVE_USART
int sam_usart_internal(const struct sam_usart_config_s * const config)
{
#ifdef CONFIG_ARCH_FAMILY_SAML21
int channel;
#endif
int ret;
/* Enable clocking to the SERCOM module */
@ -306,10 +309,20 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
sam_gclk_chan_enable(config->sercom + GCLK_CHAN_SERCOM0_CORE,
config->gclkgen);
if (config->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
#endif
sercom_slowclk_configure(config->sercom, config->slowgen);
/* Set USART configuration according to the board configuration */

12
arch/arm/src/samdl/sam_port.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samdl/sam_port.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
@ -94,7 +94,7 @@ static inline uintptr_t sam_portbase(port_pinset_t pinset)
* Name: sam_portpin
*
* Description:
* Returun the base address of the PORT register set
* Return the bit associated with the pin
*
****************************************************************************/
@ -330,7 +330,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset)
regval |= PORT_WRCONFIG_INEN;
}
if (pin > 16)
if (pin >= 16)
{
/* Select the upper half word and adjust the bit setting */
@ -538,15 +538,15 @@ int sam_dumpport(uint32_t pinset, const char *msg)
/* Get the base address associated with the PIO port */
pin = sam_portpin(pinset);
pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
port = (pinset & PORT_MASK) >> PORT_SHIFT;
base = SAM_PORTN_BASE(port);
/* The following requires exclusive access to the PORT registers */
flags = irqsave();
lldbg("PORT%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
lldbg("PORT%c pin: %d pinset: %08x base: %08x -- %s\n",
g_portchar[port], pin, pinset, base, msg);
lldbg(" DIR: %08x OUT: %08x IN: %08x\n",
getreg32(base + SAM_PORT_DIR_OFFSET),
getreg32(base + SAM_PORT_OUT_OFFSET),

2
arch/arm/src/samdl/sam_port.h
View File

@ -380,7 +380,7 @@ bool sam_portread(port_pinset_t pinset);
****************************************************************************/
#ifdef CONFIG_DEBUG
void sam_dumpport(port_pinset_t pinset, const char *msg);
int sam_dumpport(port_pinset_t pinset, const char *msg);
#else
# define sam_dumpport(p,m)
#endif

18
arch/arm/src/samdl/sam_spi.c
View File

@ -1467,6 +1467,9 @@ struct spi_dev_s *up_spiinitialize(int port)
struct sam_spidev_s *priv;
irqstate_t flags;
uint32_t regval;
#ifdef CONFIG_ARCH_FAMILY_SAML21
int channel;
#endif
#if 0 /* Not used */
int ret;
#endif
@ -1534,7 +1537,22 @@ struct spi_dev_s *up_spiinitialize(int port)
/* Configure the GCLKs for the SERCOM module */
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
sercom_coreclk_configure(priv->sercom, priv->gclkgen, false);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
if (priv->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = priv->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
#endif
sercom_slowclk_configure(priv->sercom, priv->slowgen);
/* Set the SERCOM in SPI master mode (no address) */

171
arch/arm/src/samv7/Kconfig
View File

@ -147,10 +147,6 @@ config SAMV7_HAVE_SDRAMC
bool
default n
config SAMV7_HAVE_SPI
bool
default n
config SAMV7_HAVE_SPI0
bool
default n
@ -191,6 +187,18 @@ config SAMV7_HAVE_USART2
bool
default n
config SAMV7_SPI
bool
default n
config SAMV7_SPI_MASTER
bool
default n
config SAMV7_SPI_SLAVE
bool
default n
# Peripheral Selection
menu "SAMV7 Peripheral Selection"
@ -299,14 +307,14 @@ config SAMV7_SPI0
bool "Serial Peripheral Interface 0 (SPI0)"
default n
depends on SAMV7_HAVE_SPI0
select SAMV7_HAVE_SPI
select SAMV7_SPI
select SPI
config SAMV7_SPI1
bool "Serial Peripheral Interface 1 (SPI1)"
default n
depends on SAMV7_HAVE_SPI1
select SAMV7_HAVE_SPI
select SAMV7_SPI
select SPI
config SAMV7_SSC0
@ -504,7 +512,6 @@ config SAMV7_GPIOE_IRQ
default n
endif # SAMV7_GPIO_IRQ
endif # ARCH_CHIP_SAMV7
menu "SDRAM Configuration"
depends on SAMV7_SDRAMC
@ -526,8 +533,51 @@ config SAMV7_SDRAMHEAP
endmenu # SDRAM Configuration
menu "SAMV7 SPI device driver options"
depends on AMV7_SPI0 || SAMV7_SPI1
menu "SPI Device Driver Configuration"
depends on SAMV7_SPI
choice
prompt "SPI0 Configuration"
default SAMV7_SPI0_MASTER
depends on SAMV7_SPI0
config SAMV7_SPI0_MASTER
bool "Master"
select SAMV7_SPI_MASTER
---help---
Configure SPI0 as an SPI master driver. Default: Master
config SAMV7_SPI0_SLAVE
bool "Slave"
depends on EXPERIMENTAL
select SAMV7_SPI_SLAVE
---help---
Configure SPI0 as an SPI slave driver. Default: Master
endchoice # SPI0 Configuration
choice
prompt "SPI1 Configuration"
default SAMV7_SPI1_MASTER
depends on SAMV7_SPI1
config SAMV7_SPI1_MASTER
bool "Master"
select SAMV7_SPI_MASTER
---help---
Configure SPI1 as an SPI master driver. Default: Master
config SAMV7_SPI1_SLAVE
bool "Slave"
depends on EXPERIMENTAL
select SAMV7_SPI_SLAVE
---help---
Configure SPI1 as an SPI slave driver. Default: Master
endchoice # SPI1 Configuration
if SAMV7_SPI_MASTER
comment "SPI Master Configuration"
config SAMV7_SPI_DMA
bool "SPI DMA"
@ -555,6 +605,20 @@ config SAMV7_SPI_DMADEBUG
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer.
endif # SAMV7_SPI_MASTER
if SAMV7_SPI_SLAVE
comment "SPI Slave Configuration"
config SAMV7_SPI_SLAVE_QSIZE
int "Output queue size"
default 8
---help---
The number of words that an be retained in the controller driver's
output queue.
endif # SAMV7_SPI_SLAVE
config SAMV7_SPI_REGDEBUG
bool "SPI Register level debug"
depends on DEBUG
@ -563,7 +627,54 @@ config SAMV7_SPI_REGDEBUG
Output detailed register-level SPI device debug information.
Requires also DEBUG.
endmenu # SAMV7 SPI device driver options
endmenu # SPI device driver options
menu "QSPI Device Driver Configuration"
depends on SAMV7_QSPI && !SAMV7_QSPI_IS_SPI
config SAMV7_QSPI_DLYBS
int "Delay Before QSCK (nsec)"
default 0
config SAMV7_QSPI_DLYBCT
int "Delay Between Consecutive Transfers (nsec)"
default 0
config SAMV7_QSPI_DMA
bool "QSPI DMA"
default n
depends on SAMV7_XDMAC
---help---
Use DMA to improve SPI transfer performance.
config SAMV7_QSPI_DMATHRESHOLD
int "QSPI DMA threshold"
default 4
depends on SAMV7_QSPI_DMA
---help---
When ASPI DMA is enabled, small DMA transfers will still be performed
by polling logic. But we need a threshold value to determine what
is small. That value is provided by SAMV7_QSPI_DMATHRESHOLD.
config SAMV7_QSPI_DMADEBUG
bool "QSPI DMA transfer debug"
depends on SAMV7_QSPI_DMA && DEBUG && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze QSPI DMA data transfers.
This logic is as non-invasive as possible: It samples DMA
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer.
config SAMV7_QSPI_REGDEBUG
bool "QSPI Register level debug"
depends on DEBUG
default n
---help---
Output detailed register-level QSPI device debug information.
Requires also DEBUG.
endmenu # QSPI device driver options
menu "TWIHS device driver options"
depends on SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
@ -1264,7 +1375,6 @@ menu "USB High Speed Device Controller driver (DCD) options"
config SAMV7_USBDEVHS_LOWPOWER
bool "Low-power mode"
default n
depends on EXPERIMENTAL
---help---
The USBHS can work in two modes:
@ -1272,7 +1382,9 @@ config SAMV7_USBDEVHS_LOWPOWER
available.
- Low-power mode where only Full speed and Low speed are available.
This options selects the low-power mode.
This options selects the low-power mode. In order to use high speed
mode, this option must be disabled and USBDEV_DUALSPEED must be
enabled.
config SAMV7_USBHS_SCATTERGATHER
bool
@ -1311,7 +1423,7 @@ menu "MCAN device driver options"
choice
prompt "MCAN clock source (PCK5)"
default SAMV7_MCAN_CLKSRC_MAIN
default SAMV7_MCAN_CLKSRC_MCK
config SAMV7_MCAN_CLKSRC_SLOW
bool "Slow clock"
@ -1333,7 +1445,11 @@ endchoice # MCAN clock source
config SAMV7_MCAN_CLKSRC_PRESCALER
int "MCAN clock prescaler"
default 1
range 1 256
range 1 1024
---help---
The frequency associated with time quanta is derived by dividing
down the input frequency. This setting provides prescaler/divider
must lie the range of 1 to 1024.
menu "MCAN0 device driver options"
depends on SAMV7_MCAN0
@ -1447,6 +1563,7 @@ config SAMV7_MCAN0_NEXTFILTERS
int "MCAN0 number of extended filters"
default 8
range 0 64
depends on CAN_EXTID
---help---
Number of extended message ID filters.
@ -1489,8 +1606,8 @@ endchoice # MCAN0 RX buffer element size
config SAMV7_MCAN0_RXFIFO0_SIZE
int "MCAN0 RX FIFO0 size"
default 12
range 0 64
default 8
range 1 64
---help---
Number of receive FIFO 0 elements. Zero disables FIFO 0.
@ -1533,8 +1650,8 @@ endchoice # MCAN0 RX buffer element size
config SAMV7_MCAN0_RXFIFO1_SIZE
int "MCAN0 RX FIFO1 size"
default 0
range 0 64
default 4
range 1 64
---help---
Number of receive FIFO 1 elements for MCAN0. Zero disables FIFO 1.
@ -1635,7 +1752,7 @@ config SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE
config SAMV7_MCAN0_TXFIFOQ_SIZE
int "MCAN0 TX FIFO queue size"
default 4
range 0 32
range 1 32
---help---
Number of dedicated TX buffer elements for MCAN0.
@ -1643,6 +1760,7 @@ config SAMV7_MCAN0_TXEVENTFIFO_SIZE
int "MCAN0 TX event FIFO size"
default 0
range 0 32
depends on EXPERIMENTAL
---help---
Number of TX event FIFO elements for MCAN0. Zero disables TX event FIFO.
@ -1761,6 +1879,7 @@ config SAMV7_MCAN1_NEXTFILTERS
int "MCAN1 number of extended filters"
default 8
range 0 64
depends on CAN_EXTID
---help---
Number of extended message ID filters.
@ -1803,8 +1922,8 @@ endchoice # MCAN1 RX buffer element size
config SAMV7_MCAN1_RXFIFO0_SIZE
int "MCAN1 RX FIFO0 size"
default 0
range 0 64
default 8
range 1 64
---help---
Number of receive FIFO 0 elements. Zero disables FIFO 0.
@ -1847,8 +1966,8 @@ endchoice # MCAN1 RX buffer element size
config SAMV7_MCAN1_RXFIFO1_SIZE
int "MCAN1 RX FIFO1 size"
default 0
range 0 64
default 4
range 1 64
---help---
Number of receive FIFO 1 elements for MCAN1. Zero disables FIFO 1.
@ -1940,6 +2059,7 @@ config SAMV7_MCAN1_TXEVENTFIFO_SIZE
int "MCAN1 TX event FIFO size"
default 0
range 0 32
depends on EXPERIMENTAL
---help---
Number of TX event FIFO elements for MCAN1. Zero disables TX event FIFO.
@ -1954,9 +2074,9 @@ config SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE
NOTE: Dedicated TX buffers are not used in the current MCAN design.
config SAMV7_MCAN1_TXFIFOQ_SIZE
int "MCAN1 dedicated TX FIFO queue"
int "MCAN1 TX FIFO queue"
default 4
range 0 32
range 1 32
---help---
Number of dedicated TX buffer elements for MCAN1.
@ -1972,3 +2092,4 @@ config SAMV7_MCAN_REGDEBUG
endmenu # CAN device driver options
endif # SAMV7_MCAN
endif # ARCH_CHIP_SAMV7

14
arch/arm/src/samv7/Make.defs
View File

@ -77,6 +77,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
@ -124,12 +126,18 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y)
CHIP_CSRCS += sam_xdmac.c
endif
ifeq ($(CONFIG_SAMV7_SPI0),y)
CHIP_CSRCS += sam_spi.c
else ifeq ($(CONFIG_SAMV7_SPI1),y)
ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
CHIP_CSRCS += sam_spi.c
endif
ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y)
CHIP_CSRCS += sam_spi_slave.c
endif
ifeq ($(CONFIG_SAMV7_QSPI),y)
CHIP_CSRCS += sam_qspi.c
endif
ifeq ($(CONFIG_SAMV7_TWIHS0),y)
CHIP_CSRCS += sam_twihs.c
else ifeq ($(CONFIG_SAMV7_TWIHS1),y)

274
arch/arm/src/samv7/chip/sam_qspi.h Normal file
View File

@ -0,0 +1,274 @@
/****************************************************************************************
* arch/arm/src/samv7/chip/sam_qspi.h
* Quad SPI (QSPI) definitions for the SAMV71
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samv7/chip.h>
#include "chip/sam_memorymap.h"
#if SAMV7_NQSPI > 0
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General Characteristics **************************************************************/
#define SAM_QSPI_MINBITS 8 /* Minimum word width */
#define SAM_QSPI_MAXBITS 16 /* Maximum word width */
/* QSPI register offsets ****************************************************************/
#define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_QSPI_RDR_OFFSET 0x0008 /* Receive Data Register */
#define SAM_QSPI_TDR_OFFSET 0x000c /* Transmit Data Register */
#define SAM_QSPI_SR_OFFSET 0x0010 /* Status Register */
#define SAM_QSPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
#define SAM_QSPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
#define SAM_QSPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
#define SAM_QSPI_SCR_OFFSET 0x0020 /* Serial Clock Register */
#define SAM_QSPI_IAR_OFFSET 0x0030 /* Instruction Address Register */
#define SAM_QSPI_ICR_OFFSET 0x0034 /* Instruction Code Register */
#define SAM_QSPI_IFR_OFFSET 0x0038 /* Instruction Frame Register */
/* 0x003c Reserved */
#define SAM_QSPI_SMR_OFFSET 0x0040 /* Scrambling Mode Register */
#define SAM_QSPI_SKR_OFFSET 0x0044 /* Scrambling Key Register */
/* 0x0048–0x00e0 Reserved */
#define SAM_QSPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
#define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* 0xec-0xfc: Reserved */
/* QSPI register addresses **************************************************************/
#define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
#define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
#define SAM_QSPI0_RDR (SAM_QSPI0_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
#define SAM_QSPI0_TDR (SAM_QSPI0_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
#define SAM_QSPI0_SR (SAM_QSPI0_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
#define SAM_QSPI0_IER (SAM_QSPI0_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
#define SAM_QSPI0_IDR (SAM_QSPI0_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
#define SAM_QSPI0_IMR (SAM_QSPI0_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
#define SAM_QSPI0_SCR (SAM_QSPI0_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
#define SAM_QSPI0_IAR (SAM_QSPI0_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
#define SAM_QSPI0_ICR (SAM_QSPI0_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
#define SAM_QSPI0_IFR (SAM_QSPI0_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
#define SAM_QSPI0_SMR (SAM_QSPI0_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
#define SAM_QSPI0_SKR (SAM_QSPI0_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
#define SAM_QSPI0_WPCR (SAM_QSPI0_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
#define SAM_QSPI0_WPSR (SAM_QSPI0_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
#if SAMV7_NQSPI > 1
# define SAM_QSPI1_CR (SAM_QSPI1_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
# define SAM_QSPI1_MR (SAM_QSPI1_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
# define SAM_QSPI1_RDR (SAM_QSPI1_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
# define SAM_QSPI1_TDR (SAM_QSPI1_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
# define SAM_QSPI1_SR (SAM_QSPI1_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
# define SAM_QSPI1_IER (SAM_QSPI1_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
# define SAM_QSPI1_IDR (SAM_QSPI1_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
# define SAM_QSPI1_IMR (SAM_QSPI1_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
# define SAM_QSPI1_SCR (SAM_QSPI1_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
# define SAM_QSPI1_IAR (SAM_QSPI1_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
# define SAM_QSPI1_ICR (SAM_QSPI1_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
# define SAM_QSPI1_IFR (SAM_QSPI1_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
# define SAM_QSPI1_SMR (SAM_QSPI1_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
# define SAM_QSPI1_SKR (SAM_QSPI1_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
# define SAM_QSPI1_WPCR (SAM_QSPI1_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
# define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
#endif
/* QSPI register bit definitions ********************************************************/
/* QSPI Control Register */
#define QSPI_CR_QSPIEN (1 << 0) /* Bit 0: QSPI Enable */
#define QSPI_CR_QSPIDIS (1 << 1) /* Bit 1: QSPI Disable */
#define QSPI_CR_SWRST (1 << 7) /* Bit 7: QSPI Software Reset */
#define QSPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
/* QSPI Mode Register */
#define QSPI_MR_SMM (1 << 0) /* Bit 0: Serial Memory Mode */
#define QSPI_MR_LLB (1 << 1) /* Bit 1: Local Loopback Enable */
#define QSPI_MR_WDRBT (1 << 2) /* Bit 2: Wait Data Read Before Transfer */
#define QSPI_MR_CSMODE_SHIFT (4) /* Bits 4-5: Chip Select Mode */
#define QSPI_MR_CSMODE_MASK (3 << QSPI_MR_CSMODE_SHIFT)
# define QSPI_MR_CSMODE_NRELOAD (0 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted if TD not reloaded */
# define QSPI_MR_CSMODE_LASTXFER (1 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted when LASTXFER transferred */
# define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted after each transfer */
#define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */
#define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT)
# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT)
# define QSPI_MR_NBBITS_8BIT (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */
# define QSPI_MR_NBBITS_9BIT (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */
# define QSPI_MR_NBBITS_10BIT (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */
# define QSPI_MR_NBBITS_11BIT (3 << QSPI_MR_NBBITS_SHIFT) /* 11 bits for transfer */
# define QSPI_MR_NBBITS_12BIT (4 << QSPI_MR_NBBITS_SHIFT) /* 12 bits for transfer */
# define QSPI_MR_NBBITS_13BIT (5 << QSPI_MR_NBBITS_SHIFT) /* 13 bits for transfer */
# define QSPI_MR_NBBITS_14BIT (6 << QSPI_MR_NBBITS_SHIFT) /* 14 bits for transfer */
# define QSPI_MR_NBBITS_15BIT (7 << QSPI_MR_NBBITS_SHIFT) /* 15 bits for transfer */
# define QSPI_MR_NBBITS_16BIT (8 << QSPI_MR_NBBITS_SHIFT) /* 16 bits for transfer */
#define QSPI_MR_DLYBCT_SHIFT (16) /* Bits 16-23: Delay Between Consecutive Transfers */
#define QSPI_MR_DLYBCT_MASK (0xff << QSPI_MR_DLYBCT_SHIFT)
# define QSPI_MR_DLYBCT(n) ((uint32_t)(n) << QSPI_MR_DLYBCT_SHIFT)
#define QSPI_MR_DLYCS_SHIFT (24) /* Bits 24-31: Minimum Inactive QCS Delay */
#define QSPI_MR_DLYCS_MASK (0xff << QSPI_MR_DLYCS_SHIFT)
# define QSPI_MR_DLYCS(n) ((uint32_t)(n) << QSPI_MR_DLYCS_SHIFT)
/* QSPI Receive Data Register */
#define QSPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
#define QSPI_RDR_RD_MASK (0xffff << QSPI_RDR_RD_SHIFT)
/* QSPI Transmit Data Register */
#define QSPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
#define QSPI_TDR_TD_MASK (0xffff << QSPI_TDR_TD_SHIFT)
/* QSPI Status Register, QSPI Interrupt Enable Register, QSPI Interrupt Disable Register,
* and QSPI Interrupt Mask Register (common bit fields)
*/
#define QSPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
#define QSPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
#define QSPI_INT_TXEMPTY (1 << 2) /* Bit 2: Transmission Registers Empty Interrupt */
#define QSPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
#define QSPI_INT_CSR (1 << 8) /* Bit 8: Chip Select Rise Interrupt */
#define QSPI_SR_CSS (1 << 9) /* Bit 9: Chip Select Status Interrupt */
#define QSPI_SR_INSTRE (1 << 10) /* Bit 10: Instruction End Status Interrupt */
#define QSPI_SR_QSPIENS (1 << 24) /* Bit 24: QSPI Enable Status (SR only) */
#define QSPI_INT_ALL (0x0000070f)
/* Serial Clock Register */
#define QSPI_SCR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
#define QSPI_SCR_CPHA (1 << 1) /* Bit 1: Clock Phase */
#define QSPI_SCR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
#define QSPI_SCR_SCBR_MASK (0xff << QSPI_SCR_SCBR_SHIFT)
# define QSPI_SCR_SCBR(n) ((uint32_t)(n) << QSPI_SCR_SCBR_SHIFT)
#define QSPI_SCR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before QSCK */
#define QSPI_SCR_DLYBS_MASK (0xff << QSPI_SCR_DLYBS_SHIFT)
# define QSPI_SCR_DLYBS(n) ((uint32_t)(n) << QSPI_SCR_DLYBS_SHIFT)
/* Instruction Address Register (32-bit value) */
/* Instruction Code Register */
#define QSPI_ICR_INST_SHIFT (0) /* Bits 0-7: Instruction Code */
#define QSPI_ICR_INST_MASK (0xff << QSPI_ICR_INST_SHIFT)
# define QSPI_ICR_INST(n) ((uint32_t)(n) << QSPI_ICR_INST_SHIFT)
#define QSPI_ICR_OPT_SHIFT (16) /* Bits 16-23: Option Code */
#define QSPI_ICR_OPT_MASK (0xff << QSPI_ICR_OPT_SHIFT)
# define QSPI_ICR_OPT(n) ((uint32_t)(n) << QSPI_ICR_OPT_SHIFT)
/* Instruction Frame Register */
#define QSPI_IFR_WIDTH_SHIFT (0) /* Bits 0-2: Width of Instruction Code,
* Address, Option Code and Data */
#define QSPI_IFR_WIDTH_MASK (7 << QSPI_IFR_WIDTH_SHIFT)
/* Instruction Address-Option Data */
# define QSPI_IFR_WIDTH_SINGLE (0 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Single-bit */
# define QSPI_IFR_WIDTH_DUALOUT (1 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Dual */
# define QSPI_IFR_WIDTH_QUADOUT (2 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Quad */
# define QSPI_IFR_WIDTH_DUALIO (3 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Dual Dual */
# define QSPI_IFR_WIDTH_QUADIO (4 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Quad Quad */
# define QSPI_IFR_WIDTH_DUALCMD (5 << QSPI_IFR_WIDTH_SHIFT) /* Dual Dual Dual */
# define QSPI_IFR_WIDTH_QUADCMD (6 << QSPI_IFR_WIDTH_SHIFT) /* Quad Quad Quad */
#define QSPI_IFR_INSTEN (1 << 4) /* Bit 4: Instruction Enable */
#define QSPI_IFR_ADDREN (1 << 5) /* Bit 5: Address Enable */
#define QSPI_IFR_OPTEN (1 << 6) /* Bit 6: Option Enable */
#define QSPI_IFR_DATAEN (1 << 7) /* Bit 7: Data Enable */
#define QSPI_IFR_OPTL_SHIFT (8) /* Bits 8-9: Option Code Length */
#define QSPI_IFR_OPTL_MASK (3 << QSPI_IFR_OPTL_SHIFT)
# define QSPI_IFR_OPTL_1BIT (0 << QSPI_IFR_OPTL_SHIFT) /* Option is 1 bit */
# define QSPI_IFR_OPTL_2BIT (1 << QSPI_IFR_OPTL_SHIFT) /* Option is 2 bits */
# define QSPI_IFR_OPTL_4BIT (2 << QSPI_IFR_OPTL_SHIFT) /* Option is 4 bits */
# define QSPI_IFR_OPTL_8BIT (3 << QSPI_IFR_OPTL_SHIFT) /* Option is 8 bits */
#define QSPI_IFR_ADDRL (1 << 10) /* Bit 10: Address Length */
# define QSPI_IFR_ADDRL_24BIT (0 << 10) /* 0=24-bit */
# define QSPI_IFR_ADDRL_32BIT (1 << 10) /* 1=32-bit */
#define QSPI_IFR_TFRTYP_SHIFT (12) /* Bits 12-13: Data Transfer Type */
#define QSPI_IFR_TFRTYP_MASK (3 << QSPI_IFR_TFRTYP_SHIFT)
# define QSPI_IFR_TFRTYP_READ (0 << QSPI_IFR_TFRTYP_SHIFT) /* Read transfer from serial memory */
# define QSPI_IFR_TFRTYP_RDMEM (1 << QSPI_IFR_TFRTYP_SHIFT) /* Read data transfer from serial memory */
# define QSPI_IFR_TFRTYP_WRITE (2 << QSPI_IFR_TFRTYP_SHIFT) /* Write transfer into serial memory */
# define QSPI_IFR_TFRTYP_WRMEM (3 << QSPI_IFR_TFRTYP_SHIFT) /* Write data transfer the serial memory */
#define QSPI_IFR_CRM (1 << 14) /* Bit 14: Continuous Read Mode */
#define QSPI_IFR_NBDUM_SHIFT (16) /* Bits 16-20: Number Of Dummy Cycles */
#define QSPI_IFR_NBDUM_MASK (31 << QSPI_IFR_NBDUM_SHIFT)
# define QSPI_IFR_NBDUM(n) ((uint32_t)(n) << QSPI_IFR_NBDUM_SHIFT)
/* Scrambling Mode Register */
#define QSPI_SMR_SCREN (1 << 0) /* Bit 0: Scrambling/Unscrambling Enable */
#define QSPI_SMR_RVDIS (1 << 1) /* Bit 1: Scrambling/Unscrambling Random Value Disable */
/* Scrambling Key Register (32-bit value) */
/* QSPI Write Protection Control Register */
#define QSPI_WPCR_WPEN (1 << 0) /* Bit 0: QSPI Write Protection Enable */
#define QSPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: QSPI Write Protection Key Password */
#define QSPI_WPCR_WPKEY_MASK (0x00ffffff << QSPI_WPCR_WPKEY_SHIFT)
# define QSPI_WPCR_WPKEY (0x00515350 << QSPI_WPCR_WPKEY_SHIFT)
/* QSPI Write Protection Status Register */
#define QSPI_WPSR_WPVS (1 << 0) /* Bit 0: QSPI Write Protection Violation Status */
#define QSPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: QSPI Write Protection Violation Source */
#define QSPI_WPSR_WPVSRC_MASK (0xff << QSPI_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* SAMV7_NQSPI > 0 */
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H */

7
arch/arm/src/samv7/chip/sam_spi.h
View File

@ -120,7 +120,8 @@
/* SPI Mode Register */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: 1=Master Mode */
# define SPI_MR_SLAVE (0) /* 0=Slave Mode */
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
@ -170,7 +171,9 @@
#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
#define SPI_INT_ALL (0x0000070f)
/* SPI Chip Select Registers 0-3 */

3
arch/arm/src/samv7/chip/sam_usbhs.h
View File

@ -746,6 +746,9 @@
#define USBHS_CTRL_RDERRE (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Enable */
#define USBHS_CTRL_FRZCLK (1 << 14) /* Bit 14: Freeze USB Clock */
#define USBHS_CTRL_USBE (1 << 15) /* Bit 15: USBHS Enable */
#define USBHS_CTRL_UIDE (1 << 24) /* Bit 24: UOTGID Pin Enable */
# define USBHS_CTRL_UIDE_UIMOD (0 << 24) /* 0=USB mode selected UIMOD bit. */
# define USBHS_CTRL_UIDE_UOTGID (1 << 24) /* 1=USB mode selected by UOTGID */
#define USBHS_CTRL_UIMOD_MASK (1 << 25) /* Bit 25: USBHS Mode */
# define USBHS_CTRL_UIMOD_HOST (0 << 25) /* 0=Host mode */
# define USBHS_CTRL_UIMOD_DEVICE (1 << 25) /* 1=Device mode */

2
arch/arm/src/samv7/chip/samv71_memorymap.h
View File

@ -55,7 +55,7 @@
#define SAM_MEMORY_BASE 0x60000000 /* 0x60000000-0x7fffffff: Memories */
#define SAM_QSPIMEM_BASE 0x80000000 /* 0x80000000-0x9fffffff: QSPI memory */
#define SAM_AXIMX_BASE 0xa0000000 /* 0xa0000000-0x9fffffff: AXIMX */
#define SAM_USBHSRAM_BASE 0xa0010000 /* 0xa0100000-0xa01fffff: USBHS RAM */
#define SAM_USBHSRAM_BASE 0xa0100000 /* 0xa0100000-0xa01fffff: USBHS RAM */
/* 0xa0200000-0xdfffffff: Reserved */
#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */

2
arch/arm/src/samv7/chip/samv71_pinmap.h
View File

@ -399,6 +399,7 @@
#define GPIO_SPI0_MOSI (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN21)
#define GPIO_SPI0_SPCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN22)
#define GPIO_SPI0_NSS (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_SPI0_NPCS0 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN25)
@ -409,6 +410,7 @@
#define GPIO_SPI1_MOSI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27)
#define GPIO_SPI1_SPCK (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24)
#define GPIO_SPI1_NSS (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25)
#define GPIO_SPI1_NPCS0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25)
#define GPIO_SPI1_NPCS1_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28)
#define GPIO_SPI1_NPCS1_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN0)

76
arch/arm/src/samv7/sam_clockconfig.c
View File

@ -224,30 +224,27 @@ static inline void sam_pmcsetup(void)
putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
sam_pmcwait(PMC_INT_LOCKA);
#ifdef CONFIG_USBDEV
#ifdef CONFIG_SAMV7_USBDEVHS
/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
#if 0 /* REVISIT: Does this apply only to OHCI? */
putreg32(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
#endif
#if BOARD_MAINOSC_FREQUENCY == 12000000
putreg32(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
#elif BOARD_MAINOSC_FREQUENCY == 12000000
#elif BOARD_MAINOSC_FREQUENCY == 16000000
putreg32(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
#else
# error ERROR: Unrecognized MAINSOSC frequency
#endif
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
/* Enable UTMI Clocking. The USBHS can work in two modes:
*
* - Normal mode where High speed, Full speed and Low speed are available.
* - Low-power mode where only Full speed and Low speed are available.
*
* Only the normal mode is supported by this logic.
* Only the Low-power mode is mode is supported by the logic here. Normal
* mode logic is handled in the function sam_usbclock().
*/
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
/* UTMI Low-power mode, Full/Low Speed mode
*
* Enable the 48MHz FS Clock.
@ -255,15 +252,6 @@ static inline void sam_pmcsetup(void)
putreg32(PMC_USBCLK, SAM_PMC_SCER);
#else
/* UTMI normal mode, High/Full/Low Speed
*
* Disable the 48MHz USB FS Clock. It is not used in this configuration
*/
putreg32(PMC_USBCLK, SAM_PMC_SCDR);
#endif
/* Select the UTMI PLL as the USB PLL clock input (480MHz) with divider
* to get to 48MHz. UPLL output frequency is determined only by the
* 12/16MHz crystal selection above.
@ -271,7 +259,6 @@ static inline void sam_pmcsetup(void)
regval = PMC_USB_USBS_UPLL;
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
{
/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
@ -284,7 +271,6 @@ static inline void sam_pmcsetup(void)
regval |= PMC_USB_USBDIV(9);
}
#endif
putreg32(regval, SAM_PMC_USB);
@ -296,7 +282,9 @@ static inline void sam_pmcsetup(void)
/* Wait for LOCKU */
sam_pmcwait(PMC_INT_LOCKU);
#endif
#endif /* CONFIG_SAMV7_USBDEVHS_LOWPOWER */
#endif /* CONFIG_SAMV7_USBDEVHS */
/* Switch to the fast clock and wait for MCKRDY */
@ -405,3 +393,51 @@ void sam_clockconfig(void)
sam_enabledefaultmaster();
}
/****************************************************************************
* Name: sam_usbclock
*
* Description:
* Enable USBHS clocking.
*
****************************************************************************/
#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
void sam_usbclock(void)
{
uint32_t regval;
/* Enable UTMI Clocking. The USBHS can work in two modes:
*
* - Normal mode where High speed, Full speed and Low speed are available.
* - Low-power mode where only Full speed and Low speed are available.
*
* Only the normal mode is supported by this logic of this function. Low-
* power mode was handled in the sam_clockconfig().
*/
/* UTMI normal mode, High/Full/Low Speed
*
* Disable the 48MHz USB FS Clock. It is not used in this configuration
*/
putreg32(PMC_USBCLK, SAM_PMC_SCDR);
/* Select the UTMI PLL as the USB PLL clock input (480MHz) with a divider
* of 1. UPLL output frequency is determined only by the 12/16MHz crystal
* selection set in sam_clockconfig().
*/
putreg32(PMC_USB_USBS_UPLL, SAM_PMC_USB);
/* Enable the UTMI PLL with the maximum start-up time */
regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
putreg32(regval, SAM_PMC_CKGR_UCKR);
/* Wait for LOCKU */
sam_pmcwait(PMC_INT_LOCKU);
}
#endif /* CONFIG_SAMV7_USBDEVHS && !CONFIG_SAMV7_USBDEVHS_LOWPOWER */

14
arch/arm/src/samv7/sam_clockconfig.h
View File

@ -85,6 +85,20 @@ extern "C"
void sam_clockconfig(void);
/****************************************************************************
* Name: sam_usbclock
*
* Description:
* Enable USBHS clocking.
*
****************************************************************************/
#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
void sam_usbclock(void);
#else
# define sam_usbclock()
#endif
#undef EXTERN
#if defined(__cplusplus)
}

46
arch/arm/src/samv7/sam_config.h
View File

@ -255,22 +255,60 @@
/* SPI ******************************************************************************/
/* Don't enable SPI peripherals not supported by the chip. */
#if CHIP_NSPI < 1
#if SAMV7_NSPI < 1
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1
#elif CHIP_NSPI < 2
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#elif SAMV7_NSPI < 2
# undef CONFIG_SAMV7_SPI1
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
#ifndef CONFIG_SAMV7_HAVE_SPI
#ifndef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
/* Are any SPI peripherals enabled? */
#if !defined(CONFIG_SAMV7_SPI0) && !defined(CONFIG_SAMV7_SPI0)
# undef CONFIG_SAMV7_HAVE_SPI
# undef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI_MASTER
# undef CONFIG_SAMV7_SPI_SLAVE
#endif
/* Each SPI peripheral must be enabled as a MASTER or as a SLAVE */
#ifndef CONFIG_SAMV7_SPI_MASTER
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI1_MASTER
#endif
#if !defined(CONFIG_SAMV7_SPI0_MASTER) && !defined(CONFIG_SAMV7_SPI1_MASTER)
# undef CONFIG_SAMV7_SPI_MASTER
#endif
#ifndef CONFIG_SAMV7_SPI_SLAVE
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
#if !defined(CONFIG_SAMV7_SPI0_SLAVE) && !defined(CONFIG_SAMV7_SPI1_SLAVE)
# undef CONFIG_SAMV7_SPI_SLAVE
#endif
#if !defined(CONFIG_SAMV7_SPI_MASTER) && !defined(CONFIG_SAMV7_SPI_SLAVE)
# undef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI1
#endif
/****************************************************************************

31
arch/arm/src/samv7/sam_emac.c
View File

@ -527,9 +527,9 @@ struct sam_emac_s
struct work_s work; /* For deferring work to the work queue */
#endif
/* This holds the information visible to uIP/NuttX */
/* This holds the information visible to the NuttX network */
struct net_driver_s dev; /* Interface understood by uIP */
struct net_driver_s dev; /* Interface understood by the network */
/* Constant and configured attributes of the EMAC */
@ -1470,8 +1470,9 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if uIP has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -1551,7 +1552,7 @@ static int sam_txpoll(struct net_driver_s *dev)
* Function: sam_dopoll
*
* Description:
* Perform the uIP poll.
* Perform the network poll.
*
* Parameters:
* priv - Reference to the driver state structure
@ -1575,7 +1576,7 @@ static void sam_dopoll(struct sam_emac_s *priv, int qid)
if (sam_txfree(priv, qid) > 0)
{
/* If we have the descriptor, then poll uIP for new XMIT data. */
/* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@ -1876,8 +1877,8 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
/* Check if the packet is a valid size for the uIP buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
@ -2090,7 +2091,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
xfrq->txtail = tail;
/* Then poll uIP for new XMIT data */
/* Then poll the network for new XMIT data */
sam_dopoll(priv, qid);
}
@ -2103,7 +2104,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None
@ -2216,7 +2217,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
sam_putreg(priv, SAM_EMAC_IER_OFFSET, EMAC_RX_INTS);
/* Then poll uIP for new XMIT data */
/* Then poll the network for new XMIT data */
sam_dopoll(priv, qid);
}
@ -2230,7 +2231,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None
@ -2567,7 +2568,7 @@ static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
/* Then poll uIP for new XMIT data */
/* Then poll the network for new XMIT data */
sam_dopoll(priv, EMAC_QUEUE_0);
}
@ -2677,7 +2678,7 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv)
if (sam_txfree(priv, EMAC_QUEUE_0) > 0)
{
/* Update TCP timing states and poll uIP for new XMIT data. */
/* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll, SAM_POLLHSEC);
}
@ -2927,7 +2928,7 @@ static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
if (priv->ifup)
{
/* Poll uIP for new XMIT data */
/* Poll the network for new XMIT data */
sam_dopoll(priv, EMAC_QUEUE_0);
}

26
arch/arm/src/samv7/sam_irq.c
View File

@ -78,7 +78,16 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
@ -378,16 +387,21 @@ void up_irqinitialize(void)
}
#endif
/* Set up the vector table address.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */

534
arch/arm/src/samv7/sam_mcan.c Normal file → Executable file
View File

@ -122,6 +122,10 @@
# define MCAN_ALIGN ARMV7M_DCACHE_LINESIZE
# define MCAN_ALIGN_MASK (MCAN_ALIGN-1)
# define MCAN_ALIGN_UP(n) (((n) + MCAN_ALIGN_MASK) & ~MCAN_ALIGN_MASK)
# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
# warning !!! This driver will not work without CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y!!!
# endif
#endif
/* MCAN0 Configuration ******************************************************/
@ -809,6 +813,15 @@ enum sam_canmode_e
MCAN_FD_BSW_MODE = 2 /* CAN FD operation with bit rate switching */
};
/* CAN driver state */
enum can_state_s
{
MCAN_STATE_UNINIT = 0, /* Not yet initialized */
MCAN_STATE_RESET, /* Initialized, reset state */
MCAN_STATE_SETUP, /* can_setup() has been called */
};
/* This structure describes the MCAN message RAM layout */
struct sam_msgram_s
@ -869,22 +882,22 @@ struct sam_config_s
struct sam_mcan_s
{
const struct sam_config_s *config; /* The constant configuration */
bool initialized; /* True: Device has been initialized */
uint8_t state; /* See enum can_state_s */
#ifdef CONFIG_CAN_EXTID
uint8_t nextalloc; /* Number of allocated extended filters */
#else
uint8_t nstdalloc; /* Number of allocated standard filters */
uint8_t nextalloc; /* Number of allocated extended filters */
#endif
uint8_t nstdalloc; /* Number of allocated standard filters */
sem_t locksem; /* Enforces mutually exclusive access */
sem_t txfsem; /* Used to wait for TX FIFO availability */
uint32_t btp; /* Current bit timing */
uint32_t fbtp; /* Current fast bit timing */
uint32_t rxints; /* Configured RX interrupts */
uint32_t txints; /* Configured TX interrupts */
#ifdef CONFIG_CAN_EXTID
uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */
#else
uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */
#endif
uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */
#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
uintptr_t regaddr; /* Last register address read */
@ -914,7 +927,7 @@ static void mcan_dev_lock(FAR struct sam_mcan_s *priv);
#define mcan_dev_unlock(priv) sem_post(&priv->locksem)
static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv);
#define mcan_buffer_release(priv) sem_post(&priv->txfsem)
static void mcan_buffer_release(FAR struct sam_mcan_s *priv);
/* MCAN helpers */
@ -925,13 +938,13 @@ static uint8_t mcan_bytes2dlc(FAR struct sam_mcan_s *priv, uint8_t nbytes);
#ifdef CONFIG_CAN_EXTID
static int mcan_add_extfilter(FAR struct sam_mcan_s *priv,
FAR struct canioc_stdfilter_s *extconfig);
FAR struct canioc_extfilter_s *extconfig);
static int mcan_del_extfilter(FAR struct sam_mcan_s *priv, int ndx);
#else
#endif
static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv,
FAR struct canioc_stdfilter_s *stdconfig);
static int mcan_del_stdfilter(FAR struct sam_mcan_s *priv, int ndx);
#endif
/* CAN driver methods */
static void mcan_reset(FAR struct can_dev_s *dev);
@ -952,6 +965,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev);
static bool mcan_dedicated_rxbuffer_available(FAR struct sam_mcan_s *priv,
int bufndx);
#endif
static void mcan_error(FAR struct can_dev_s *dev, uint32_t status);
static void mcan_receive(FAR struct can_dev_s *dev,
FAR uint32_t *rxbuffer, unsigned long nwords);
static void mcan_interrupt(FAR struct can_dev_s *dev);
@ -1385,8 +1399,9 @@ static void mcan_dev_lock(FAR struct sam_mcan_s *priv)
* Name: mcan_buffer_reserve
*
* Description:
* Take the semaphore that indicates the availability of a TX FIFOQ
* buffer, handling any exceptional conditions
* Take the semaphore, decrementing the semaphore count to indicate that
* one fewer TX FIFOQ buffer is available. Handles any exceptional
* conditions.
*
* Input Parameters:
* priv - A reference to the MCAN peripheral state
@ -1394,10 +1409,19 @@ static void mcan_dev_lock(FAR struct sam_mcan_s *priv)
* Returned Value:
* None
*
* Assumptions:
* Called only non-interrupt logic via mcan_write(). We do not have
* exclusive access to the MCAN hardware and interrupts are not disabled.
* mcan_write() does lock the scheduler for reasons noted below.
*
****************************************************************************/
static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
{
irqstate_t flags;
uint32_t txfqs1;
uint32_t txfqs2;
int sval;
int ret;
/* Wait until we successfully get the semaphore. EINTR is the only
@ -1407,12 +1431,147 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
do
{
/* We take some extra precautions here because it is possible that on
* certain error conditions, the semaphore count could get out of
* phase with the actual count of elements in the TX FIFO (I have
* never seen this happen, however. My paranoia).
*
* An missed TX interrupt could cause the semaphore count to fail to
* be incremented and, hence, to be too low.
*/
for(;;)
{
/* Get the current queue status and semaphore count. */
flags = irqsave();
txfqs1 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
(void)sem_getvalue(&priv->txfsem, &sval);
txfqs2 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
/* If the semaphore count and the TXFQS samples are in
* sync, then break out of the look with interrupts
* disabled.
*/
if (txfqs1 == txfqs2)
{
break;
}
/* Otherwise, re-enable interrupts to interrupts that may
* resynchronize, the semaphore count and try again.
*/
irqrestore(flags);
}
/* We only have one useful bit of information in the TXFQS:
* Is the TX FIFOQ full or not? We can only do limited checks
* with that single bit of information.
*/
if ((txfqs1 & MCAN_TXFQS_TFQF) != 0)
{
/* The TX FIFOQ is full. The semaphore count should then be
* less than or equal to zero. If it is greater than zero,
* then reinitialize it to 0.
*/
if (sval > 0)
{
candbg("ERROR: TX FIFOQ full but txfsem is %d\n", sval);
sem_init(&priv->txfsem, 0, 0);
}
}
/* The FIFO is not full so the semaphore count should be greater
* than zero. If it is not, then we have missed a call to
* mcan_buffer_release(0).
*
* NOTE: Since there is no mutual exclusion, it might be possible
* that mcan_write() could be re-entered AFTER taking the semaphore
* and dropping the count to zero, but BEFORE adding the message
* to the TX FIFOQ. That corner case is handled in mcan_write() by
* locking the scheduler.
*/
else if (sval <= 0)
{
candbg("ERROR: TX FIFOQ not full but txfsem is %d\n", sval);
/* Less than zero means that another thread is waiting */
if (sval < 0)
{
/* Bump up the count by one and try again */
sem_post(&priv->txfsem);
irqrestore(flags);
continue;
}
/* Exactly zero but the FIFO is not full. Just return without
* decrementing the count.
*/
irqrestore(flags);
return;
}
/* The semaphore value is reasonable. Wait for the next TC interrupt. */
ret = sem_wait(&priv->txfsem);
irqrestore(flags);
DEBUGASSERT(ret == 0 || errno == EINTR);
}
while (ret < 0);
}
/****************************************************************************
* Name: mcan_buffer_release
*
* Description:
* Release the semaphore, increment the semaphore count to indicate that
* one more TX FIFOQ buffer is available.
*
* Input Parameters:
* priv - A reference to the MCAN peripheral state
*
* Returned Value:
* None
*
* Assumptions:
* This function is called only from the interrupt level in response to the
* complete of a transmission.
*
****************************************************************************/
static void mcan_buffer_release(FAR struct sam_mcan_s *priv)
{
int sval;
/* We take some extra precautions here because it is possible that on
* certain error conditions, the semaphore count could get out of phase
* with the actual count of elements in the TX FIFO (I have never seen
* this happen, however. My paranoia).
*
* An extra TC interrupt could cause the count to be incremented too
* many times.
*/
(void)sem_getvalue(&priv->txfsem, &sval);
if (sval < priv->config->ntxfifoq)
{
sem_post(&priv->txfsem);
}
else
{
candbg("ERROR: txfsem would increment beyond %d\n",
priv->config->ntxfifoq);
}
}
/****************************************************************************
* Name: mcan_dlc2bytes
*
@ -1554,7 +1713,7 @@ static uint8_t mcan_bytes2dlc(FAR struct sam_mcan_s *priv, uint8_t nbytes)
#ifdef CONFIG_CAN_EXTID
static int mcan_add_extfilter(FAR struct sam_mcan_s *priv,
FAR struct canioc_stdfilter_s *extconfig)
FAR struct canioc_extfilter_s *extconfig)
{
FAR const struct sam_config_s *config;
FAR uint32_t *extfilter;
@ -1745,7 +1904,6 @@ static int mcan_del_extfilter(FAR struct sam_mcan_s *priv, int ndx)
*
****************************************************************************/
#ifndef CONFIG_CAN_EXTID
static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv,
FAR struct canioc_stdfilter_s *stdconfig)
{
@ -1846,7 +2004,6 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv,
mcan_dev_unlock(priv);
return -EAGAIN;
}
#endif
/****************************************************************************
* Name: mcan_del_stdfilter
@ -1864,7 +2021,6 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv,
*
****************************************************************************/
#ifndef CONFIG_CAN_EXTID
static int mcan_del_stdfilter(FAR struct sam_mcan_s *priv, int ndx)
{
FAR const struct sam_config_s *config;
@ -1915,7 +2071,6 @@ static int mcan_del_stdfilter(FAR struct sam_mcan_s *priv, int ndx)
mcan_dev_unlock(priv);
return OK;
}
#endif
/****************************************************************************
* Name: mcan_reset
@ -1955,9 +2110,19 @@ static void mcan_reset(FAR struct can_dev_s *dev)
mcan_putreg(priv, SAM_MCAN_IE_OFFSET, 0);
mcan_putreg(priv, SAM_MCAN_TXBTIE_OFFSET, 0);
/* Make sure that all buffers are released.
*
* REVISIT: What if a thread is waiting for a buffer? The following
* will not wake up any waiting threads.
*/
sem_destroy(&priv->txfsem);
sem_init(&priv->txfsem, 0, config->ntxfifoq);
/* Disable peripheral clocking to the MCAN controller */
sam_disableperiph1(priv->config->pid);
priv->state = MCAN_STATE_RESET;
mcan_dev_unlock(priv);
}
@ -2027,6 +2192,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
/* Enable receive interrupts */
priv->state = MCAN_STATE_SETUP;
mcan_rxint(dev, true);
mcan_dumpregs(priv, "After receive setup");
@ -2072,19 +2238,24 @@ static void mcan_shutdown(FAR struct can_dev_s *dev)
mcan_dev_lock(priv);
/* Disable the MCAN interrupts */
/* Disable MCAN interrupts at the NVIC */
up_disable_irq(config->irq0);
up_disable_irq(config->irq1);
/* Disable all interrupts from the MCAN peripheral */
mcan_putreg(priv, SAM_MCAN_IE_OFFSET, 0);
mcan_putreg(priv, SAM_MCAN_TXBTIE_OFFSET, 0);
/* Detach the MCAN interrupt handler */
irq_detach(config->irq0);
irq_detach(config->irq1);
/* And reset the hardware */
/* Disable peripheral clocking to the MCAN controller */
mcan_reset(dev);
sam_disableperiph1(priv->config->pid);
mcan_dev_unlock(priv);
}
@ -2200,6 +2371,125 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
switch (cmd)
{
/* CANIOC_GET_BITTIMING:
* Description: Return the current bit timing settings
* Argument: A pointer to a write-able instance of struct
* canioc_bittiming_s in which current bit timing values
* will be returned.
* Returned Value: Zero (OK) is returned on success. Otherwise -1 (ERROR)
* is returned with the errno variable set to indicate the
* nature of the error.
* Dependencies: None
*/
case CANIOC_GET_BITTIMING:
{
FAR struct canioc_bittiming_s *bt =
(FAR struct canioc_bittiming_s *)arg;
uint32_t regval;
uint32_t brp;
DEBUGASSERT(bt != NULL);
regval = mcan_getreg(priv, SAM_MCAN_BTP_OFFSET);
bt->bt_sjw = ((regval & MCAN_BTP_SJW_MASK) >> MCAN_BTP_SJW_SHIFT) + 1;
bt->bt_tseg1 = ((regval & MCAN_BTP_TSEG1_MASK) >> MCAN_BTP_TSEG1_SHIFT) + 1;
bt->bt_tseg2 = ((regval & MCAN_BTP_TSEG2_MASK) >> MCAN_BTP_TSEG2_SHIFT) + 1;
brp = ((regval & MCAN_BTP_BRP_MASK) >> MCAN_BTP_BRP_SHIFT) + 1;
bt->bt_baud = SAMV7_MCANCLK_FREQUENCY / brp /
(bt->bt_tseg1 + bt->bt_tseg2 + 1);
ret = OK;
}
break;
/* CANIOC_SET_BITTIMING:
* Description: Set new current bit timing values
* Argument: A pointer to a read-able instance of struct
* canioc_bittiming_s in which the new bit timing values
* are provided.
* Returned Value: Zero (OK) is returned on success. Otherwise -1 (ERROR)
* is returned with the errno variable set to indicate the
* nature of the error.
* Dependencies: None
*
* REVISIT: There is probably a limitation here: If there are multiple
* threads trying to send CAN packets, when one of these threads reconfigures
* the bitrate, the MCAN hardware will be reset and the context of operation
* will be lost. Hence, this IOCTL can only safely be executed in quiescent
* time periods.
*/
case CANIOC_SET_BITTIMING:
{
FAR const struct canioc_bittiming_s *bt =
(FAR const struct canioc_bittiming_s *)arg;
irqstate_t flags;
uint32_t brp;
uint32_t tseg1;
uint32_t tseg2;
uint32_t sjw;
uint32_t ie;
uint8_t state;
DEBUGASSERT(bt != NULL);
DEBUGASSERT(bt->bt_baud < SAMV7_MCANCLK_FREQUENCY);
DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16);
DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16);
DEBUGASSERT(bt->bt_tseg2 > 1 && bt->bt_tseg2 <= 64);
/* Extract bit timing data */
tseg1 = bt->bt_tseg1 - 1;
tseg2 = bt->bt_tseg2 - 1;
sjw = bt->bt_sjw - 1;
brp = (uint32_t)
(((float) SAMV7_MCANCLK_FREQUENCY /
((float)(tseg1 + tseg2 + 3) * (float)bt->bt_baud)) - 1);
/* Save the value of the new bit timing register */
flags = irqsave();
priv->btp = MCAN_BTP_BRP(brp) | MCAN_BTP_TSEG1(tseg1) |
MCAN_BTP_TSEG2(tseg2) | MCAN_BTP_SJW(sjw);
/* We need to reset to instantiate the new timing. Save
* current state information so that recover to this
* state.
*/
ie = mcan_getreg(priv, SAM_MCAN_IE_OFFSET);
state = priv->state;
/* Reset the MCAN */
mcan_reset(dev);
ret = OK;
/* If we have previously been setup, then setup again */
if (state == MCAN_STATE_SETUP)
{
ret = mcan_setup(dev);
}
/* We we have successfully re-initialized, then restore the
* interrupt state.
*
* REVISIT: Since the hardware was reset, any pending TX
* activity was lost. Should we disable TX interrupts?
*/
if (ret == OK)
{
mcan_putreg(priv, SAM_MCAN_IE_OFFSET, ie & ~priv->txints);
}
irqrestore(flags);
}
break;
#ifdef CONFIG_CAN_EXTID
/* CANIOC_ADD_EXTFILTER:
* Description: Add an address filter for a extended 29 bit
@ -2232,8 +2522,8 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
ret = mcan_del_extfilter(priv, (int)arg);
}
break;
#endif
#else
/* CANIOC_ADD_STDFILTER:
* Description: Add an address filter for a standard 11 bit
* address.
@ -2265,7 +2555,6 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
ret = mcan_del_stdfilter(priv, (int)arg);
}
break;
#endif
/* Unsupported/unrecognized command */
@ -2357,15 +2646,22 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
* not full and cannot become full at least until we add our packet to
* the FIFO.
*
* We can't get exclusive access to MAN resource here because that
* lock the MCAN while we wait for a free buffer. Instead, the
* scheduler is locked here momentarily. See discussion in
* mcan_buffer_reserve() for an explanation.
*
* REVISIT: This needs to be extended in order to handler case where
* the MCAN device was opened O_NONBLOCK.
*/
sched_lock();
mcan_buffer_reserve(priv);
/* Get exclusive access to the MCAN peripheral */
mcan_dev_lock(priv);
sched_unlock();
/* Get our reserved Tx FIFO/queue put index */
@ -2387,15 +2683,19 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
*/
#ifdef CONFIG_CAN_EXTID
DEBUGASSERT(msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID);
if (msg->cm_hdr.ch_extid)
{
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID);
regval = BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD;
#else
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID);
regval = BUFFER_R0_STDID(msg->cm_hdr.ch_id);
regval = BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD;
}
else
#endif
{
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID);
regval = BUFFER_R0_STDID(msg->cm_hdr.ch_id);
}
if (msg->cm_hdr.ch_rtr)
{
@ -2443,6 +2743,17 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
mcan_putreg(priv, SAM_MCAN_TXBAR_OFFSET, (1 << ndx));
/* Report that the TX transfer is complete to the upper half logic. Of
* course, the transfer is not complete, but this early notification
* allows the upper half logic to free resources sooner.
*
* REVISTI: Should we disable interrupts? can_txdone() was designed to
* be called from and interrupt handler and, hence, may be unsafe when
* called from the tasking level.
*/
can_txdone(dev);
mcan_dev_unlock(priv);
return OK;
}
@ -2591,6 +2902,108 @@ bool mcan_dedicated_rxbuffer_available(FAR struct sam_mcan_s *priv, int bufndx)
}
#endif
/****************************************************************************
* Name: mcan_error
*
* Description:
* Report a CAN error
*
* Input Parameters:
* dev - CAN-common state data
* status - Interrupt status with error bits set
*
* Returned Value:
* None
*
****************************************************************************/
static void mcan_error(FAR struct can_dev_s *dev, uint32_t status)
{
struct can_hdr_s hdr;
uint16_t errbits;
int ret;
/* Encode error bits */
errbits = 0;
if ((status & (MCAN_INT_ELO | MCAN_INT_EW)) != 0)
{
errbits |= CAN_ERROR_SYSTEM;
}
if ((status & (MCAN_INT_RF0L | MCAN_INT_RF1L)) != 0)
{
errbits |= CAN_ERROR_RXLOST;
}
if ((status & MCAN_INT_TEFL) != 0)
{
errbits |= CAN_ERROR_TXLOST;
}
if ((status & (MCAN_INT_MRAF | MCAN_INT_BO)) != 0)
{
errbits |= CAN_ERROR_ACCESS;
}
if ((status & MCAN_INT_TOO) != 0)
{
errbits |= CAN_ERROR_TIMEOUT;
}
if ((status & MCAN_INT_EP) != 0)
{
errbits |= CAN_ERROR_PASSIVE;
}
if ((status & MCAN_INT_CRCE) != 0)
{
errbits |= CAN_ERROR_CRC;
}
if ((status & MCAN_INT_BE) != 0)
{
errbits |= CAN_ERROR_BIT;
}
if ((status & MCAN_INT_ACKE) != 0)
{
errbits |= CAN_ERROR_ACK;
}
if ((status & MCAN_INT_FOE) != 0)
{
errbits |= CAN_ERROR_FORMAT;
}
if ((status & MCAN_INT_STE) != 0)
{
errbits |= CAN_ERROR_STUFF;
}
if (errbits != 0)
{
/* Format the CAN header for the error report. */
hdr.ch_id = errbits;
hdr.ch_dlc = 0;
hdr.ch_rtr = 0;
hdr.ch_error = 1;
#ifdef CONFIG_CAN_EXTID
hdr.ch_extid = 0;
#endif
hdr.ch_unused = 0;
/* And provide the error report to the upper half logic */
ret = can_receive(dev, &hdr, NULL);
if (ret < 0)
{
canlldbg("ERROR: can_receive failed: %d\n", ret);
}
}
}
/****************************************************************************
* Name: mcan_receive
*
@ -2627,9 +3040,10 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
canregdbg("R0: %08x\n", regval);
hdr.ch_rtr = 0;
#ifdef CONFIG_CAN_EXTID
hdr.ch_error = 0;
hdr.ch_unused = 0;
#ifdef CONFIG_CAN_EXTID
if ((regval & BUFFER_R0_XTD) != 0)
{
/* Save the extended ID of the newly received message */
@ -2696,9 +3110,6 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
uint32_t regval;
unsigned int nelem;
unsigned int ndx;
#ifdef CONFIG_DEBUG
int sval;
#endif
bool handled;
DEBUGASSERT(priv && priv->config);
@ -2725,6 +3136,10 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
/* Clear the error indications */
mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_CMNERR_INTS);
/* Report errors */
mcan_error(dev, pending & MCAN_CMNERR_INTS);
handled = true;
}
@ -2738,13 +3153,22 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_TXERR_INTS);
/* Report errors */
mcan_error(dev, pending & MCAN_TXERR_INTS);
/* REVISIT: Will MCAN_INT_TC also be set in the event of
* a transmission error? Each write must conclude with a
* call to can_txdone(), whether or not the write was
* successful.
* call to man_buffer_release(), whether or not the write
* was successful.
*
* Here we force transmit complete processing just in case.
* This could have the side effect of pushing the semaphore
* count up to high.
*/
handled = true;
pending |= MCAN_INT_TC;
handled = true;
}
/* Check for successful completion of a transmission */
@ -2765,15 +3189,6 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
*/
mcan_buffer_release(priv);
#ifdef CONFIG_DEBUG
(void)sem_getvalue(&priv->txfsem, &sval);
DEBUGASSERT(sval <= config->ntxfifoq);
#endif
/* Report that the TX transfer is complete to the upper half logic */
can_txdone(dev);
handled = true;
}
else if ((pending & priv->txints) != 0)
@ -2840,6 +3255,11 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
/* Clear the error indications */
mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_RXERR_INTS);
/* Report errors */
mcan_error(dev, pending & MCAN_TXERR_INTS);
handled = true;
}
/* Clear the RX FIFO1 new message interrupt */
@ -2871,7 +3291,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
/* Handle the newly received message in FIFO1 */
ndx = (regval & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT;
ndx = (regval & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT;
if ((regval & MCAN_RXF0S_RF0L) != 0)
{
@ -3066,8 +3486,8 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
/* Configure MCAN bit timing */
mcan_putreg(priv, SAM_MCAN_BTP_OFFSET, config->btp);
mcan_putreg(priv, SAM_MCAN_FBTP_OFFSET, config->fbtp);
mcan_putreg(priv, SAM_MCAN_BTP_OFFSET, priv->btp);
mcan_putreg(priv, SAM_MCAN_FBTP_OFFSET, priv->fbtp);
/* Configure message RAM starting addresses and sizes. */
@ -3335,19 +3755,27 @@ FAR struct can_dev_s *sam_mcan_initialize(int port)
/* Is this the first time that we have handed out this device? */
if (!priv->initialized)
if (priv->state == MCAN_STATE_UNINIT)
{
/* Yes, then perform one time data initialization */
memset(priv, 0, sizeof(struct sam_mcan_s));
priv->config = config;
priv->initialized = true;
priv->config = config;
/* Set the initial bit timing. This might change subsequently
* due to IOCTL command processing.
*/
priv->btp = config->btp;
priv->fbtp = config->fbtp;
/* Initialize semaphores */
sem_init(&priv->locksem, 0, 1);
sem_init(&priv->txfsem, 0, config->ntxfifoq);
dev->cd_ops = &g_mcanops;
dev->cd_priv = (FAR void *)priv;
dev->cd_ops = &g_mcanops;
dev->cd_priv = (FAR void *)priv;
/* And put the hardware in the initial state */

1739
arch/arm/src/samv7/sam_qspi.c Normal file
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File diff suppressed because it is too large Load Diff

108
arch/arm/src/samv7/sam_qspi.h Normal file
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@ -0,0 +1,108 @@
/****************************************************************************
* arch/arm/src/samv7/sam_qspi.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H
#define __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
#include "sam_config.h"
#ifdef CONFIG_SAMV7_QSPI
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_qspi_initialize
*
* Description:
* Initialize the selected QSPI port in master mode
*
* Input Parameter:
* intf - Interface number(must be zero)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct qspi_dev_s;
FAR struct qspi_dev_s *sam_qspi_initialize(int intf);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_SAMV7_QSPI */
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H */

50
arch/arm/src/samv7/sam_spi.c
View File

@ -69,7 +69,7 @@
#include "chip/sam_spi.h"
#include "chip/sam_pinmap.h"
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
#ifdef CONFIG_SAMV7_SPI_MASTER
/****************************************************************************
* Pre-processor Definitions
@ -86,13 +86,13 @@
#ifdef CONFIG_SAMV7_SPI_DMA
# if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_DMAC0)
# if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_DMAC0)
# define SAMV7_SPI0_DMA true
# else
# define SAMV7_SPI0_DMA false
# endif
# if defined(CONFIG_SAMV7_SPI1) && defined(CONFIG_SAMV7_DMAC1)
# if defined(CONFIG_SAMV7_SPI1_MASTER) && defined(CONFIG_SAMV7_DMAC1)
# define SAMV7_SPI1_DMA true
# else
# define SAMV7_SPI1_DMA false
@ -118,7 +118,7 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Debug *******************************************************************/
/* Check if SPI debut is enabled (non-standard.. no support in
/* Check if SPI debug is enabled (non-standard.. no support in
* include/debug.h
*/
@ -170,7 +170,7 @@ struct sam_spics_s
#endif
uint8_t nbits; /* Width of word in bits (8 to 16) */
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) || defined(CONFIG_SAMV7_SPI1_MASTER)
uint8_t spino; /* SPI controller number (0 or 1) */
#endif
uint8_t cs; /* Chip select number */
@ -196,7 +196,7 @@ struct sam_spics_s
typedef void (*select_t)(enum spi_dev_e devid, bool selected);
/* Chip select register offsetrs */
/* Chip select register offsets */
/* The overall state of one SPI controller */
@ -273,7 +273,7 @@ static inline uintptr_t spi_regaddr(struct sam_spics_s *spics,
unsigned int offset);
#endif
/* SPI methods */
/* SPI master methods */
#ifndef CONFIG_SPI_OWNBUS
static int spi_lock(struct spi_dev_s *dev, bool lock);
@ -309,7 +309,7 @@ static const uint8_t g_csroffset[4] =
SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR3_OFFSET
};
#ifdef CONFIG_SAMV7_SPI0
#ifdef CONFIG_SAMV7_SPI0_MASTER
/* SPI0 driver operations */
static const struct spi_ops_s g_spi0ops =
@ -348,7 +348,7 @@ static struct sam_spidev_s g_spi0dev =
};
#endif
#ifdef CONFIG_SAMV7_SPI1
#ifdef CONFIG_SAMV7_SPI1_MASTER
/* SPI1 driver operations */
static const struct spi_ops_s g_spi1ops =
@ -541,9 +541,9 @@ static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics)
{
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
return spics->spino ? &g_spi1dev : &g_spi0dev;
#elif defined(CONFIG_SAMV7_SPI0)
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
return &g_spi0dev;
#else
return &g_spi1dev;
@ -1726,7 +1726,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
* Name: up_spiinitialize
*
* Description:
* Initialize the selected SPI port
* Initialize the selected SPI port in master mode
*
* Input Parameter:
* cs - Chip select number (identifying the "logical" SPI port)
@ -1736,10 +1736,10 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
*
****************************************************************************/
struct spi_dev_s *up_spiinitialize(int port)
FAR struct spi_dev_s *up_spiinitialize(int port)
{
struct sam_spidev_s *spi;
struct sam_spics_s *spics;
FAR struct sam_spidev_s *spi;
FAR struct sam_spics_s *spics;
int csno = (port & __SPI_CS_MASK) >> __SPI_CS_SHIFT;
int spino = (port & __SPI_SPI_MASK) >> __SPI_SPI_SHIFT;
irqstate_t flags;
@ -1753,9 +1753,9 @@ struct spi_dev_s *up_spiinitialize(int port)
spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
DEBUGASSERT(spino >= 0 && spino <= 1);
#elif defined(CONFIG_SAMV7_SPI0)
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
DEBUGASSERT(spino == 0);
#else
DEBUGASSERT(spino == 1);
@ -1812,9 +1812,9 @@ struct spi_dev_s *up_spiinitialize(int port)
/* Select the SPI operations */
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops;
#elif defined(CONFIG_SAMV7_SPI0)
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
spics->spidev.ops = &g_spi0ops;
#else
spics->spidev.ops = &g_spi1ops;
@ -1823,7 +1823,7 @@ struct spi_dev_s *up_spiinitialize(int port)
/* Save the chip select and SPI controller numbers */
spics->cs = csno;
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) || defined(CONFIG_SAMV7_SPI1_MASTER)
spics->spino = spino;
#endif
@ -1838,10 +1838,10 @@ struct spi_dev_s *up_spiinitialize(int port)
/* Enable clocking to the SPI block */
flags = irqsave();
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
if (spino == 0)
#endif
#if defined(CONFIG_SAMV7_SPI0)
#if defined(CONFIG_SAMV7_SPI0_MASTER)
{
sam_spi0_enableclk();
@ -1854,10 +1854,10 @@ struct spi_dev_s *up_spiinitialize(int port)
sam_configgpio(GPIO_SPI0_SPCK);
}
#endif
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
else
#endif
#if defined(CONFIG_SAMV7_SPI1)
#if defined(CONFIG_SAMV7_SPI1_MASTER)
{
sam_spi1_enableclk();
@ -1938,4 +1938,4 @@ struct spi_dev_s *up_spiinitialize(int port)
return &spics->spidev;
}
#endif /* CONFIG_SAMV7_SPI0 || CONFIG_SAMV7_SPI1 */
#endif /* CONFIG_SAMV7_SPI_MASTER */

59
arch/arm/src/samv7/sam_spi.h
View File

@ -46,6 +46,9 @@
#include <stdbool.h>
#include "chip.h"
#include "sam_config.h"
#ifdef CONFIG_SAMV7_SPI
/****************************************************************************
* Pre-processor Definitions
@ -108,6 +111,43 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_spiinitialize
*
* Description:
* Initialize the selected SPI port in master mode
*
* Input Parameter:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
#if 0 /* Prototyped in include/nuttx/spi/spi.h */
FAR struct spi_dev_s *up_spiinitialize(int port)
#endif
/****************************************************************************
* Name: up_spi_slave_initialize
*
* Description:
* Initialize the selected SPI port in slave mode.
*
* Input Parameter:
* port - Chip select number identifying the "logical" SPI port. Includes
* encoded port and chip select information.
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
#if 0 /* Prototyped in include/nuttx/spi/slave.h */
FAR struct spi_sctrlr_s *up_spi_slave_initialize(int port);
#endif
/****************************************************************************
* Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
*
@ -115,7 +155,7 @@ extern "C"
* These external functions must be provided by board-specific logic.
* They include:
*
* o sam_spi[0|1]select is a functions tomanage the board-specific chip
* o sam_spi[0|1]select is a functions to manage the board-specific chip
* selects
* o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the
* status and cmddata methods of the SPI interface defined by struct
@ -142,9 +182,8 @@ extern "C"
*
****************************************************************************/
#ifdef CONFIG_SAMV7_SPI0
struct spi_dev_s;
enum spi_dev_e;
struct spi_dev_s; /* Forward reference */
enum spi_dev_e; /* Forward reference */
/****************************************************************************
* Name: sam_spi[0|1]select
@ -172,10 +211,10 @@ enum spi_dev_e;
*
****************************************************************************/
#ifdef CONFIG_SAMV7_SPI0
#ifdef CONFIG_SAMV7_SPI0_MASTER
void sam_spi0select(enum spi_dev_e devid, bool selected);
#endif
#ifdef CONFIG_SAMV7_SPI1
#ifdef CONFIG_SAMV7_SPI1_MASTER
void sam_spi1select(enum spi_dev_e devid, bool selected);
#endif
@ -226,14 +265,13 @@ uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_SAMV7_SPI0
#ifdef CONFIG_SAMV7_SPI0_MASTER
int sam_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_SAMV7_SPI1
#ifdef CONFIG_SAMV7_SPI1_MASTER
int sam_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#endif /* CONFIG_SAMV7_SPI0 */
#endif /* CONFIG_SPI_CMDDATA */
#undef EXTERN
#if defined(__cplusplus)
@ -241,4 +279,5 @@ int sam_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_SAMV7_SPI */
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SPI_H */

1286
arch/arm/src/samv7/sam_spi_slave.c Normal file
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File diff suppressed because it is too large Load Diff

716
arch/arm/src/samv7/sam_usbdevhs.c
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File diff suppressed because it is too large Load Diff

4
arch/arm/src/samv7/sam_xdmac.h
View File

@ -101,7 +101,9 @@
# define DMACH_FLAG_PERIPHPID(n) ((uint32_t)(n) << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID_MAX DMACH_FLAG_PERIPHPID_MASK
#define DMACH_FLAG_PERIPHH2SEL (0) /* No HW handshaking */
#define DMACH_FLAG_PERIPHISPERIPH (1 << 7) /* Bit 7: 0=memory; 1=peripheral */
#define DMACH_FLAG_PERIPHIS_MASK (1 << 7) /* Bit 7: Peripheral type */
# define DMACH_FLAG_PERIPHISPERIPH (1 << 7) /* Bit 7: 1 = Peripheral */
# define DMACH_FLAG_PERIPHISMEMORY (0 << 7) /* Bit 7: 0 = Memory */
#define DMACH_FLAG_PERIPHAHB_MASK (1 << 8) /* Bit 8: Peripheral ABH layer 1 */
# define DMACH_FLAG_PERIPHAHB_AHB_IF0 (0)
# define DMACH_FLAG_PERIPHAHB_AHB_IF1 DMACH_FLAG_PERIPHAHB_MASK

71
arch/arm/src/stm32/Kconfig
View File

@ -460,6 +460,30 @@ config ARCH_CHIP_STM32F302VC
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303K6
bool "STM32F303K6"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303K8
bool "STM32F303K8"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303C6
bool "STM32F303C6"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303C8
bool "STM32F303C8"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303CB
bool "STM32F303CB"
select ARCH_CORTEXM4
@ -484,6 +508,18 @@ config ARCH_CHIP_STM32F303RC
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RD
bool "STM32F303RD"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RE
bool "STM32F303RE"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303VB
bool "STM32F303VB"
select ARCH_CORTEXM4
@ -743,6 +779,8 @@ config ARCH_CHIP_STM32F446M
select STM32_STM32F40XX
select STM32_STM32F446
select ARCH_HAVE_FPU
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
config ARCH_CHIP_STM32F446R
bool "STM32F446R"
@ -750,6 +788,8 @@ config ARCH_CHIP_STM32F446R
select STM32_STM32F40XX
select STM32_STM32F446
select ARCH_HAVE_FPU
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
config ARCH_CHIP_STM32F446V
bool "STM32F446V"
@ -757,6 +797,8 @@ config ARCH_CHIP_STM32F446V
select STM32_STM32F40XX
select STM32_STM32F446
select ARCH_HAVE_FPU
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
config ARCH_CHIP_STM32F446Z
bool "STM32F446Z"
@ -764,7 +806,8 @@ config ARCH_CHIP_STM32F446Z
select STM32_STM32F40XX
select STM32_STM32F446
select ARCH_HAVE_FPU
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
endchoice
@ -1346,6 +1389,14 @@ config STM32_HAVE_SPI6
bool
default n
config STM32_HAVE_SAIPLL
bool
default n
config STM32_HAVE_I2SPLL
bool
default n
# These are the peripheral selections proper
config STM32_ADC1
@ -2009,6 +2060,24 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
---help---
Enables special, board-specific STM32 clock configuration.
config STM32_SAIPLL
bool "SAIPLL"
default n
depends on STM32_HAVE_SAIPLL
---help---
The STM32F446 has a separate PLL for the SAI block.
Set this true and provide configuration parameters in
board.h to use this PLL.
config STM32_I2SPLL
bool "I2SPLL"
default n
depends on STM32_HAVE_I2SPLL
---help---
The STM32F446 has a separate PLL for the I2S block.
Set this true and provide configuration parameters in
board.h to use this PLL.
config STM32_CCMEXCLUDE
bool "Exclude CCM SRAM from the heap"
default y if ARCH_DMA || ELF

2
arch/arm/src/stm32/Make.defs
View File

@ -95,6 +95,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif

2
arch/arm/src/stm32/chip/stm32_adc.h
View File

@ -270,7 +270,7 @@
#ifdef CONFIG_STM32_STM32F10XX
# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
#elif CONFIG_STM32_STM32L15XX
#elif defined(CONFIG_STM32_STM32L15XX)
# define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no
* conversion is on going. This bit is available in high and medium+
* density devices only.

1022
arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h Normal file
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File diff suppressed because it is too large Load Diff

9
arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
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@ -536,10 +536,10 @@
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S N multiplication factor for VCO */
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIF-Rx clock */
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (0x3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
/* Set PLLI2S P to 2,4,6,8 */
# define RCC_PLLI2SCFGR_PLLI2SP(n) (((((n)-2)/2) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) & RCC_PLLI2SCFGR_PLLI2SP_MASK)
#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAI1 clock*/
#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
@ -562,7 +562,8 @@
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48 MHz clock */
#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
/* Set PLLSAI P to 2,4,6,8 */
# define RCC_PLLSAICFGR_PLLSAIP(n) (((((n)-2)/2) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) & RCC_PLLSAICFGR_PLLSAIP_MASK)
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)

1014
arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h Normal file
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File diff suppressed because it is too large Load Diff

9
arch/arm/src/stm32/stm32_adc.c
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@ -960,7 +960,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
if (enable)
{
#if CONFIG_ADC_CONTINUOUS
#ifdef CONFIG_ADC_CONTINUOUS
/* Set continuous mode */
@ -974,7 +974,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
}
else
{
#if CONFIG_ADC_CONTINUOUS
#ifdef CONFIG_ADC_CONTINUOUS
/* Disable the continuous conversion */
@ -1761,10 +1761,9 @@ static void adc_shutdown(FAR struct adc_dev_s *dev)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
#if CONFIG_STM32_STM32L15XX
#ifdef CONFIG_STM32_STM32L15XX
adc_enable(priv, false);
# if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \
(STM32_SYSCLK_SW != RCC_CFGR_SW_HSI))
# if (STM32_CFGR_PLLSRC != 0) || (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)
adc_enable_hsi(false);
# endif
#endif

14
arch/arm/src/stm32/stm32_can.c
View File

@ -1070,6 +1070,7 @@ static int can_rx0interrupt(int irq, void *context)
/* Get the CAN identifier. */
regval = can_getreg(priv, STM32_CAN_RI0R_OFFSET);
#ifdef CONFIG_CAN_EXTID
if ((regval & CAN_RIR_IDE) != 0)
{
@ -1089,17 +1090,22 @@ static int can_rx0interrupt(int irq, void *context)
goto errout;
}
hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT;
hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT;
#endif
/* Clear the error indication and unused bits */
hdr.ch_error = 0;
hdr.ch_unused = 0;
/* Extract the RTR bit */
hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0 ? true : false;
hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0 ? true : false;
/* Get the DLC */
regval = can_getreg(priv, STM32_CAN_RDT0R_OFFSET);
hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT;
regval = can_getreg(priv, STM32_CAN_RDT0R_OFFSET);
hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT;
/* Save the message data */

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