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Add LM3S6965 configuration

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2655 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-05-07 04:20:12 +00:00
parent b3df65ddb5
commit 0fba26332d
12 changed files with 188 additions and 67 deletions
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2
arch/arm/src/lm3s/chip.h
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@ -46,7 +46,7 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Get customizations for each supported chip (only the LM3S6918 right now) */ /* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
#if defined(CONFIG_ARCH_CHIP_LM3S6918) #if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define LM3S_NTIMERS 4 /* Four general purpose timers */ # define LM3S_NTIMERS 4 /* Four general purpose timers */

13
arch/arm/src/lm3s/lm3s_dumpgpio.c
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@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/lm3s/lm3s_dumpgpio.c * arch/arm/src/lm3s/lm3s_dumpgpio.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -60,6 +60,7 @@
/* NOTE: this is duplicated in lm3s_gpio.c */ /* NOTE: this is duplicated in lm3s_gpio.c */
#ifdef LM3S_GPIOH_BASE
static const uint32_t g_gpiobase[8] = static const uint32_t g_gpiobase[8] =
{ {
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
@ -67,6 +68,15 @@ static const uint32_t g_gpiobase[8] =
}; };
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
#else
static const uint32_t g_gpiobase[8] =
{
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
};
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
#endif
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
@ -123,6 +133,7 @@ int lm3s_dumpgpio(uint32_t pinset, const char *msg)
/* Get the base address associated with the GPIO port */ /* Get the base address associated with the GPIO port */
base = lm3s_gpiobaseaddress(port); base = lm3s_gpiobaseaddress(port);
DEBUGASSERT(base != 0);
/* The following requires exclusive access to the GPIO registers */ /* The following requires exclusive access to the GPIO registers */

4
arch/arm/src/lm3s/lm3s_ethernet.c
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@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/lm3s/lm3s_ethernet.c * arch/arm/src/lm3s/lm3s_ethernet.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -1068,7 +1068,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)
/* Setup the time stamp configuration register */ /* Setup the time stamp configuration register */
#ifndef CONFIG_ARCH_CHIP_LM3S6918 #if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965)
regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET);
#ifdef CONFIG_LM3S_TIMESTAMP #ifdef CONFIG_LM3S_TIMESTAMP
regval |= MAC_TS_EN; regval |= MAC_TS_EN;

6
arch/arm/src/lm3s/lm3s_ethernet.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/lm3s/lm3s_ethernet.h * arch/arm/src/lm3s/lm3s_ethernet.h
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -66,7 +66,7 @@
#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ #define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ #define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ #define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
#ifndef CONFIG_ARCH_CHIP_LM3S6918 #if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ # define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
#endif #endif
@ -89,7 +89,7 @@
#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) #define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) #define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) #define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
#ifndef CONFIG_ARCH_CHIP_LM3S6918 #if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) # define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
#endif #endif

12
arch/arm/src/lm3s/lm3s_gpio.c
View File

@ -2,7 +2,7 @@
* arch/arm/src/lm3s/lm3s_gpio.c * arch/arm/src/lm3s/lm3s_gpio.c
* arch/arm/src/chip/lm3s_gpio.c * arch/arm/src/chip/lm3s_gpio.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -140,11 +140,18 @@ static const struct gpio_func_s g_funcbits[] =
{GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
}; };
static const uint32_t g_gpiobase[] = #ifdef LM3S_GPIOH_BASE
{ {
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
}; };
#else
static const uint32_t g_gpiobase[] =
{
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
};
#endif
/**************************************************************************** /****************************************************************************
* Public Data * Public Data
@ -704,6 +711,7 @@ int lm3s_configgpio(uint32_t cfgset)
/* Get the base address associated with the GPIO port */ /* Get the base address associated with the GPIO port */
base = lm3s_gpiobaseaddress(port); base = lm3s_gpiobaseaddress(port);
DEBUGASSERT(base != 0);
/* The following requires exclusive access to the GPIO registers */ /* The following requires exclusive access to the GPIO registers */

68
arch/arm/src/lm3s/lm3s_gpio.h
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@ -48,42 +48,38 @@
/* GPIO Register Offsets ************************************************************/ /* GPIO Register Offsets ************************************************************/
#ifdef CONFIG_ARCH_CHIP_LM3S6918 #define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */
# define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ #define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */
# define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ #define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */
# define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ #define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */
# define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ #define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */
# define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ #define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */
# define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ #define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */
# define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ #define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */
# define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ #define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */
# define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ #define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */
# define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ #define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */
# define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ #define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */
# define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ #define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */
# define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ #define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */
# define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ #define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */
# define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ #define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */
# define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ #define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */
# define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ #define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */
# define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ #define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */
# define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ #define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */
# define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ #define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */
# define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ #define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */
# define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ #define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */
# define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ #define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */
# define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ #define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */
# define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ #define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */
# define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ #define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */
# define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ #define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */
# define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ #define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */
# define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ #define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */
# define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ #define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */
# define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ #define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
# define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
#else
# error "GPIO register offsets not specified for this LM3S chip"
#endif
/* GPIO Register Addresses **********************************************************/ /* GPIO Register Addresses **********************************************************/

25
arch/arm/src/lm3s/lm3s_gpioirq.c
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@ -2,7 +2,7 @@
* arch/arm/src/lm3s/lm3s_gpioirq.c * arch/arm/src/lm3s/lm3s_gpioirq.c
* arch/arm/src/chip/lm3s_gpioirq.c * arch/arm/src/chip/lm3s_gpioirq.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -72,27 +72,43 @@ static const uint32_t g_gpiobase[] =
{ {
#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
LM3S_GPIOA_BASE, LM3S_GPIOA_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
LM3S_GPIOB_BASE, LM3S_GPIOB_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
LM3S_GPIOC_BASE, LM3S_GPIOC_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
LM3S_GPIOD_BASE, LM3S_GPIOD_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
LM3S_GPIOE_BASE, LM3S_GPIOE_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
LM3S_GPIOF_BASE, LM3S_GPIOF_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
LM3S_GPIOG_BASE, LM3S_GPIOG_BASE,
#else
0,
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS #if !defined(CONFIG_LM3S_DISABLE_GPIOH_IRQS) && defined(LM3S_GPIOH_BASE)
LM3S_GPIOH_BASE, LM3S_GPIOH_BASE,
#else
0,
#endif #endif
}; };
@ -210,7 +226,7 @@ static int lm3s_gpioghandler(int irq, FAR void *context)
} }
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS #if !defined(CONFIG_LM3S_DISABLE_GPIOH_IRQS) && defined(LM3S_GPIOH_BASE)
static int lm3s_gpiohhandler(int irq, FAR void *context) static int lm3s_gpiohhandler(int irq, FAR void *context)
{ {
return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
@ -263,7 +279,7 @@ int gpio_irqinitialize(void)
#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS #ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler); irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler);
#endif #endif
#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS #if !defined(CONFIG_LM3S_DISABLE_GPIOH_IRQS) && defined(LM3S_GPIOH_BASE)
irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler); irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler);
#endif #endif
@ -332,6 +348,7 @@ void gpio_irqenable(int irq)
/* Get the base address of the GPIO module associated with this IRQ */ /* Get the base address of the GPIO module associated with this IRQ */
base = lm3s_gpiobaseaddress(gpioirq); base = lm3s_gpiobaseaddress(gpioirq);
DEBUGASSERT(base != 0);
pin = (1 << (gpioirq & 7)); pin = (1 << (gpioirq & 7));
/* Disable the GPIO interrupt. "The GPIO IM register is the interrupt /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt

6
arch/arm/src/lm3s/lm3s_internal.h
View File

@ -51,7 +51,7 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* The LM3S6918 only supports 8 priority levels. The hardware priority mechanism /* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism
* will only look at the upper N bits of the 8-bit priority level (where N is 3 for * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
* the Stellaris family), so any prioritization must be performed in those bits. * the Stellaris family), so any prioritization must be performed in those bits.
* The default priority level is set to the middle value * The default priority level is set to the middle value
@ -153,7 +153,7 @@
* hardware function for each pin. * hardware function for each pin.
*/ */
#ifdef CONFIG_ARCH_CHIP_LM3S6918 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ # define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ # define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ # define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
@ -191,7 +191,7 @@
# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ # define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ # define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
#ifdef CONFIG_ARCH_CHIP_LM3S6965 #elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ # define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ # define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ # define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */

1
arch/arm/src/lm3s/lm3s_memorymap.h
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@ -167,7 +167,6 @@
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ # define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */ /* -0x1ffffff: Reserved */
#else #else
#else
# error "Peripheral base addresses not specified for this LM3S chip" # error "Peripheral base addresses not specified for this LM3S chip"
#endif #endif

6
arch/arm/src/lm3s/lm3s_ssi.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/lm32/lm3s_spi.c * arch/arm/src/lm32/lm3s_spi.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -77,8 +77,8 @@
#endif #endif
/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI /* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
* modules (others may support more -- in such case, the following must be * modules, the LM3S6965 supports 1 module (others may support more than 2-- in
* expanded). * such case, the following must be expanded).
*/ */
#if LM3S_NSSI == 0 #if LM3S_NSSI == 0

7
arch/arm/src/lm3s/lm3s_syscontrol.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/lm3s/lm3s_syscontrol.h * arch/arm/src/lm3s/lm3s_syscontrol.h
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -48,8 +48,6 @@
/* System Control Register Offsets **************************************************/ /* System Control Register Offsets **************************************************/
#ifdef CONFIG_ARCH_CHIP_LM3S6918
#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ #define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ #define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ #define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
@ -79,9 +77,6 @@
#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ #define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ #define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ #define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
#else
# error "System control register offsets not specified for this LM3S chip"
#endif
/* System Control Register Addresses ************************************************/ /* System Control Register Addresses ************************************************/

105
arch/arm/src/lm3s/lm3s_vectors.S
View File

@ -2,7 +2,7 @@
* arch/arm/src/lm3s/lm3s_vectors.S * arch/arm/src/lm3s/lm3s_vectors.S
* arch/arm/src/chip/lm3s_vectors.S * arch/arm/src/chip/lm3s_vectors.S
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -127,7 +127,7 @@ lm3s_vectors:
/* External Interrupts */ /* External Interrupts */
#ifdef CONFIG_ARCH_CHIP_LM3S6918 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
.word lm3s_gpioa /* Vector 16: GPIO Port A */ .word lm3s_gpioa /* Vector 16: GPIO Port A */
.word lm3s_gpiob /* Vector 17: GPIO Port B */ .word lm3s_gpiob /* Vector 17: GPIO Port B */
.word lm3s_gpiod /* Vector 18: GPIO Port C */ .word lm3s_gpiod /* Vector 18: GPIO Port C */
@ -154,7 +154,7 @@ lm3s_vectors:
.word lm3s_tmr2a /* Vector 39: Timer 2 A */ .word lm3s_tmr2a /* Vector 39: Timer 2 A */
.word lm3s_tmr2b /* Vector 40: Timer 3 B */ .word lm3s_tmr2b /* Vector 40: Timer 3 B */
.word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */
.word lm3s_dmp1 /* Vector 42: Analog Comparator 1 */ .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */
.word lm3s_reserved /* Vector 43: Reserved */ .word lm3s_reserved /* Vector 43: Reserved */
.word lm3s_syscon /* Vector 44: System Control */ .word lm3s_syscon /* Vector 44: System Control */
.word lm3s_flashcon /* Vector 45: FLASH Control */ .word lm3s_flashcon /* Vector 45: FLASH Control */
@ -183,6 +183,62 @@ lm3s_vectors:
.word lm3s_reserved /* Vector 68: Reserved */ .word lm3s_reserved /* Vector 68: Reserved */
.word lm3s_reserved /* Vector 69: Reserved */ .word lm3s_reserved /* Vector 69: Reserved */
.word lm3s_reserved /* Vector 70: Reserved */ .word lm3s_reserved /* Vector 70: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
.word lm3s_gpioa /* Vector 16: GPIO Port A */
.word lm3s_gpiob /* Vector 17: GPIO Port B */
.word lm3s_gpiod /* Vector 18: GPIO Port C */
.word lm3s_gpioe /* Vector 19: GPIO Port D */
.word lm3s_gpioe /* Vector 20: GPIO Port E */
.word lm3s_uart0 /* Vector 21: UART 0 */
.word lm3s_uart1 /* Vector 22: UART 1 */
.word lm3s_ssi0 /* Vector 23: SSI 0 */
.word lm3s_i2c0 /* Vector 24: I2C 0 */
.word lm3s_pwmfault /* Vector 25: PWM Fault */
.word lm3s_pwm0 /* Vector 26: PWM Generator 0 */
.word lm3s_pwm1 /* Vector 27: PWM Generator 1 */
.word lm3s_pwm2 /* Vector 28: PWM Generator 2 */
.word lm3s_qei0 /* Vector 29: QEI0 */
.word lm3s_adc0 /* Vector 30: ADC Sequence 0 */
.word lm3s_adc1 /* Vector 31: ADC Sequence 1 */
.word lm3s_adc2 /* Vector 32: ADC Sequence 2 */
.word lm3s_adc3 /* Vector 33: ADC Sequence 3 */
.word lm3s_wdog /* Vector 34: Watchdog Timer */
.word lm3s_tmr0a /* Vector 35: Timer 0 A */
.word lm3s_tmr0b /* Vector 36: Timer 0 B */
.word lm3s_tmr1a /* Vector 37: Timer 1 A */
.word lm3s_tmr1b /* Vector 38: Timer 1 B */
.word lm3s_tmr2a /* Vector 39: Timer 2 A */
.word lm3s_tmr2b /* Vector 40: Timer 3 B */
.word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */
.word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */
.word lm3s_reserved /* Vector 43: Reserved */
.word lm3s_syscon /* Vector 44: System Control */
.word lm3s_flashcon /* Vector 45: FLASH Control */
.word lm3s_gpiof /* Vector 46: GPIO Port F */
.word lm3s_gpiog /* Vector 47: GPIO Port G */
.word lm3s_reserved /* Vector 48: Reserved */
.word lm3s_uart2 /* Vector 49: UART 2 */
.word lm3s_reserved /* Vector 50: Reserved */
.word lm3s_tmr3a /* Vector 51: Timer 3 A */
.word lm3s_tmr3b /* Vector 52: Timer 3 B */
.word lm3s_i2c1 /* Vector 53: I2C 1 */
.word lm3s_qei1 /* Vector 54: QEI1 */
.word lm3s_reserved /* Vector 55: Reserved */
.word lm3s_reserved /* Vector 56: Reserved */
.word lm3s_reserved /* Vector 57: Reserved */
.word lm3s_eth /* Vector 58: Ethernet Controller */
.word lm3s_hib /* Vector 59: Hibernation Module */
.word lm3s_reserved /* Vector 60: Reserved */
.word lm3s_reserved /* Vector 61: Reserved */
.word lm3s_reserved /* Vector 62: Reserved */
.word lm3s_reserved /* Vector 63: Reserved */
.word lm3s_reserved /* Vector 64: Reserved */
.word lm3s_reserved /* Vector 65: Reserved */
.word lm3s_reserved /* Vector 66: Reserved */
.word lm3s_reserved /* Vector 67: Reserved */
.word lm3s_reserved /* Vector 68: Reserved */
.word lm3s_reserved /* Vector 69: Reserved */
.word lm3s_reserved /* Vector 70: Reserved */
#else #else
# error "Vectors not specified for this LM3S chip" # error "Vectors not specified for this LM3S chip"
#endif #endif
@ -207,7 +263,7 @@ handlers:
HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */
#ifdef CONFIG_ARCH_CHIP_LM3S6918 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
@ -229,7 +285,7 @@ handlers:
HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm3s_dmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
@ -241,6 +297,45 @@ handlers:
HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#else #else
# error "Vectors not specified for this LM3S chip" # error "Vectors not specified for this LM3S chip"
#endif #endif