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LPC43xx: Add ehci driver.

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This commit is contained in:
Ilya Averyanov 2015-09-10 07:23:03 -06:00 committed by Gregory Nutt
parent 87aa1cb83b
commit 0fea56cd8b
7 changed files with 5477 additions and 39 deletions
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42
arch/arm/src/lpc43xx/Kconfig
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@ -421,6 +421,48 @@ config LPC43_USART3
select ARCH_HAVE_USART3
select ARCH_HAVE_SERIAL_TERMIOS
config LPC43_USBOTG
bool "USB EHCI"
default n
select USBHOST_HAVE_ASYNCH
if LPC43_USBOTG && USBHOST
menu "USB host controller driver (HCD) options"
config LPC43_EHCI_NQHS
int "Number of Queue Head (QH) structures"
default 4
---help---
Configurable number of Queue Head (QH) structures. The default is
one per Root hub port plus one for EP0 (4).
config LPC43_EHCI_NQTDS
int "Number of Queue Element Transfer Descriptor (qTDs)"
default 6
---help---
Configurable number of Queue Element Transfer Descriptor (qTDs).
The default is one per root hub plus three from EP0 (6).
config LPC43_EHCI_BUFSIZE
int "Size of one request/descriptor buffer"
default 128
---help---
The size of one request/descriptor buffer in bytes. The TD buffe
size must be an even number of 32-bit words and must be large enough
to hangle the largest transfer via a SETUP request.
config LPC43_EHCI_PREALLOCATE
bool "Preallocate descriptor pool"
default y
---help---
Select this option to pre-allocate EHCI queue and descriptor
structure pools in .bss. Otherwise, these pools will be
dynamically allocated using kmm_memalign().
endmenu # USB host controller driver (HCD) options
endif # LPC43_USBOTG && USBHOST
config LPC43_USB0
bool "USB0"
default n

4
arch/arm/src/lpc43xx/Make.defs
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@ -166,6 +166,10 @@ CHIP_CSRCS += lpc43_adc.c
endif
endif
ifeq ($(CONFIG_LPC43_USBOTG),y)
CHIP_CSRCS += lpc43_ehci.c
endif
ifeq ($(CONFIG_LPC43_USB0),y)
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += lpc43_usb0dev.c

80
arch/arm/src/lpc43xx/chip/lpc43_usb0.h
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@ -50,6 +50,7 @@
/* 0x000 - 0x0ff: Reserved */
/* Device/host capability registers */
#define LPC43_USBOTG_HCCR_OFFSET 0x0100 /* Offset to EHCI Host Controller Capabiliy registers */
#define LPC43_USBOTG_CAPLENGTH_OFFSET 0x0100 /* Capability length register */
#define LPC43_USBHOST_HCSPARAMS_OFFSET 0x0104 /* Host controller structural parameters */
#define LPC43_USBHOST_HCCPARAMS_OFFSET 0x0108 /* Host controller capability parameters */
@ -57,7 +58,7 @@
#define LPC43_USBDEV_DCCPARAMS_OFFSET 0x0124 /* Device controller capability parameters */
/* Device/host/OTG operational registers */
#define LPC43_USBOTG_HCOR_OFFSET 0x0140 /* Offset to EHCI Host Controller Operational Registers */
#define LPC43_USBOTG_USBCMD_OFFSET 0x0140 /* USB command (both) */
#define LPC43_USBOTG_USBSTS_OFFSET 0x0144 /* USB status (both) */
#define LPC43_USBOTG_USBINTR_OFFSET 0x0148 /* USB interrupt enable (both) */
@ -117,33 +118,33 @@
/* USB0 register (virtual) addresses **********************************************************/
/* Device/host capability registers */
#define LPC43_USBOTG_CAPLENGTH (LPC43_USBOTG_BASE+LPC43_USBOTG_CAPLENGTH_OFFSET)
#define LPC43_USBHOST_HCIVERSION (LPC43_USBOTG_BASE+LPC43_USBHOST_HCIVERSION_OFFSET)
#define LPC43_USBHOST_HCSPARAMS (LPC43_USBOTG_BASE+LPC43_USBHOST_HCSPARAMS_OFFSET)
#define LPC43_USBHOST_HCCPARAMS (LPC43_USBOTG_BASE+LPC43_USBHOST_HCCPARAMS_OFFSET)
#define LPC43_USBDEV_DCIVERSION (LPC43_USBOTG_BASE+LPC43_USBDEV_DCIVERSION_OFFSET)
#define LPC43_USBDEV_DCCPARAMS (LPC43_USBOTG_BASE+LPC43_USBDEV_DCCPARAMS_OFFSET)
#define LPC43_USBOTG_HCCR_BASE (LPC43_USB0_BASE+LPC43_USBOTG_HCCR_OFFSET)
#define LPC43_USBOTG_CAPLENGTH (LPC43_USB0_BASE+LPC43_USBOTG_CAPLENGTH_OFFSET)
#define LPC43_USBHOST_HCIVERSION (LPC43_USB0_BASE+LPC43_USBHOST_HCIVERSION_OFFSET)
#define LPC43_USBHOST_HCSPARAMS (LPC43_USB0_BASE+LPC43_USBHOST_HCSPARAMS_OFFSET)
#define LPC43_USBHOST_HCCPARAMS (LPC43_USB0_BASE+LPC43_USBHOST_HCCPARAMS_OFFSET)
#define LPC43_USBDEV_DCIVERSION (LPC43_USB0_BASE+LPC43_USBDEV_DCIVERSION_OFFSET)
#define LPC43_USBDEV_DCCPARAMS (LPC43_USB0_BASE+LPC43_USBDEV_DCCPARAMS_OFFSET)
/* Device/host operational registers */
#define LPC43_USBOTG_USBCMD (LPC43_USBOTG_BASE+LPC43_USBOTG_USBCMD_OFFSET)
#define LPC43_USBOTG_USBSTS (LPC43_USBOTG_BASE+LPC43_USBOTG_USBSTS_OFFSET)
#define LPC43_USBOTG_USBINTR (LPC43_USBOTG_BASE+LPC43_USBOTG_USBINTR_OFFSET)
#define LPC43_USBOTG_FRINDEX (LPC43_USBOTG_BASE+LPC43_USBOTG_FRINDEX_OFFSET)
#define LPC43_USBHOST_PERIODICLIST (LPC43_USBOTG_BASE+LPC43_USBHOST_PERIODICLIST_OFFSET)
#define LPC43_USBDEV_DEVICEADDR (LPC43_USBOTG_BASE+LPC43_USBDEV_DEVICEADDR_OFFSET)
#define LPC43_USBHOST_ASYNCLISTADDR (LPC43_USBOTG_BASE+LPC43_USBHOST_ASYNCLISTADDR_OFFSET)
#define LPC43_USBDEV_ENDPOINTLIST (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPOINTLIST_OFFSET)
#define LPC43_USBHOST_TTCTRL (LPC43_USBOTG_BASE+LPC43_USBHOST_TTCTRL_OFFSET)
#define LPC43_USBOTG_BURSTSIZE (LPC43_USBOTG_BASE+LPC43_USBOTG_BURSTSIZE_OFFSET)
#define LPC43_USBHOST_TXFILLTUNING (LPC43_USBOTG_BASE+LPC43_USBHOST_TXFILLTUNING_OFFSET)
#define LPC43_USBOTG_BINTERVAL (LPC43_USBOTG_BASE+LPC43_USBOTG_BINTERVAL_OFFSET)
#define LPC43_USBDEV_ENDPTNAK (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTNAK_OFFSET)
#define LPC43_USBDEV_ENDPTNAKEN (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTNAKEN_OFFSET)
#define LPC43_USBOTG_PORTSC1 (LPC43_USBOTG_BASE+LPC43_USBOTG_PORTSC1_OFFSET)
#define LPC43_USBOTG_OTGSC (LPC43_USBOTG_BASE+LPC43_USBOTG_OTGSC_OFFSET)
#define LPC43_USBOTG_USBMODE (LPC43_USBOTG_BASE+LPC43_USBOTG_USBMODE_OFFSET)
#define LPC43_USBOTG_HCOR_BASE (LPC43_USB0_BASE+LPC43_USBOTG_HCOR_OFFSET)
#define LPC43_USBOTG_USBCMD (LPC43_USB0_BASE+LPC43_USBOTG_USBCMD_OFFSET)
#define LPC43_USBOTG_USBSTS (LPC43_USB0_BASE+LPC43_USBOTG_USBSTS_OFFSET)
#define LPC43_USBOTG_USBINTR (LPC43_USB0_BASE+LPC43_USBOTG_USBINTR_OFFSET)
#define LPC43_USBOTG_FRINDEX (LPC43_USB0_BASE+LPC43_USBOTG_FRINDEX_OFFSET)
#define LPC43_USBHOST_PERIODICLIST (LPC43_USB0_BASE+LPC43_USBHOST_PERIODICLIST_OFFSET)
#define LPC43_USBDEV_DEVICEADDR (LPC43_USB0_BASE+LPC43_USBDEV_DEVICEADDR_OFFSET)
#define LPC43_USBHOST_ASYNCLISTADDR (LPC43_USB0_BASE+LPC43_USBHOST_ASYNCLISTADDR_OFFSET)
#define LPC43_USBDEV_ENDPOINTLIST (LPC43_USB0_BASE+LPC43_USBDEV_ENDPOINTLIST_OFFSET)
#define LPC43_USBHOST_TTCTRL (LPC43_USB0_BASE+LPC43_USBHOST_TTCTRL_OFFSET)
#define LPC43_USBOTG_BURSTSIZE (LPC43_USB0_BASE+LPC43_USBOTG_BURSTSIZE_OFFSET)
#define LPC43_USBHOST_TXFILLTUNING (LPC43_USB0_BASE+LPC43_USBHOST_TXFILLTUNING_OFFSET)
#define LPC43_USBOTG_BINTERVAL (LPC43_USB0_BASE+LPC43_USBOTG_BINTERVAL_OFFSET)
#define LPC43_USBDEV_ENDPTNAK (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTNAK_OFFSET)
#define LPC43_USBDEV_ENDPTNAKEN (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTNAKEN_OFFSET)
#define LPC43_USBOTG_PORTSC1 (LPC43_USB0_BASE+LPC43_USBOTG_PORTSC1_OFFSET)
#define LPC43_USBOTG_OTGSC (LPC43_USB0_BASE+LPC43_USBOTG_OTGSC_OFFSET)
#define LPC43_USBOTG_USBMODE (LPC43_USB0_BASE+LPC43_USBOTG_USBMODE_OFFSET)
/* Device side naming of common register offsets */
@ -169,19 +170,19 @@
/* Device endpoint registers */
#define LPC43_USBDEV_ENDPTSETUPSTAT (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTSETUPSTAT_OFFSET)
#define LPC43_USBDEV_ENDPTPRIME (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTPRIME_OFFSET)
#define LPC43_USBDEV_ENDPTFLUSH (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTFLUSH_OFFSET)
#define LPC43_USBDEV_ENDPTSTATUS (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTSTATUS_OFFSET)
#define LPC43_USBDEV_ENDPTCOMPLETE (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCOMPLETE_OFFSET)
#define LPC43_USBDEV_ENDPTSETUPSTAT (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTSETUPSTAT_OFFSET)
#define LPC43_USBDEV_ENDPTPRIME (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTPRIME_OFFSET)
#define LPC43_USBDEV_ENDPTFLUSH (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTFLUSH_OFFSET)
#define LPC43_USBDEV_ENDPTSTATUS (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTSTATUS_OFFSET)
#define LPC43_USBDEV_ENDPTCOMPLETE (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCOMPLETE_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL(n) (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL_OFFSET(n))
#define LPC43_USBDEV_ENDPTCTRL0 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL0_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL1 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL1_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL2 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL2_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL3 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL3_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL4 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL4_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL5 (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL5_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL(n) (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL_OFFSET(n))
#define LPC43_USBDEV_ENDPTCTRL0 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL0_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL1 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL1_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL2 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL2_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL3 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL3_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL4 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL4_OFFSET)
#define LPC43_USBDEV_ENDPTCTRL5 (LPC43_USB0_BASE+LPC43_USBDEV_ENDPTCTRL5_OFFSET)
/* USB0 register bit definitions **************************************************************/
@ -457,6 +458,7 @@
#define USBDEV_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBDEV_PRTSC1_PSPD_MASK (3 << USBDEV_PRTSC1_PSPD_SHIFT)
# define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBDEV_PRTSC1_PSPD_LS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */
/* Bits 28-31: Reserved */
/* Port Status and Control register PRTSC1 -- Host Mode */
@ -526,7 +528,7 @@
#define USBOTG_OTGSC_BSE (1 << 12) /* Bit 12: B-session end */
#define USBOTG_OTGSC_1MST (1 << 13) /* Bit 13: 1 millisecond timer toggle */
#define USBOTG_OTGSC_DPS (1 << 14) /* Bit 14: Data bus pulsing status */
/* Bit 15: Reserved *.
/* Bit 15: Reserved */
/* OTG interrupt status */
#define USBOTG_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID interrupt status */

71
arch/arm/src/lpc43xx/lpc43_cgu.c
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@ -417,6 +417,77 @@ static inline void lpc43_m4clkselect(uint32_t clksel)
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: lpc43_pll0usbconfig
*
* Description:
* Configure PLL0USB dividers and multipliers per the settings in the board.h
* file to generate the desired Fclkcout and Fcco frequencies.
*
****************************************************************************/
void lpc43_pll0usbconfig(void)
{
putreg32(BOARD_USB0_CTL, LPC43_PLL0USB_CTRL);
putreg32(BOARD_USB0_MDIV, LPC43_PLL0USB_MDIV);
putreg32(BOARD_USB0_NP_DIV, LPC43_PLL0USB_NP_DIV);
}
/****************************************************************************
* Name: lpc43_pll0usbenable
*
* Description:
* Take PLL0USB out of power-down mode and wait until it is locked onto the
* input clock.
*
****************************************************************************/
void lpc43_pll0usbenable(void)
{
uint32_t regval;
/* Take PLL1 out of power down mode. The reset state of the PD bit
* is one, i.e., powered down.
*/
regval = getreg32(LPC43_PLL0USB_CTRL);
regval &= ~PLL0USB_CTRL_PD;
putreg32(regval, LPC43_PLL0USB_CTRL);
/* When the power-down mode is terminated, PPL1 will resume its normal
* operation and will make the lock signal high once it has regained
* lock on the input clock
*
* Wait for PLL1 to report that it is locked.
*/
while ((getreg32(LPC43_PLL0USB_STAT) & PLL0USB_STAT_LOCK) == 0);
}
/****************************************************************************
* Name: lpc43_pll0usbdisable
*
* Description:
* Take PLL0USB to power-down mode.
*
****************************************************************************/
void lpc43_pll0usbdisable(void)
{
uint32_t regval;
/* Take PLL1 out of power down mode. The reset state of the PD bit
* is one, i.e., powered down.
*/
regval = getreg32(LPC43_PLL0USB_CTRL);
regval |= PLL0USB_CTRL_PD;
putreg32(regval, LPC43_PLL0USB_CTRL);
}
/****************************************************************************
* Name: lpc43_clockconfig
*

31
arch/arm/src/lpc43xx/lpc43_cgu.h
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@ -71,6 +71,37 @@ extern "C"
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: lpc43_pll0usbdisable
*
* Description:
* Take PLL0USB to power-down mode.
*
****************************************************************************/
EXTERN void lpc43_pll0usbdisable(void);
/****************************************************************************
* Name: lpc43_pll0usbenable
*
* Description:
* Take PLL0USB out of power-down mode and wait until it is locked onto the
* input clock.
*
****************************************************************************/
EXTERN void lpc43_pll0usbenable(void);
/************************************************************************************
* Name: lpc43_pll0usbconfig
*
* Description:
* Config USB0 PLL
*
************************************************************************************/
EXTERN void lpc43_pll0usbconfig(void);
/************************************************************************************
* Name: lpc43_clockconfig
*

5179
arch/arm/src/lpc43xx/lpc43_ehci.c Normal file
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File diff suppressed because it is too large Load Diff

109
arch/arm/src/lpc43xx/lpc43_ehci.h Normal file
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@ -0,0 +1,109 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_ehci.h
*
* Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_EHCI_H
#define __ARCH_ARM_SRC_LPC43XX_LPC43_EHCI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/*******************************************************************************
* Name: lpc31_ehci_initialize
*
* Description:
* Initialize USB EHCI host controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order
* to initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already connected.
*
*******************************************************************************/
#if defined(CONFIG_LPC43_USBOTG) && defined(CONFIG_USBHOST)
struct usbhost_connection_s;
FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EHCI_H */