stm32_dac: separate dma buffer configuration for channels
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raiden00pl
parent
55f27c40e8
commit
104ff2b5d8
@ -5849,6 +5849,10 @@ config STM32_DAC1CH1_DMA
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if STM32_DAC1CH1_DMA
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config STM32_DAC1CH1_DMA_BUFFER_SIZE
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int "DAC1CH1 DMA buffer size"
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default 256
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config STM32_DAC1CH1_TIMER
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int "DAC1CH1 timer"
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range 2 8
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@ -5871,6 +5875,10 @@ config STM32_DAC1CH2_DMA
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if STM32_DAC1CH2_DMA
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config STM32_DAC1CH2_DMA_BUFFER_SIZE
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int "DAC1CH2 DMA buffer size"
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default 256
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config STM32_DAC1CH2_TIMER
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int "DAC1CH2 timer"
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range 2 8
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@ -5893,6 +5901,10 @@ config STM32_DAC2CH1_DMA
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if STM32_DAC2CH1_DMA
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config STM32_DAC2CH1_DMA_BUFFER_SIZE
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int "DAC2CH1 DMA buffer size"
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default 256
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config STM32_DAC2CH1_TIMER
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int "DAC2CH1 timer"
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default 0
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@ -5904,10 +5916,6 @@ config STM32_DAC2CH1_TIMER_FREQUENCY
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endif
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config STM32_DAC_DMA_BUFFER_SIZE
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int "DAC DMA buffer size"
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default 256
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endmenu
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config STM32_USART
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@ -190,19 +190,31 @@
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#undef HAVE_DMA
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#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \
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defined(CONFIG_STM32_DAC2CH1_DMA)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# define HAVE_DMA 1
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# define DAC_DMA 2
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# define DAC1CH1_DMA_CHAN DMACHAN_DAC_CHAN1
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# define DAC1CH2_DMA_CHAN DMACHAN_DAC_CHAN2
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# define DAC2CH1_DMA_CHAN DMACHAN_DAC_CHAN2
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \
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defined(CONFIG_STM32_STM32F33XX)
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# define HAVE_DMA 1
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# define DAC_DMA 1
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# define DAC1CH1_DMA_CHAN DMAMAP_DAC1
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# define DAC1CH2_DMA_CHAN DMAMAP_DAC1
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# define DAC2CH1_DMA_CHAN DMAMAP_DAC2
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F33XX)
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# define HAVE_DMA 1
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# define DAC_DMA 2
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# ifdef CONFIG_STM32_DAC1CH1
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# define DAC1CH1_DMA_CHAN DMACHAN_DAC1_CH1
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# endif
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# ifdef CONFIG_STM32_DAC1CH2
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# define DAC1CH2_DMA_CHAN DMACHAN_DAC1_CH2
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# endif
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# ifdef CONFIG_STM32_DAC2CH1
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# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH2
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# endif
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
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# define HAVE_DMA 1
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# define DAC_DMA 1
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# ifdef CONFIG_STM32_DAC1CH1
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# define DAC1CH1_DMA_CHAN DMAMAP_DAC1
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# endif
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# ifdef CONFIG_STM32_DAC1CH1
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# define DAC1CH2_DMA_CHAN DMAMAP_DAC1
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# endif
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# ifdef CONFIG_STM32_DAC1CH1
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# define DAC2CH1_DMA_CHAN DMAMAP_DAC2
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# endif
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# endif
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#endif
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@ -409,8 +421,16 @@
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# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW
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#endif
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#ifndef CONFIG_STM32_DAC_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC_DMA_BUFFER_SIZE 256
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#ifndef CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE 256
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#endif
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#ifndef CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE 256
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#endif
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#ifndef CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE 256
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#endif
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/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and
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@ -462,10 +482,11 @@ struct stm32_chan_s
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uint32_t tsel; /* CR trigger select value */
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#ifdef HAVE_DMA
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uint16_t dmachan; /* DMA channel needed by this DAC */
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uint16_t buffer_len; /* DMA buffer length */
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DMA_HANDLE dma; /* Allocated DMA channel */
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uint32_t tbase; /* Timer base address */
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uint32_t tfrequency; /* Timer frequency */
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uint16_t dmabuffer[CONFIG_STM32_DAC_DMA_BUFFER_SIZE]; /* DMA transfer buffer */
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uint16_t *dmabuffer; /* DMA transfer buffer */
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#endif
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};
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@ -521,6 +542,10 @@ static const struct dac_ops_s g_dacops =
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#ifdef CONFIG_STM32_DAC1CH1
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/* Channel 1: DAC1 channel 1 */
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#ifdef CONFIG_STM32_DAC1CH1_DMA
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uint16_t dac1ch1_buffer[CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE];
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#endif
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static struct stm32_chan_s g_dac1ch1priv =
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{
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.intf = 0,
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@ -536,6 +561,8 @@ static struct stm32_chan_s g_dac1ch1priv =
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#ifdef CONFIG_STM32_DAC1CH1_DMA
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.hasdma = 1,
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.dmachan = DAC1CH1_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE,
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.dmabuffer = dac1ch1_buffer,
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.timer = CONFIG_STM32_DAC1CH1_TIMER,
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.tsel = DAC1CH1_TSEL_VALUE,
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.tbase = DAC1CH1_TIMER_BASE,
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@ -554,6 +581,10 @@ static struct dac_dev_s g_dac1ch1dev =
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#ifdef CONFIG_STM32_DAC1CH2
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/* Channel 2: DAC1 channel 2 */
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#ifdef CONFIG_STM32_DAC1CH2_DMA
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uint16_t dac1ch2_buffer[CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE];
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#endif
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static struct stm32_chan_s g_dac1ch2priv =
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{
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.intf = 1,
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@ -563,6 +594,8 @@ static struct stm32_chan_s g_dac1ch2priv =
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#ifdef CONFIG_STM32_DAC2_DMA
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.hasdma = 1,
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.dmachan = DAC1CH2_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE,
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.dmabuffer = dac1ch2_buffer,
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.timer = CONFIG_STM32_DAC1CH2_TIMER,
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.tsel = DAC1CH2_TSEL_VALUE,
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.tbase = DAC1CH2_TIMER_BASE,
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@ -584,6 +617,10 @@ static struct dac_dev_s g_dac1ch2dev =
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#ifdef CONFIG_STM32_DAC2CH1
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/* Channel 3: DAC2 channel 1 */
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#ifdef CONFIG_STM32_DAC2CH1_DMA
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uint16_t dac2ch1_buffer[CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE];
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#endif
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static struct stm32_chan_s g_dac2ch1priv =
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{
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.intf = 2,
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@ -593,6 +630,8 @@ static struct stm32_chan_s g_dac2ch1priv =
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#ifdef CONFIG_STM32_DAC2CH1_DMA
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.hasdma = 1,
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.dmachan = DAC2CH1_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE,
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.dmabuffer = dac2ch1_buffer,
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.timer = CONFIG_STM32_DAC2CH1_TIMER,
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.tsel = DAC2CH1_TSEL_VALUE,
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.tbase = DAC2CH1_TIMER_BASE,
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@ -888,7 +927,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
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*/
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stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer,
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CONFIG_STM32_DAC_DMA_BUFFER_SIZE, DAC_DMA_CONTROL_WORD);
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chan->buffer_len, DAC_DMA_CONTROL_WORD);
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/* Enable DMA */
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