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arch/arm/src/stm32f7: Refactor FMC functions for STM32F7

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This refactor is based on the FMC architecture of STM32H7, with the
exception of the board specific definitions.
This commit is contained in:
Gustavo Henrique Nihei 2020-06-23 17:22:22 -03:00 committed by Alan Carvalho de Assis
parent cf86459495
commit 105d561a51
5 changed files with 728 additions and 509 deletions
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4
arch/arm/src/stm32f7/Make.defs
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@ -133,6 +133,10 @@ ifeq ($(CONFIG_STM32F7_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32F7_FMC),y)
CHIP_CSRCS += stm32_fmc.c
endif
ifeq ($(CONFIG_PM),y)
CHIP_CSRCS += stm32_pmstandby.c stm32_pmstop.c stm32_pmsleep.c
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)

396
arch/arm/src/stm32f7/hardware/stm32_fmc.h Normal file
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@ -0,0 +1,396 @@
/****************************************************************************
* arch/arm/src/stm32f7/hardware/stm32_fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FMC_H
#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
#define STM32_FMC_PCR_OFFSET 0x0080 /* NAND Flash control register */
#define STM32_FMC_SR_OFFSET 0x0084 /* FIFO status and interrupt register */
#define STM32_FMC_PMEM_OFFSET 0x0088 /* Common memory space timing register */
#define STM32_FMC_PATT_OFFSET 0x008c /* Attribute memory space timing register */
#define STM32_FMC_ECCR_OFFSET 0x0094 /* ECC result register */
#define STM32_FMC_SDCR_OFFSET(n) (4*((n)-1)+0x0140)
#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */
#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
#define STM32_FMC_SDTR_OFFSET(n) (4*((n)-1)+0x0148)
#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Command mode register */
#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
/* Register Addresses *******************************************************/
#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
#define STM32_FMC_PCR (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET)
#define STM32_FMC_SR (STM32_FMC_BASE+STM32_FMC_SR_OFFSET)
#define STM32_FMC_PMEM (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET)
#define STM32_FMC_PATT (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET)
#define STM32_FMC_ECCR (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET)
#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID32 (2 << FMC_BCR_MWID_SHIFT)
#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#define FMC_BCR_CPSIZE_SHIFT (16)
#define FMC_BCR_CPSIZE_MASK (7 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE0 (0 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE128 (1 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE256 (2 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE1024 (3 << FMC_BCR_CPSIZE_SHIFT)
#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FMC_BCR_CCLKEN (1 << 20) /* Continuous Clock Enable */
#define FMC_BCR_WFDIS (1 << 21) /* Write FIFO Disable */
#define FMC_BCR_BMAP_SHIFT (24)
#define FMC_BCR_BMAP_MASK (3 << FMC_BCR_BMAP_SHIFT)
# define FMC_BCR_BMAP0 (0 << FMC_BCR_BMAP_SHIFT) /* Default mapping */
# define FMC_BCR_BMAP1 (1 << FMC_BCR_BMAP_SHIFT) /* NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped */
# define FMC_BCR_BMAP2 (2 << FMC_BCR_BMAP_SHIFT) /* SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping */
#define FMC_BCR_FMCEN (1 << 31) /* FMC controller Enable */
#define FMC_BCR_RSTVALUE(n) ((n == 0) ? 0x000030db : 0x000030d2) /* Reset value for BCR */
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT)/* (n)xHCLK n=1..16 */
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT)
/* (n)xHCLK n=2..17 */
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
#define FMC_BTR_RSTVALUE 0xffffffff
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT)/* (n)xHCLK n=1..16 */
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT)/* (n)xHCLK n=2..16 */
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT)/* (n)xHCLK n=2..256 */
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT)/* (n)xHCLK n=2..16 */
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT)/* (n)xHCLK n=2..17 */
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODD (3 << FMC_BWTR_ACCMOD_SHIFT)
#define FMC_PCR_RSTVALUE (0x00000018)
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FMC_PMEM_RSTVALUE (0xfcfcfcfc)
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT)/* (n)xHCLK n=1..256 */
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
# define FMC_PMEM_MEMWAIT(n) ((n-1)<<FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT)/* (n)xHCLK n=1..255 */
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT)/* (n)xHCLK n=1..256 */
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
# define FMC_PATT_ATTWAIT(n) ((n-1)<<FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT)/* (n)xHCLK n=1..255 */
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
# define FMC_SDCR_COLBITS_SHIFT (0)
# define FMC_SDCR_COLBITS_MASK (3 << FMC_SDCR_COLBITS_SHIFT)
# define FMC_SDCR_COLBITS_8 0x00000000
# define FMC_SDCR_COLBITS_9 0x00000001
# define FMC_SDCR_COLBITS_10 0x00000002
# define FMC_SDCR_COLBITS_11 0x00000003
# define FMC_SDCR_ROWBITS_SHIFT (2)
# define FMC_SDCR_ROWBITS_MASK (3 << FMC_SDCR_ROWBITS_SHIFT)
# define FMC_SDCR_ROWBITS_11 0x00000000
# define FMC_SDCR_ROWBITS_12 0x00000004
# define FMC_SDCR_ROWBITS_13 0x00000008
# define FMC_SDCR_WIDTH_SHIFT (4)
# define FMC_SDCR_WIDTH_MASK (3 << FMC_SDCR_WIDTH_SHIFT)
# define FMC_SDCR_WIDTH_8 0x00000000
# define FMC_SDCR_WIDTH_16 0x00000010
# define FMC_SDCR_WIDTH_32 0x00000020
# define FMC_SDCR_BANKS_SHIFT (6)
# define FMC_SDCR_BANKS_MASK (1 << FMC_SDCR_BANKS_SHIFT)
# define FMC_SDCR_BANKS_2 0x00000000
# define FMC_SDCR_BANKS_4 0x00000040
# define FMC_SDCR_CASLAT_SHIFT (7)
# define FMC_SDCR_CASLAT_MASK (3 << FMC_SDCR_CASLAT_SHIFT)
# define FMC_SDCR_CASLAT_1 0x00000080
# define FMC_SDCR_CASLAT_2 0x00000100
# define FMC_SDCR_CASLAT_3 0x00000180
# define FMC_SDCR_WP 0x00000200
# define FMC_SDCR_SDCLK_SHIFT (10)
# define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT)
# define FMC_SDCR_SDCLK_DISABLE 0x00000000
# define FMC_SDCR_SDCLK_2X 0x00000800
# define FMC_SDCR_SDCLK_3X 0x00000C00
# define FMC_SDCR_BURST_READ 0x00001000
# define FMC_SDCR_RPIPE_SHIFT (13)
# define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT)
# define FMC_SDCR_RPIPE_0 0x00000000
# define FMC_SDCR_RPIPE_1 0x00002000
# define FMC_SDCR_RPIPE_2 0x00004000
#define FMC_SDCR_RESERVED (0x1FFFF << 15) /* reserved bits */
#define FMC_SDTR_TMRD_SHIFT (0)
#define FMC_SDTR_TMRD_MASK FMC_SDTR_TMRD(16)
#define FMC_SDTR_TMRD(n) (((n)-1)<<FMC_SDTR_TMRD_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TXSR_SHIFT (4)
#define FMC_SDTR_TXSR_MASK FMC_SDTR_TXSR(16)
#define FMC_SDTR_TXSR(n) (((n)-1) << FMC_SDTR_TXSR_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_TRAS_SHIFT (8)
#define FMC_SDTR_TRAS_MASK FMC_SDTR_TRAS(16)
#define FMC_SDTR_TRAS(n) (((n)-1) << FMC_SDTR_TRAS_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_TRC_SHIFT (12)
#define FMC_SDTR_TRC_MASK FMC_SDTR_TRC(16)
#define FMC_SDTR_TRC(n) (((n)-1) << FMC_SDTR_TRC_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TWR_SHIFT (16)
#define FMC_SDTR_TWR_MASK FMC_SDTR_TWR(16)
#define FMC_SDTR_TWR(n) (((n)-1) << FMC_SDTR_TWR_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TRP_SHIFT (20)
#define FMC_SDTR_TRP_MASK FMC_SDTR_TRP(16)
#define FMC_SDTR_TRP(n) (((n)-1) << FMC_SDTR_TRP_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TRCD_SHIFT (24)
#define FMC_SDTR_TRCD_MASK FMC_SDTR_TRCD(16)
#define FMC_SDTR_TRCD(n) (((n)-1) << FMC_SDTR_TRCD_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_RESERVED (0xF << 28) /* reserved bits */
#define FMC_SDCMR_MODE_SHIFT (0)
#define FMC_SDCMR_MODE_MASK (7 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_NORMAL (0 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_CLK_ENABLE (1 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_PALL (2 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_AUTO_REFRESH (3 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_LOAD_MODE (4 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_SELF_REFRESH (5 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_POWER_DOWN (6 << FMC_SDCMR_MODE_SHIFT)
#define FMC_SDCMR_CTB2 (1 << 3)
#define FMC_SDCMR_CTB1 (1 << 4)
#define FMC_SDCMR_NRFS_SHIFT (5)
#define FMC_SDCMR_NRFS(n) (((n)-1)<<FMC_SDCMR_NRFS_SHIFT) /* 1 to 16 cycles */
#define FMC_SDCMR_MRD_SHIFT (9)
#define FMC_SDCMR_MRD_MASK FMC_SDCMR_MRD(16383)
#define FMC_SDCMR_MRD(n) ((n) << FMC_SDCMR_MRD_SHIFT) /* SDRAM Mode Register */
# define FMC_SDCMR_MRD_BURST_LENGTH_1 FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_BURST_LENGTH_2 FMC_SDCMR_MRD(0x0001)
# define FMC_SDCMR_MRD_BURST_LENGTH_4 FMC_SDCMR_MRD(0x0002)
# define FMC_SDCMR_MRD_BURST_LENGTH_8 FMC_SDCMR_MRD(0x0004)
# define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED FMC_SDCMR_MRD(0x0008)
# define FMC_SDCMR_MRD_CAS_LATENCY_2 FMC_SDCMR_MRD(0x0020)
# define FMC_SDCMR_MRD_CAS_LATENCY_3 FMC_SDCMR_MRD(0x0030)
# define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE FMC_SDCMR_MRD(0x0200)
#define FMC_SDCMR_RESERVED (0x1ff << 23) /* reserved bits */
#define FMC_SDRTR_CRE (1 << 0)
#define FMC_SDRTR_COUNT_SHIFT (1)
#define FMC_SDRTR_COUNT_MASK FMC_SDRTR_COUNT(0x1fff)
#define FMC_SDRTR_COUNT(val) ((val) << FMC_SDRTR_COUNT_SHIFT)
#define FMC_SDRTR_REIE (14 << 0)
#define FMC_SDSR_RE (1 << 0)
#define FMC_SDSR_MODES1_SHIFT (1)
#define FMC_SDSR_MODES1_MASK FMC_SDSR_MODES1(3)
#define FMC_SDSR_MODES1(n) ((n) << FMC_SDSR_MODES1_SHIFT)
# define FMC_SDSR_MODES1_NORMAL FMC_SDSR_MODES1(FMC_SDSR_MODES_NORMAL)
# define FMC_SDSR_MODES1_SELF_REFRESH FMC_SDSR_MODES1(FMC_SDSR_MODES_SELF_REFRESH)
# define FMC_SDSR_MODES1_POWER_DOWN FMC_SDSR_MODES1(FMC_SDSR_MODES_POWER_DOWN)
#define FMC_SDSR_MODES2_SHIFT (3)
#define FMC_SDSR_MODES2_MASK FMC_SDSR_MODES2(3)
#define FMC_SDSR_MODES2(n) ((n) << FMC_SDSR_MODES2_SHIFT)
# define FMC_SDSR_MODES2_NORMAL FMC_SDSR_MODES2(FMC_SDSR_MODES_NORMAL)
# define FMC_SDSR_MODES2_SELF_REFRESH FMC_SDSR_MODES2(FMC_SDSR_MODES_SELF_REFRESH)
# define FMC_SDSR_MODES2_POWER_DOWN FMC_SDSR_MODES2(FMC_SDSR_MODES_POWER_DOWN)
#define FMC_SDSR_MODES_NORMAL (0)
#define FMC_SDSR_MODES_SELF_REFRESH (1)
#define FMC_SDSR_MODES_POWER_DOWN (2)
#define FMC_SDSR_BUSY (1 << 5)
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FMC_H */

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@ -0,0 +1,234 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_fmc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_FMC)
#include <debug.h>
#include <nuttx/arch.h>
#include "chip.h"
#include "arm_arch.h"
#include "stm32_fmc.h"
#include "stm32_rcc.h"
/****************************************************************************
* Private data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_fmc_sdram_wait
*
* Description:
* Wait for the SDRAM controller to be ready.
*
****************************************************************************/
static void stm32_fmc_sdram_wait(void)
{
int timeout = 0xffff;
while (timeout > 0)
{
if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
{
break;
}
timeout--;
}
DEBUGASSERT(timeout > 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_fmc_init
*
* Description:
* Initialize the FMC peripheral.
*
****************************************************************************/
void stm32_fmc_init(void)
{
uint32_t regval;
/* Reset the FMC on the AHB3 bus */
regval = getreg32(STM32_RCC_AHB3RSTR);
regval |= RCC_AHB3RSTR_FMCRST;
putreg32(regval, STM32_RCC_AHB3RSTR);
/* Leave reset state */
regval &= ~RCC_AHB3RSTR_FMCRST;
putreg32(regval, STM32_RCC_AHB3RSTR);
}
/****************************************************************************
* Name: stm32_fmc_sdram_write_protect
*
* Description:
* Enable/Disable writes to an SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_write_protect(int bank, bool state)
{
uint32_t val;
uint32_t sdcr;
DEBUGASSERT(bank == 1 || bank == 2);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
val = getreg32(sdcr);
if (state)
{
val |= FMC_SDCR_WP; /* wp == 1 */
}
else
{
val &= ~FMC_SDCR_WP; /* wp == 0 */
}
putreg32(val, sdcr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_refresh_rate
*
* Description:
* Set the SDRAM refresh rate.
*
****************************************************************************/
void stm32_fmc_sdram_set_refresh_rate(int count)
{
uint32_t val;
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDRTR);
val &= ~(0x1fff << 1); /* preserve non-count bits */
val |= (count << 1);
putreg32(val, STM32_FMC_SDRTR);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
* Set the SDRAM timing parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
uint32_t val;
uint32_t sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
val = getreg32(sdtr);
val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
val |= timing;
putreg32(val, sdtr);
}
/****************************************************************************
* Name: stm32_fmc_enable
*
* Description:
* Enable FMC SDRAM. Do this after issue refresh rate.
*
****************************************************************************/
void stm32_fmc_sdram_enable(void)
{
uint32_t val;
val = FMC_BCR_FMCEN | getreg32(STM32_FMC_BCR1);
putreg32(val, STM32_FMC_BCR1);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
* Set the SDRAM control parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
uint32_t val;
uint32_t sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
val = getreg32(sdcr);
val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
val |= ctrl;
putreg32(val, sdcr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_command
*
* Description:
* Send a command to the SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_command(uint32_t cmd)
{
uint32_t val;
DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
/* Wait for the controller to be ready */
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDCMR);
val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */
val |= cmd;
putreg32(val, STM32_FMC_SDCMR);
}
#endif /* CONFIG_STM32F7_FMC */

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arch/arm/src/stm32f7/stm32_fmc.h
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@ -1,411 +1,125 @@
/*****************************************************************************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/stm32_fmc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_FMC_H
#define __ARCH_ARM_SRC_STM32F7_STM32_FMC_H
/*****************************************************************************************************************************************************
/****************************************************************************
* Included Files
*****************************************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/stm32_fmc.h"
/*****************************************************************************************************************************************************
* Pre-processor Definitions
*****************************************************************************************************************************************************/
#ifndef __ASSEMBLY__
/* Register Offsets **********************************************************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
/****************************************************************************
* Name: stm32_fmc_init
*
* Description:
* Initialize the FMC peripheral.
*
****************************************************************************/
#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
void stm32_fmc_init(void);
#define STM32_FMC_PCR_OFFSET 0x0080 /* NAND Flash control register */
/****************************************************************************
* Name: stm32_fmc_sdram_write_protect
*
* Description:
* Enable/Disable writes to an SDRAM.
*
****************************************************************************/
#define STM32_FMC_SR_OFFSET 0x0084 /* FIFO status and interrupt register */
void stm32_fmc_sdram_write_protect(int bank, bool state);
#define STM32_FMC_PMEM_OFFSET 0x0088 /* Common memory space timing register */
/****************************************************************************
* Name: stm32_fmc_sdram_set_refresh_rate
*
* Description:
* Set the SDRAM refresh rate.
*
****************************************************************************/
#define STM32_FMC_PATT_OFFSET 0x008c /* Attribute memory space timing register */
void stm32_fmc_sdram_set_refresh_rate(int count);
#define STM32_FMC_ECCR_OFFSET 0x0094 /* ECC result register */
/****************************************************************************
* Name: stm32_fmc_sdram_enable
*
* Description:
* Enable FMC SDRAM. Do this after issue refresh rate.
*
****************************************************************************/
#define STM32_FMC_SDCR_OFFSET(n) (4*((n)-1)+0x0140)
#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */
#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
void stm32_fmc_sdram_enable(void);
#define STM32_FMC_SDTR_OFFSET(n) (4*((n)-1)+0x0148)
#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
* Set the SDRAM timing parameters.
*
****************************************************************************/
#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Command mode register */
#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing);
/* Register Addresses ********************************************************************************************************************************/
/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
* Set the SDRAM control parameters.
*
****************************************************************************/
#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl);
#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
/****************************************************************************
* Name: stm32_fmc_sdram_command
*
* Description:
* Send a command to the SDRAM.
*
****************************************************************************/
#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
void stm32_fmc_sdram_command(uint32_t cmd);
#define STM32_FMC_PCR (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET)
#define STM32_FMC_SR (STM32_FMC_BASE+STM32_FMC_SR_OFFSET)
#define STM32_FMC_PMEM (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET)
#define STM32_FMC_PATT (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET)
#define STM32_FMC_ECCR (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET)
#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
/* Register Bitfield Definitions *********************************************************************************************************************/
#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID32 (2 << FMC_BCR_MWID_SHIFT)
#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#define FMC_BCR_CPSIZE_SHIFT (16)
#define FMC_BCR_CPSIZE_MASK (7 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE0 (0 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE128 (1 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE256 (2 << FMC_BCR_CPSIZE_SHIFT)
# define FMC_BCR_CPSIZE1024 (3 << FMC_BCR_CPSIZE_SHIFT)
#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FMC_BCR_CCLKEN (1 << 20) /* Continuous Clock Enable */
#define FMC_BCR_WFDIS (1 << 21) /* Write FIFO Disable */
#define FMC_BCR_BMAP_SHIFT (24)
#define FMC_BCR_BMAP_MASK (3 << FMC_BCR_BMAP_SHIFT)
# define FMC_BCR_BMAP0 (0 << FMC_BCR_BMAP_SHIFT) /* Default mapping */
# define FMC_BCR_BMAP1 (1 << FMC_BCR_BMAP_SHIFT) /* NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped */
# define FMC_BCR_BMAP2 (2 << FMC_BCR_BMAP_SHIFT) /* SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping */
#define FMC_BCR_FMCEN (1 << 31) /* FMC controller Enable */
#define FMC_BCR_RSTVALUE(n) ((n == 0) ? 0x000030db : 0x000030d2) /* Reset value for BCR */
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT)/* (n)xHCLK n=1..16 */
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT)
/* (n)xHCLK n=2..17 */
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
#define FMC_BTR_RSTVALUE 0xffffffff
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT)/* (n)xHCLK n=1..16 */
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT)/* (n)xHCLK n=2..16 */
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT)/* (n)xHCLK n=2..256 */
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT)/* (n)xHCLK n=2..16 */
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT)/* (n)xHCLK n=2..17 */
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODD (3 << FMC_BWTR_ACCMOD_SHIFT)
#define FMC_PCR_RSTVALUE (0x00000018)
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FMC_PMEM_RSTVALUE (0xfcfcfcfc)
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT)/* (n)xHCLK n=1..256 */
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
# define FMC_PMEM_MEMWAIT(n) ((n-1)<<FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT)/* (n)xHCLK n=1..255 */
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT)/* (n)xHCLK n=1..256 */
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
# define FMC_PATT_ATTWAIT(n) ((n-1)<<FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT)/* (n)xHCLK n=1..255 */
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
# define FMC_SDCR_COLBITS_SHIFT (0)
# define FMC_SDCR_COLBITS_MASK (3 << FMC_SDCR_COLBITS_SHIFT)
# define FMC_SDCR_COLBITS_8 0x00000000
# define FMC_SDCR_COLBITS_9 0x00000001
# define FMC_SDCR_COLBITS_10 0x00000002
# define FMC_SDCR_COLBITS_11 0x00000003
# define FMC_SDCR_ROWBITS_SHIFT (2)
# define FMC_SDCR_ROWBITS_MASK (3 << FMC_SDCR_ROWBITS_SHIFT)
# define FMC_SDCR_ROWBITS_11 0x00000000
# define FMC_SDCR_ROWBITS_12 0x00000004
# define FMC_SDCR_ROWBITS_13 0x00000008
# define FMC_SDCR_WIDTH_SHIFT (4)
# define FMC_SDCR_WIDTH_MASK (3 << FMC_SDCR_WIDTH_SHIFT)
# define FMC_SDCR_WIDTH_8 0x00000000
# define FMC_SDCR_WIDTH_16 0x00000010
# define FMC_SDCR_WIDTH_32 0x00000020
# define FMC_SDCR_BANKS_SHIFT (6)
# define FMC_SDCR_BANKS_MASK (1 << FMC_SDCR_BANKS_SHIFT)
# define FMC_SDCR_BANKS_2 0x00000000
# define FMC_SDCR_BANKS_4 0x00000040
# define FMC_SDCR_CASLAT_SHIFT (7)
# define FMC_SDCR_CASLAT_MASK (3 << FMC_SDCR_CASLAT_SHIFT)
# define FMC_SDCR_CASLAT_1 0x00000080
# define FMC_SDCR_CASLAT_2 0x00000100
# define FMC_SDCR_CASLAT_3 0x00000180
# define FMC_SDCR_WP 0x00000200
# define FMC_SDCR_SDCLK_SHIFT (10)
# define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT)
# define FMC_SDCR_SDCLK_DISABLE 0x00000000
# define FMC_SDCR_SDCLK_2X 0x00000800
# define FMC_SDCR_SDCLK_3X 0x00000C00
# define FMC_SDCR_BURST_READ 0x00001000
# define FMC_SDCR_RPIPE_SHIFT (13)
# define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT)
# define FMC_SDCR_RPIPE_0 0x00000000
# define FMC_SDCR_RPIPE_1 0x00002000
# define FMC_SDCR_RPIPE_2 0x00004000
#define FMC_SDCR_RESERVED (0x1FFFF << 15) /* reserved bits */
#define FMC_SDTR_TMRD_SHIFT (0)
#define FMC_SDTR_TMRD_MASK FMC_SDTR_TMRD(16)
#define FMC_SDTR_TMRD(n) (((n)-1)<<FMC_SDTR_TMRD_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TXSR_SHIFT (4)
#define FMC_SDTR_TXSR_MASK FMC_SDTR_TXSR(16)
#define FMC_SDTR_TXSR(n) (((n)-1) << FMC_SDTR_TXSR_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_TRAS_SHIFT (8)
#define FMC_SDTR_TRAS_MASK FMC_SDTR_TRAS(16)
#define FMC_SDTR_TRAS(n) (((n)-1) << FMC_SDTR_TRAS_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_TRC_SHIFT (12)
#define FMC_SDTR_TRC_MASK FMC_SDTR_TRC(16)
#define FMC_SDTR_TRC(n) (((n)-1) << FMC_SDTR_TRC_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TWR_SHIFT (16)
#define FMC_SDTR_TWR_MASK FMC_SDTR_TWR(16)
#define FMC_SDTR_TWR(n) (((n)-1) << FMC_SDTR_TWR_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TRP_SHIFT (20)
#define FMC_SDTR_TRP_MASK FMC_SDTR_TRP(16)
#define FMC_SDTR_TRP(n) (((n)-1) << FMC_SDTR_TRP_SHIFT) /* 1 to 16 cycles */
#define FMC_SDTR_TRCD_SHIFT (24)
#define FMC_SDTR_TRCD_MASK FMC_SDTR_TRCD(16)
#define FMC_SDTR_TRCD(n) (((n)-1) << FMC_SDTR_TRCD_SHIFT)/* 1 to 16 cycles */
#define FMC_SDTR_RESERVED (0xF << 28) /* reserved bits */
#define FMC_SDCMR_MODE_SHIFT (0)
#define FMC_SDCMR_MODE_MASK (7 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_NORMAL (0 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_CLK_ENABLE (1 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_PALL (2 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_AUTO_REFRESH (3 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_LOAD_MODE (4 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_SELF_REFRESH (5 << FMC_SDCMR_MODE_SHIFT)
# define FMC_SDCMR_MODE_POWER_DOWN (6 << FMC_SDCMR_MODE_SHIFT)
#define FMC_SDCMR_CTB2 (1 << 3)
#define FMC_SDCMR_CTB1 (1 << 4)
#define FMC_SDCMR_NRFS_SHIFT (5)
#define FMC_SDCMR_NRFS(n) (((n)-1)<<FMC_SDCMR_NRFS_SHIFT) /* 1 to 16 cycles */
#define FMC_SDCMR_MRD_SHIFT (9)
#define FMC_SDCMR_MRD_MASK FMC_SDCMR_MRD(16383)
#define FMC_SDCMR_MRD(n) ((n) << FMC_SDCMR_MRD_SHIFT) /* SDRAM Mode Register */
# define FMC_SDCMR_MRD_BURST_LENGTH_1 FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_BURST_LENGTH_2 FMC_SDCMR_MRD(0x0001)
# define FMC_SDCMR_MRD_BURST_LENGTH_4 FMC_SDCMR_MRD(0x0002)
# define FMC_SDCMR_MRD_BURST_LENGTH_8 FMC_SDCMR_MRD(0x0004)
# define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED FMC_SDCMR_MRD(0x0008)
# define FMC_SDCMR_MRD_CAS_LATENCY_2 FMC_SDCMR_MRD(0x0020)
# define FMC_SDCMR_MRD_CAS_LATENCY_3 FMC_SDCMR_MRD(0x0030)
# define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED FMC_SDCMR_MRD(0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE FMC_SDCMR_MRD(0x0200)
#define FMC_SDCMR_RESERVED (0x1ff << 23) /* reserved bits */
#define FMC_SDRTR_CRE (1 << 0)
#define FMC_SDRTR_COUNT_SHIFT (1)
#define FMC_SDRTR_COUNT_MASK FMC_SDRTR_COUNT(0x1fff)
#define FMC_SDRTR_COUNT(val) ((val) << FMC_SDRTR_COUNT_SHIFT)
#define FMC_SDRTR_REIE (14 << 0)
#define FMC_SDSR_RE (1 << 0)
#define FMC_SDSR_MODES1_SHIFT (1)
#define FMC_SDSR_MODES1_MASK FMC_SDSR_MODES1(3)
#define FMC_SDSR_MODES1(n) ((n) << FMC_SDSR_MODES1_SHIFT)
# define FMC_SDSR_MODES1_NORMAL FMC_SDSR_MODES1(FMC_SDSR_MODES_NORMAL)
# define FMC_SDSR_MODES1_SELF_REFRESH FMC_SDSR_MODES1(FMC_SDSR_MODES_SELF_REFRESH)
# define FMC_SDSR_MODES1_POWER_DOWN FMC_SDSR_MODES1(FMC_SDSR_MODES_POWER_DOWN)
#define FMC_SDSR_MODES2_SHIFT (3)
#define FMC_SDSR_MODES2_MASK FMC_SDSR_MODES2(3)
#define FMC_SDSR_MODES2(n) ((n) << FMC_SDSR_MODES2_SHIFT)
# define FMC_SDSR_MODES2_NORMAL FMC_SDSR_MODES2(FMC_SDSR_MODES_NORMAL)
# define FMC_SDSR_MODES2_SELF_REFRESH FMC_SDSR_MODES2(FMC_SDSR_MODES_SELF_REFRESH)
# define FMC_SDSR_MODES2_POWER_DOWN FMC_SDSR_MODES2(FMC_SDSR_MODES_POWER_DOWN)
#define FMC_SDSR_MODES_NORMAL (0)
#define FMC_SDSR_MODES_SELF_REFRESH (1)
#define FMC_SDSR_MODES_POWER_DOWN (2)
#define FMC_SDSR_BUSY (1 << 5)
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_FMC_H */

133
boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c
View File

@ -100,135 +100,6 @@ static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_fmc_sdram_wait
*
* Description:
* Wait for the SDRAM controller to be ready.
*
****************************************************************************/
static void stm32_fmc_sdram_wait(void)
{
int timeout = 0xffff;
while (timeout > 0)
{
if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
{
break;
}
timeout--;
}
DEBUGASSERT(timeout > 0);
}
/****************************************************************************
* Name: stm32_fmc_enable
*
* Description:
* Enable clocking to the FMC.
*
****************************************************************************/
static void stm32_fmc_enable(void)
{
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_refresh_rate
*
* Description:
* Set the SDRAM refresh rate.
*
****************************************************************************/
static void stm32_fmc_sdram_set_refresh_rate(int count)
{
uint32_t val;
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDRTR);
val &= ~(0x1fff << 1); /* preserve non-count bits */
val |= (count << 1);
putreg32(val, STM32_FMC_SDRTR);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
* Set the SDRAM timing parameters.
*
****************************************************************************/
static void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
uint32_t val;
uint32_t sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
val = getreg32(sdtr);
val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
val |= timing;
putreg32(val, sdtr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
* Set the SDRAM control parameters.
*
****************************************************************************/
static void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
uint32_t val;
uint32_t sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
val = getreg32(sdcr);
val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
val |= ctrl;
putreg32(val, sdcr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_command
*
* Description:
* Send a command to the SDRAM.
*
****************************************************************************/
static void stm32_fmc_sdram_command(uint32_t cmd)
{
uint32_t val;
DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
/* Wait for the controller to be ready */
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDCMR);
val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */
val |= cmd;
putreg32(val, STM32_FMC_SDCMR);
}
/****************************************************************************
* Name: stm32_extmemgpios
*
@ -271,9 +142,9 @@ void stm32_sdram_initialize(void)
stm32_extmemgpios(g_addressconfig, STM32_FMC_NADDRCONFIGS);
stm32_extmemgpios(g_dataconfig, STM32_FMC_NDATACONFIGS);
/* Enable AHB clocking to the FMC */
/* Initialize the FMC peripheral */
stm32_fmc_enable();
stm32_fmc_init();
/* Configure and enable the SDRAM bank1
*