arch: z80: nxstyle fixes
nxstyle fixes to pass CI Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
David Sidrane
parent
4802b096c5
commit
106a471ef1
@ -22,7 +22,7 @@
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#define __ARCH_Z80_INCLUDE_LIMITS_H
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/****************************************************************************
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* Pre-processor Definitions
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* Included Files
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****************************************************************************/
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#include <arch/chip/limits.h>
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@ -19,7 +19,7 @@
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through sys/types.h
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* through sys/types.h
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*/
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#ifndef __ARCH_Z80_INCLUDE_TYPES_H
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@ -42,11 +42,13 @@
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* The z180 address environment is represented in hardware as the 8-bit
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* Common Base Register (CBR). CBR specifies the base address (on 4KB
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* boundaries) used to generate a 20-bit physical address for Common Area 1
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* accesses. CBR is the upper 8-bits of the 20-bit address; the lower 14-bits
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* of the base address are implicitly zero (hence the 4KB boundary alignment).
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* accesses. CBR is the upper 8-bits of the 20-bit address; the lower
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* 14-bits of the base address are implicitly zero (hence the 4KB boundary
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* alignment).
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*/
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#ifdef CONFIG_ARCH_ADDRENV
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@ -43,6 +43,7 @@
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#define Z180_S_FLAG 0x80 /* Bit 7: Sign flag */
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/* Z180 Chip Definitions ****************************************************/
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/* Z800180
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*
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* The 8-bit Z80180 MPU provides the benefits of reduced system costs and
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@ -121,10 +122,10 @@
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */
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#elif defined(CONFIG_ARCH_CHIP_Z8018000XSO)
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defined(CONFIG_ARCH_CHIP_Z8018010FEG)
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defined(CONFIG_ARCH_CHIP_Z8018000WSO)
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defined(CONFIG_ARCH_CHIP_Z8018008PEG)
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#elif defined(CONFIG_ARCH_CHIP_Z8018000XSO)|| \
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defined(CONFIG_ARCH_CHIP_Z8018010FEG)|| \
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defined(CONFIG_ARCH_CHIP_Z8018000WSO)|| \
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defined(CONFIG_ARCH_CHIP_Z8018008PEG)||
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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@ -146,10 +147,11 @@
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/* Z80181
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*
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* The Z80181 SAC Smart Access Controller is an 8-bit CMOS microprocessor that
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* combines a Z180-compatible MPU, one channel of the Z85C30 Serial Communications
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* Controller, a Z80 CTC, two 8-bit general-purpose parallel ports, and two Chip
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* Select signals, into a single 100-pin Quad Flat Pack package.
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* The Z80181 SAC Smart Access Controller is an 8-bit CMOS microprocessor
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* that combines a Z180-compatible MPU, one channel of the Z85C30 Serial
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* Communications Controller, a Z80 CTC, two 8-bit general-purpose parallel
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* ports, and two Chip Select signals, into a single 100-pin Quad Flat Pack
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* package.
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*
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* Z80181 Features
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*
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@ -187,11 +189,11 @@
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/* Z80182
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*
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* The Z80182 and Z8L182 MPUs are smart peripheral controller ICs for modems, fax,
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* voice messaging, and other communications applications. It uses the Z80180
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* microprocessor linked with two channels of the industry-standard Z85230 ESCC,
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* 24 bits of parallel I/O, and a 16550 MIMIC for direct connection to the IBM PC,
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* XT, or AT bus
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* The Z80182 and Z8L182 MPUs are smart peripheral controller ICs for modems,
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* fax, voice messaging, and other communications applications. It uses the
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* Z80180 microprocessor linked with two channels of the industry-standard
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* Z85230 ESCC, 24 bits of parallel I/O, and a 16550 MIMIC for direct
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* connection to the IBM PC, XT, or AT bus
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*
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* Z80182 Features
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*
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@ -203,7 +205,8 @@
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* Clock Serial I/O
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* Power-Down Mode
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* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options
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* Enhanced Serial Communication Controller (ESCC) (2 Channels) with 32-Bit CRC
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* Enhanced Serial Communication Controller (ESCC)
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* (2 Channels) with 32-Bit CRC
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* 16550 MIMIC
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* 24 Parallel I/O
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* 3.3 V and 5 V Version
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@ -235,11 +238,12 @@
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/* Z80195
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*
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* The Z80195 MPU is a smart peripheral controller device designed for general data
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* communications applications, and architected specifically to accommodate all
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* input and output (I/O) requirements for serial and parallel connectivity.
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* Combining a high-performance CPU core with a variety of system and I/O
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* resources, the Z80195 is useful in a broad range of applications.
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* The Z80195 MPU is a smart peripheral controller device designed for
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* general data communications applications, and architected specifically
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* to accommodate all input and output (I/O) requirements for serial and
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* parallel connectivity. Combining a high-performance CPU core with a
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* variety of system and I/O resources, the Z80195 is useful in a broad
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* range of applications.
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*
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* Z80195 Features
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*
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@ -277,10 +281,10 @@
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/* Z8L180
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*
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models,
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* while still providing full backward compatibility with existing ZiLOG Z80
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* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving
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* modes, and EMI noise reduction.
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180
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* models, while still providing full backward compatibility with existing
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* ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds,
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* power-saving modes, and EMI noise reduction.
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*
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* Z8L180 Features
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*
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@ -322,12 +326,12 @@
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/* Z8L182
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*
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* The Z80182/Z8L182 is a smart peripheral controller IC for modem (in particular
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* V. Fast applications), fax, voice messaging and other communications
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* applications. It uses the Z80180 microprocessor (Z8S180 MPU core) linked with
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* two channels of the industry standard Z85230 ESCC (Enhanced Serial
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* Communications Controller), 24 bits of parallel I/O, and a 16550 MIMIC for
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* direct connection to the IBM PC, XT, AT bus.
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* The Z80182/Z8L182 is a smart peripheral controller IC for modem (in
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* particular V. Fast applications), fax, voice messaging and other
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* communications applications. It uses the Z80180 microprocessor (Z8S180
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* MPU core) linked with two channels of the industry standard Z85230 ESCC
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* (Enhanced Serial Communications Controller), 24 bits of parallel I/O,
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* and a 16550 MIMIC for direct connection to the IBM PC, XT, AT bus.
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*
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* Z8L182 Features
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*
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@ -369,14 +373,14 @@
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/* Z8SL180
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*
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models,
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* while still providing full backward compatibility with existing ZiLOG Z80
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* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving
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* modes, and EMI noise reduction.This enhanced Z180 design also incorporates
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* additional feature enhancements to the ASCIs, DMAs, and STANDBY mode power
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* consumption. With the addition of ESCC-like Baud Rate Generators (BRGs), the
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* two ASCIs offer the flexibility and capability to transfer data
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* asynchronously at rates of up to 512 Kbps.
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180
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* models, while still providing full backward compatibility with existing
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* ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds,
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* power-saving modes, and EMI noise reduction.This enhanced Z180 design
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* also incorporates additional feature enhancements to the ASCIs, DMAs,
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* and STANDBY mode power consumption. With the addition of ESCC-like
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* Baud Rate Generators (BRGs), the two ASCIs offer the flexibility and
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* capability to transfer data asynchronously at rates of up to 512 Kbps.
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*
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* Z8S180 Features
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*
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@ -38,7 +38,9 @@
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****************************************************************************/
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/* Z180 Interrupts */
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/* Resets */
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/* RST 0 is the power-up interrupt vector */
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#define Z180_RST1 (0) /* RST 1 */
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#define Z180_RST2 (1) /* RST 2 */
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@ -579,7 +579,9 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
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else if (regval == I2C_SR_MDATARDNAK)
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{
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/* Since we just NACKed the incoming byte, it must be the last */
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/* Since we just NACKed the incoming byte, it must be the
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* last
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*/
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DEBUGASSERT(count <= 1);
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@ -925,7 +927,9 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
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ccr = ez80_i2c_getccr(100 * 1000);
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ez80_i2c_setccr(ccr);
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/* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */
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/* No GPIO setup is required -- I2C pints,
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* SCL/SDA are not multiplexed
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*/
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/* This semaphore enforces serialized access for I2C transfers */
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@ -673,7 +673,9 @@ void z80_serial_initialize(void)
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/* Configure pins for usage of UARTs */
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#ifdef CONFIG_EZ80_UART0
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/* Set Port D, pins 0 and 1 for their alternate function (Mode 7) to enable UART0 */
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/* Set Port D, pins 0 and 1 for their alternate function (Mode 7)
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* to enable UART0
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*/
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regval = inp(EZ80_PD_DDR);
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regval |= 3;
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@ -689,7 +691,9 @@ void z80_serial_initialize(void)
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#endif
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#ifdef CONFIG_EZ80_UART1
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/* Set Port C, pins 0 and 1 for their alternate function (Mode 7) to enable UART1 */
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/* Set Port C, pins 0 and 1 for their alternate function (Mode 7)
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* to enable UART1
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*/
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regval = inp(EZ80_PC_DDR);
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regval |= 3;
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@ -743,7 +747,7 @@ int up_putc(int ch)
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if (ch == '\n')
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{
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/* Output CR before LF*/
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/* Output CR before LF */
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ez80_waittxready(priv);
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ez80_serialout(priv, EZ80_UART_THR, '\r');
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@ -207,7 +207,8 @@ void z180_restoreusercontext(FAR chipreg_t *regs);
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/* Defined in z180_sigsetup.c */
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void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
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void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver,
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FAR chipreg_t *regs);
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/* Defined in z180_registerdump.c */
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@ -34,6 +34,7 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Verify that selected features match the capability of the selected CPU */
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#ifndef HAVE_Z8X181
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@ -111,9 +112,9 @@
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# undef CONFIG_Z180_ESCCA_SERIAL_CONSOLE
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# undef CONFIG_Z180_ESCCB_SERIAL_CONSOLE
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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# ifndef USE_SERIALDRIVER
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# undef CONFIG_Z180_UART1
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@ -126,15 +127,15 @@
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# define HAVE_UART_CONSOLE 1
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# define HAVE_SERIAL_CONSOLE 1
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/* Disable other console selections */
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/* Disable other console selections */
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# undef CONFIG_Z180_SCC_SERIAL_CONSOLE
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# undef CONFIG_Z180_ESCCA_SERIAL_CONSOLE
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# undef CONFIG_Z180_ESCCB_SERIAL_CONSOLE
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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# ifndef USE_SERIALDRIVER
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# undef CONFIG_Z180_UART0
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@ -147,14 +148,14 @@
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# define HAVE_SCC_CONSOLE 1
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# define HAVE_SERIAL_CONSOLE 1
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/* Disable other console selections */
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/* Disable other console selections */
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# undef CONFIG_Z180_ESCCA_SERIAL_CONSOLE
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# undef CONFIG_Z180_ESCCB_SERIAL_CONSOLE
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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# ifndef USE_SERIALDRIVER
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# undef CONFIG_Z180_UART0
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@ -167,13 +168,13 @@
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# define HAVE_SCC_CONSOLE 1
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# define HAVE_SERIAL_CONSOLE 1
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/* Disable other console selections */
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/* Disable other console selections */
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# undef CONFIG_Z180_ESCCB_SERIAL_CONSOLE
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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# ifndef USE_SERIALDRIVER
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# undef CONFIG_Z180_UART0
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@ -182,17 +183,17 @@
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# undef CONFIG_Z180_ESCCB
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# endif
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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#elif defined(CONFIG_Z180_ESCCB_SERIAL_CONSOLE)
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# define HAVE_SCC_CONSOLE 1
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# define HAVE_SERIAL_CONSOLE 1
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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/* If we are not using the serial driver, then the serial console is all
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* that we will support.
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*/
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# ifndef USE_SERIALDRIVER
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# undef CONFIG_Z180_UART0
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@ -212,7 +213,7 @@
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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* Public Functions Prototypes
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************************************************************************************/
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#endif /* __ARCH_Z80_SRC_Z180_Z180_CONFIG_H */
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@ -61,7 +61,6 @@ void outp(char p, char c)
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__endasm;
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}
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/****************************************************************************
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* Name: inpb
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*
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@ -30,11 +30,13 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* These registers may be relocated to multiples of 0x40 by setting the IO Control
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* Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The configuration setting,
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* CONFIG_Z180_SFROFFSET, indicates that offset (but is not fully supported yet!)
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/* These registers may be relocated to multiples of 0x40 by setting the IO
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* Control Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The
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* configuration setting, CONFIG_Z180_SFROFFSET, indicates that offset
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* (but is not fully supported yet!)
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*/
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#ifdef CONFIG_Z180_SFROFFSET
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@ -44,6 +46,7 @@
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#endif
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/* Z180 Register Bit addresses ******************************************************/
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/* ASCI Registers */
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#define Z180_ASCI0_CNTLA (SFR_OFFSET+0x00) /* ASCI Control Register A Ch 0 */
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@ -105,6 +108,7 @@
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#define Z180_DMA1_MARB (SFR_OFFSET+0x2a) /* DMA Memory Address Register Ch 1B */
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#define Z180_DMA1_IARL (SFR_OFFSET+0x2b) /* DMA I/0 Address Register Ch 1L */
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#define Z180_DMA1_IARH (SFR_OFFSET+0x2c) /* DMA I/0 Address Register Ch 1H */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_DMA1_IARB (SFR_OFFSET+0x2d) /* DMA I/O Address Register Ch 1B */
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#endif
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@ -138,6 +142,7 @@
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#define Z180_ICR (SFR_OFFSET+0x3f) /* I/O Control Register */
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/* The following registers are not relocatable */
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/* Registers unique to Z8x181 class CPUs */
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#ifdef HAVE_Z8X181
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@ -241,10 +246,12 @@
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#endif
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/* [E]SCC Internal Register Definitions */
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/* Read Registers. The SCC contains eight read registers. To read the contents
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* of a register (rather than RR0), the program must first initialize a pointer
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* to WR0 in exactly the same manner as a write operation. The next I/O read
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* cycle will place the contents of the selected read registers onto the data bus
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/* Read Registers. The SCC contains eight read registers. To read the
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* contents of a register (rather than RR0), the program must first
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* initialize a pointer to WR0 in exactly the same manner as a write
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* operation. The next I/O read cycle will place the contents of the
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* selected read registers onto the data bus
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*/
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#define Z18X_SCC_RR0 0x00 /* Transmit and Receive buffer status and external status */
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@ -259,11 +266,12 @@
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#define Z18X_SCC_RR13 0x0d /* Upper byte of baud rate generator time constant */
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#define Z18X_SCC_RR15 0x0f /* External Status interrupt information */
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/* Write Registers. The SCC contains fifteen write registers that are programmed
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* to configure the operating modes of the channel. With the exception of WR0, programming
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* the write registers is a two step operation. The first operation is a pointer written to
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* WR0 that points to the selected register. The second operation is the actual control
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* word that is written into the register to configure the SCC channel
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/* Write Registers. The SCC contains fifteen write registers that are
|
||||
* programmed to configure the operating modes of the channel. With the
|
||||
* exception of WR0, programming the write registers is a two step operation.
|
||||
* The first operation is a pointer written to WR0 that points to the
|
||||
* selected register. The second operation is the actual control word that is
|
||||
* written into the register to configure the SCC channel
|
||||
*/
|
||||
|
||||
#define Z18X_SCC_WR0 0x00 /* Register Pointers, various initialization commands */
|
||||
@ -284,8 +292,11 @@
|
||||
#define Z18X_SCC_WR15 0x0f /* External status interrupt enable control */
|
||||
|
||||
/* Z180 Register Bit definitions ****************************************************/
|
||||
|
||||
/* ASCI Registers *******************************************************************/
|
||||
|
||||
/* ASCI Control Register A 0 (CNTLA0: 0x00) */
|
||||
|
||||
/* ASCI Control Register A 1 (CNTLA1: 0x01) */
|
||||
|
||||
#define ASCI_CNTRLA_MPE (0x80) /* Bit 7: Multi-Processor Mode Enable */
|
||||
@ -300,6 +311,7 @@
|
||||
#define ASCI_CNTRLA_MOD0 (0x01) /* Bit 0: Parity enabled */
|
||||
|
||||
/* ASCI Control Register B 0 (CNTLB0: 0x02) */
|
||||
|
||||
/* ASCI Control Register B 1 (CNTLB1: 0x03) */
|
||||
|
||||
#define ASCI_CNTRLB_MPBT (0x80) /* Bit 7: Multiprocessor Bit Transmit */
|
||||
@ -321,6 +333,7 @@
|
||||
# define ASCI_CNTRLB_SS_EXT (7 << ASCI_CNTRLB_SS_SHIFT) /* External clock */
|
||||
|
||||
/* ASCI Status Register 0 (STAT0: 0x04) */
|
||||
|
||||
/* ASCI Status Register 1 (STAT1: 0x05) */
|
||||
|
||||
#define ASCI_STAT_RFRF (0x80) /* Bit 7: Receive Data Register Full */
|
||||
@ -334,12 +347,20 @@
|
||||
#define ASCI_STAT_TIE (0x01) /* Bit 0: Transmit Interrupt Enable */
|
||||
|
||||
/* ASCI Transmit Data Register Ch. 0 (TDR0: 0x06) - 8-bit data */
|
||||
|
||||
/* ASCI Transmit Data Register Ch. 1 (TDR1: 0x07) - 8-bit data */
|
||||
|
||||
/* ASCI Receive Data Register Ch. 0 (RDR0: 0x08) - 8-bit data */
|
||||
|
||||
/* ASCI Receive Data Register Ch. 1 (RDR0: 0x09) - 8-bit data */
|
||||
|
||||
/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */
|
||||
/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */
|
||||
/* ASCI0 Extension Control Register (I/O Address: 0x12)
|
||||
* (Z8S180/L180-Class Processors Only)
|
||||
*/
|
||||
|
||||
/* ASCI1 Extension Control Register (I/O Address: 0x13)
|
||||
* (Z8S180/L180-Class Processors Only)
|
||||
*/
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define ASCI_ASEXT_RDRF (0x80) /* Bit 7: RDRF Interrupt Inhibit */
|
||||
@ -352,12 +373,24 @@
|
||||
# define ASCI_ASEXT_SNDBRK (0x80) /* Bit 0: Send Break */
|
||||
#endif
|
||||
|
||||
/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI0 Time Constant Low Register (I/O Address: 0x1a)
|
||||
* (Z8S180/L180-Class Processors Only) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* ASCI0 Time Constant High Register (I/O Address: 0x1b)
|
||||
* (Z8S180/L180-Class Processors Only) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c)
|
||||
* (Z8S180/L180-Class Processors Only) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* ASCI1 Time Constant High Register (I/O Address: 0x1d)
|
||||
* (Z8S180/L180-Class Processors Only) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* CSI/O Registers ******************************************************************/
|
||||
|
||||
/* CSI/O Control/Status Register (CNTR: 0x0a) */
|
||||
|
||||
#define CSIO_CNTR_EF (0x80) /* Bit 7: End Flag */
|
||||
@ -375,12 +408,17 @@
|
||||
# define CSIO_CNTR_DIV1280 (6 << CSIO_CNTR_SS_SHIFT) /* Divide Ratio: 1280 Baud: 3125 */
|
||||
# define CSIO_CNTR_EXT (7 << CSIO_CNTR_SS_SHIFT) /* External Clock input (less than 20) */
|
||||
/* Baud at Phi = 4 MHz */
|
||||
|
||||
/* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */
|
||||
|
||||
/* Timer Registers ******************************************************************/
|
||||
|
||||
/* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */
|
||||
|
||||
/* Timer Data Register 0H (TMDR0H: 0x0d) -- 8-bit data */
|
||||
|
||||
/* Timer Reload Register Channel 0L (RLDR0L: 0x0e) -- 8-bit data */
|
||||
|
||||
/* Timer Reload Register Channel 0H (RLDR0H: 0x0f) -- 8-bit data */
|
||||
|
||||
/* Programmable Reload Timer (PTR) Control Register (TCR: 0x10) */
|
||||
@ -395,18 +433,36 @@
|
||||
#define PRT_TCR_TDE0 (0x01) /* Bit 0: Timer 0 Down Count Enable */
|
||||
|
||||
/* Timer Data Register 1L (TMDR1L: 0x14) -- 8-bit data */
|
||||
|
||||
/* Timer Data Register 1H (TMDR1H: 0x15) -- 8-bit data */
|
||||
|
||||
/* Timer Reload Register Channel 1L (RLDR1L: 0x16) -- 8-bit data */
|
||||
|
||||
/* Timer Reload Register Channel 1H (RLDR1H: 0x17) -- 8-bit data */
|
||||
|
||||
/* Free Running counter (FRC: 0x18) -- 8-bit data */
|
||||
|
||||
/* DMA Registers ********************************************************************/
|
||||
/* DMA Destination Address Register Channel 0 (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data */
|
||||
/* DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
|
||||
/* DMA Memory Address Register Channel 1 (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data */
|
||||
/* DMA I/O Address Register Channel 1 (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data */
|
||||
|
||||
/* DMA I/O Address Register Ch. 1 (IAR1B: 0x2d) (Z8S180/L180-Class Processor Only) */
|
||||
/* DMA Destination Address Register Channel 0
|
||||
* (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* DMA Byte Count Register Channel 0
|
||||
* (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* DMA Memory Address Register Channel 1
|
||||
* (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* DMA I/O Address Register Channel 1
|
||||
* (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* DMA I/O Address Register Ch. 1
|
||||
* (IAR1B: 0x2d) (Z8S180/L180-Class Processor Only)
|
||||
*/
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define IAR1B_ALTCH (0x80) /* Bit 7: Alternating Channels */
|
||||
@ -422,7 +478,9 @@
|
||||
# define IAR1B_IO_PIA (7 << IAR1B_IO_SHIFT) /* DMA1 PIA27-20 (P1284) */
|
||||
#endif
|
||||
|
||||
/* DMA Byte Count Register Channel 1 (BCR1: I/O Address = 0x2e to 0x2f) -- 8-bit data */
|
||||
/* DMA Byte Count Register Channel 1
|
||||
* (BCR1: I/O Address = 0x2e to 0x2f) -- 8-bit data
|
||||
*/
|
||||
|
||||
/* DMA Status Register (DSTAT: 0x30) */
|
||||
|
||||
@ -442,12 +500,14 @@
|
||||
# define DMODE_DM_MEMDECR (1 << DMODE_DM_SHIFT) /* Memory with address decrement */
|
||||
# define DMODE_DM_MEM (2 << DMODE_DM_SHIFT) /* Memory with fixed address */
|
||||
# define DMODE_DM_IO (3 << DMODE_DM_SHIFT) /* I/O */
|
||||
|
||||
#define DMODE_SM_SHIFT (2) /* Bits 2-3: Source Mode Channel */
|
||||
#define DMODE_SM_MASK (3 << DMODE_SM_SHIFT)
|
||||
# define DMODE_SM_MEMINCR (0 << DMODE_SM_SHIFT) /* Memory with address increment */
|
||||
# define DMODE_SM_MEMDECR (1 << DMODE_SM_SHIFT) /* Memory with address decrement */
|
||||
# define DMODE_SM_MEM (2 << DMODE_SM_SHIFT) /* Memory with fixed address */
|
||||
# define DMODE_SM_IO (3 << DMODE_SM_SHIFT) /* I/O */
|
||||
|
||||
#define DMODE_MMODE (0x01) /* Bit 0: DMA Memory Mode Channel 0 */
|
||||
|
||||
/* DMA/WAIT Control Register (DCNTL: 0x32) */
|
||||
@ -468,7 +528,10 @@
|
||||
# define DCNTL_DIM_IO2MD (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */
|
||||
|
||||
/* System Control Registers *********************************************************/
|
||||
/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
/* Clock Multiplier Register (CMR: 0x1e)
|
||||
* (Z8S180/L180-Class Processors Only)
|
||||
*/
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define CMR_CMM (0x80) /* Bit 7: X2 Clock Multiplier Mode */
|
||||
@ -515,6 +578,7 @@
|
||||
# define RCR_CYC1 (2 << RCR_CYC_SHIFT)
|
||||
|
||||
/* MMU Common Base Register (CBR: 0x38) - 8-bit base address of Common Area 1 */
|
||||
|
||||
/* MMU Bank Base Register (BBR: 0x39) - 8-bit address of Bank area */
|
||||
|
||||
/* MMU Common/Bank Area Register (CBAR: 0x3a) */
|
||||
@ -542,12 +606,15 @@
|
||||
|
||||
#ifdef HAVE_Z8X181
|
||||
/* PIA Registers */
|
||||
|
||||
/* PIAn Data Direction and Data Registers */
|
||||
|
||||
# define PIA(n) (1 << (n))
|
||||
|
||||
/* CTC Registers */
|
||||
|
||||
/* CTC Channel Control/Vector Registers */
|
||||
|
||||
/* Control Bit Definitions */
|
||||
|
||||
# define CTC_IE (0x80) /* Bit 7: Interrupt Enable */
|
||||
@ -570,8 +637,11 @@
|
||||
/* SCC Registers -- See interface description below */
|
||||
|
||||
/* System Control Registers */
|
||||
|
||||
/* RAM Upper Boundary Address Register -- 8-bit address (A12-A19) */
|
||||
|
||||
/* RAM Lower Boundary Address Register -- 8-bit address (A12-A19) */
|
||||
|
||||
/* ROM Address Boundary Register -- 8-bit address (A12-A19) */
|
||||
|
||||
/* System Configuration Register */
|
||||
@ -587,6 +657,7 @@
|
||||
|
||||
#ifdef HAVE_Z8X182
|
||||
/* PIA Registers */
|
||||
|
||||
/* Pn Data Direction and Data Register */
|
||||
|
||||
# define PIA(n) (1 << (n))
|
||||
@ -605,11 +676,13 @@
|
||||
# define SCR_DC (0x01) /* Bit 0: Daisy Chain */
|
||||
|
||||
/* 16550 MIMIC Registers */
|
||||
|
||||
/* To be provided */
|
||||
|
||||
#endif
|
||||
|
||||
/* [E]SCC Internal Register Definitions *********************************************/
|
||||
|
||||
/* Read Registers */
|
||||
|
||||
/* RR0: Transmit and Receive buffer status and external status */
|
||||
@ -642,7 +715,10 @@
|
||||
#define RR3_TX (0x10) /* Bit 4: Tx IP */
|
||||
#define RR3_EXT (0x08) /* Bit 3: Ext/Status IP */
|
||||
|
||||
/* RR6: SDLC FIFO byte counter lower byte (only when enabled) -- 8-bit counter value */
|
||||
/* RR6: SDLC FIFO byte counter lower byte (only when enabled) --
|
||||
* 8-bit counter value
|
||||
*/
|
||||
|
||||
/* RR7: SDLC FIFO byte count and status (only when enabled) */
|
||||
|
||||
#define RR7_BC_SHIFT (0) /* Bits 0-5 : Upper 6-bits of counter */
|
||||
@ -651,6 +727,7 @@
|
||||
#define RR7_FOS (0x80) /* Bit 7: FIFO Overflow Status */
|
||||
|
||||
/* RR8: Receive buffer */
|
||||
|
||||
/* RR10: Miscellaneous status bits */
|
||||
|
||||
#define RR10_1MISS (0x80) /* Bit 7: One Clock Missing */
|
||||
@ -658,8 +735,13 @@
|
||||
#define RR10_SEND (0x10) /* Bit 4: Loop Sending */
|
||||
#define RR10_ON (0x02) /* Bit 1: On Loop */
|
||||
|
||||
/* RR12: Lower byte of baud rate generator time constant -- 8-bit time constant value */
|
||||
/* RR13: Upper byte of baud rate generator time constant -- 8-bit time constant value */
|
||||
/* RR12: Lower byte of baud rate generator time constant --
|
||||
* 8-bit time constant value
|
||||
*/
|
||||
|
||||
/* RR13: Upper byte of baud rate generator time constant --
|
||||
* 8-bit time constant value
|
||||
*/
|
||||
|
||||
/* RR15: External Status interrupt information */
|
||||
|
||||
@ -683,6 +765,7 @@
|
||||
# define WR0_CMD1_RXCRCRST (1 << WR0_CMD1_SHIFT); /* Reset Rx CRC Checker */
|
||||
# define WR0_CMD1_TXCRCRST (2 << WR0_CMD1_SHIFT); /* Reset Tx CRC Generator */
|
||||
# define WR0_CMD1_TXURRST (3 << WR0_CMD1_SHIFT); /* Reset Tx Underrun/EOM Latch */
|
||||
|
||||
#define WR0_CMD2_SHIFT (3) /* Bits 3-5: Command */
|
||||
#define WR0_CMD2_MASK (3 << WR0_CMD2_SHIFT);
|
||||
# define WR0_CMD2_NULL (0 << WR0_CMD2_SHIFT); /* Null Code */
|
||||
@ -693,6 +776,7 @@
|
||||
# define WR0_CMD2_TXPRST (5 << WR0_CMD2_SHIFT); /* Reset Tx Int Pending */
|
||||
# define WR0_CMD2_ERRRST (6 << WR0_CMD2_SHIFT); /* Error Reset */
|
||||
# define WR0_CMD2_IUSRST (7 << WR0_CMD2_SHIFT); /* Reset Highest IUS */
|
||||
|
||||
#define WR0_REG_SHIFT (0) /* Bits 0-2 : Register address */
|
||||
#define WR0_REG_MASK (7 << WR0_REG_SHIFT);
|
||||
|
||||
@ -707,6 +791,7 @@
|
||||
# define WR1_CMD_RXINT1ST (1 << WR1_CMD_SHIFT) /* Rx Int On First Character or Special Condition */
|
||||
# define WR1_CMD_RXINTALL (2 << WR1_CMD_SHIFT) /* Int On All Rx Characters or Special Condition */
|
||||
# define WR1_CMD_RXINTSPEC (3 << WR1_CMD_SHIFT) /* Rx Int On Special Condition Only */
|
||||
|
||||
#define WR1_PSPEC (0x04) /* Bit 2: Parity is Special Condition */
|
||||
#define WR1_TXIE (0x02) /* Bit 1: Tx Int Enable */
|
||||
#define WR1_EXTIE (0x01) /* Bit 0: Ext Int Enable */
|
||||
@ -721,6 +806,7 @@
|
||||
# define WR3_BPC_7 (1 << WR3_BPC_SHIFT) /* Rx 7 Bits/Character */
|
||||
# define WR3_BPC_6 (2 << WR3_BPC_SHIFT) /* Rx 6 Bits/Character */
|
||||
# define WR3_BPC_8 (3 << WR3_BPC_SHIFT) /* Rx 8 Bits/Character */
|
||||
|
||||
#define WR3_AE (0x20) /* Bit 5: Auto Enables */
|
||||
#define WR3_EHM (0x10) /* Bit 4: Enter Hunt Mode */
|
||||
#define WR3_RXCRCEN (0x08) /* Bit 3: Rx CRC Enable */
|
||||
@ -736,18 +822,21 @@
|
||||
# define WR4_CM_X16 (1 << WR4_CM_SHIFT) /* X16 Clock Mode */
|
||||
# define WR4_CM_X32 (2 << WR4_CM_SHIFT) /* X32 Clock Mode */
|
||||
# define WR4_CM_X64 (3 << WR4_CM_SHIFT) /* X64 Clock Mode */
|
||||
|
||||
#define WR4_SM_SHIFT (4) /* Bits 4-5: Sync mode */
|
||||
#define WR4_SM_MASK (3 << WR4_SM_SHIFT)
|
||||
# define WR4_SM_8BIT (0 << WR4_SM_SHIFT) /* 8-Bit Sync Character */
|
||||
# define WR4_SM_16BIT (1 << WR4_SM_SHIFT) /* 16-Bit Sync Character */
|
||||
# define WR4_SM_SDLC (2 << WR4_SM_SHIFT) /* SDLC Mode (01111110 Flag) */
|
||||
# define WR4_SM_EXT (3 << WR4_SM_SHIFT) /* External Sync Mode */
|
||||
|
||||
#define WR4_SB_SHIFT (2) /* Bits 2-3: Sync mode enables */
|
||||
#define WR4_SB_MASK (3 << WR4_SB_SHIFT)
|
||||
# define WR4_SB_SME (0 << WR4_SB_SHIFT) /* Sync Modes Enable */
|
||||
# define WR4_SB_STOP1 (1 << WR4_SB_SHIFT) /* 1 Stop Bit/Character */
|
||||
# define WR4_SB_STOP1p5 (2 << WR4_SB_SHIFT) /* 1 1/2 Stop Bits/Character */
|
||||
# define WR4_SB_STOP2 (3 << WR4_SB_SHIFT) /* 2 Stop Bits/Character */
|
||||
|
||||
#define WR4_PEO (0x02) /* Bit 1: Parity EVEN//ODD */
|
||||
#define WR4_PEN (0x01) /* Bit : Parity Enable */
|
||||
|
||||
@ -760,14 +849,20 @@
|
||||
# define WR5_TXBITS_7 (1 << WR5_TXBITS_SHIFT) /* Tx 7 Bits/Character */
|
||||
# define WR5_TXBITS_6 (2 << WR5_TXBITS_SHIFT) /* Tx 6 Bits/Character */
|
||||
# define WR5_TXBITS_8 (3 << WR5_TXBITS_SHIFT) /* Tx 8 Bits/Character */
|
||||
|
||||
#define WR5_SENDBRK (0x10) /* Bit 4: Send Break */
|
||||
#define WR5_TXEN (0x08) /* Bit 3: Tx Enable */
|
||||
#define WR5_CRC16 (0x04) /* Bit 2: /SDLC/CRC-16 */
|
||||
#define WR5_RTS (0x02) /* Bit 1: RTS */
|
||||
#define WR5_TXCRCEN (0x01) /* Bit 0: Tx CRC Enable */
|
||||
|
||||
/* WR6: Sync Character or SDLC address -- 8-bit Monosync, Bisync, or SDLC value */
|
||||
/* WR7: Sync Character or SDLC flag -- 8-bit Monosync, Bisync, or SDLC value */
|
||||
/* WR6: Sync Character or SDLC address --
|
||||
* 8-bit Monosync, Bisync, or SDLC value
|
||||
*/
|
||||
|
||||
/* WR7: Sync Character or SDLC flag --
|
||||
* 8-bit Monosync, Bisync, or SDLC value
|
||||
*/
|
||||
|
||||
#define WR7_SDLC_SYNC (0x7e)
|
||||
|
||||
@ -791,6 +886,7 @@
|
||||
# define WR9_RST_NONE (0 << WR9_RST_SHIFT) /* No Reset */
|
||||
# define WR9_RST_CHAN (2 << WR9_RST_SHIFT) /* Channel Reset */
|
||||
# define WR9_RST_HWRST (3 << WR9_RST_SHIFT) /* Force Hardware Reset */
|
||||
|
||||
#ifdef HAVE_Z8X182 /* ESCC only */
|
||||
# define WR9_INTACKEN (0x20) /* Bit 5: Software INTACK Enable */
|
||||
#endif
|
||||
@ -809,6 +905,7 @@
|
||||
# define WR10_NRZI (1 << WR10_NRZFM_SHIFT) /* NRZI */
|
||||
# define WR10_FM1 (2 << WR10_NRZFM_SHIFT) /* FM1 (Transition = 1) */
|
||||
# define WR10_FM0 (3 << WR10_NRZFM_SHIFT) /* FM0 (Transition = 0) */
|
||||
|
||||
#define WR10_ACTPOLL (0x10) /* Bit 4: Go Active On Poll */
|
||||
#define WR10_IDLE (0x08) /* Bit 3: Mark/Flag Idle */
|
||||
#define WR10_URABORT (0x04) /* Bit 2: Abort/Flag On Underrun */
|
||||
@ -824,12 +921,14 @@
|
||||
# define WR11_RCLK_TRXC (1 << WR11_RCLK_SHIFT) /* Receive Clock = /TRxC Pin */
|
||||
# define WR11_RCLK_BRG (2 << WR11_RCLK_SHIFT) /* Receive Clock = BR Generator Output */
|
||||
# define WR11_RCLK_DPLL (3 << WR11_RCLK_SHIFT) /* Receive Clock = DPLL Output */
|
||||
|
||||
#define WR11_TCLK_SHIFT (3) /* Bits 3-4: Transmit Clock */
|
||||
#define WR11_TCLK_MASK (3 << WR11_TCLK_SHIFT)
|
||||
# define WR11_TCLK_RTXC (0 << WR11_TCLK_SHIFT) /* Transmit Clock = /RTxC Pin */
|
||||
# define WR11_TCLK_TRXC (1 << WR11_TCLK_SHIFT) /* Transmit Clock = /TRxC Pin */
|
||||
# define WR11_TCLK_BRG (2 << WR11_TCLK_SHIFT) /* Transmit Clock = BR Generator Output */
|
||||
# define WR11_TCLK_DPLL (3 << WR11_TCLK_SHIFT) /* Transmit Clock = DPLL Output */
|
||||
|
||||
#define WR11_TRXCIO (0x04) /* Bit 2: /TRxC O/I */
|
||||
#define WR11_TRXCO_SHIFT (0) /* Bits 0-1 : /TRxC Out */
|
||||
#define WR11_TRXO_MASK (3 << WR11_TRXCO_SHIFT)
|
||||
@ -839,6 +938,7 @@
|
||||
# define WR11_TRXO_DPLL (3 << WR11_TRXCO_SHIFT) /* /TRxC Out = DPLL Output */
|
||||
|
||||
/* WR12: Lower byte of baud rate generator -- 8-bit time constant value */
|
||||
|
||||
/* WR13: Upper byte of baud rate generator -- 8-bit time constant value */
|
||||
|
||||
/* WR14: Miscellaneous control bits */
|
||||
@ -853,6 +953,7 @@
|
||||
# define WR14_CMD_SRCRTXC (5 << WR14_CMD_SHIFT) /* Set Source = /RTxC */
|
||||
# define WR14_CMD_FM (6 << WR14_CMD_SHIFT) /* Set FM Mode */
|
||||
# define WR14_CMD_NRZI (7 << WR14_CMD_SHIFT) /* Set NRZI Mode */
|
||||
|
||||
#define WR14_LPBK (0x10) /* Bit 4: Local Loopback */
|
||||
#define WR14_AUTOECHO (0x08) /* Bit 3: Auto Echo */
|
||||
#define WR14_DTRREQ (0x04) /* Bit 2: /DTR/Request Function */
|
||||
|
||||
@ -46,9 +46,9 @@
|
||||
volatile chipreg_t *g_current_regs;
|
||||
|
||||
/* This holds the value of the MMU's CBR register. This value is set to the
|
||||
* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR if
|
||||
* an interrupt level context switch occurs, and restored on interrupt exit. In
|
||||
* this way, the CBR is always correct on interrupt exit.
|
||||
* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR
|
||||
* if an interrupt level context switch occurs, and restored on interrupt
|
||||
* exit. In this way, the CBR is always correct on interrupt exit.
|
||||
*/
|
||||
|
||||
uint8_t current_cbr;
|
||||
|
||||
@ -41,6 +41,7 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_ADDRENV
|
||||
@ -66,7 +67,8 @@ static struct z180_cbr_s g_cbrs[CONFIG_MAX_TASKS];
|
||||
* Name: z180_mmu_alloccbr
|
||||
*
|
||||
* Description:
|
||||
* Find an unused structure in g_cbrs (i.e., one with reference count == 0).
|
||||
* Find an unused structure in g_cbrs
|
||||
* (i.e., one with reference count == 0).
|
||||
* If a structure is found, its reference count is set to one and a pointer
|
||||
* to the structure is returned.
|
||||
*
|
||||
@ -150,9 +152,9 @@ int z80_mmu_initialize(void)
|
||||
* say that 1 page is 1 byte.
|
||||
*/
|
||||
|
||||
g_physhandle = gran_initialize((FAR void *)Z180_PHYSHEAP_STARTPAGE,
|
||||
g_physhandle = gran_initialize((FAR void *)Z180_PHYSHEAP_STARTPAGE,
|
||||
Z180_PHYSHEAP_NPAGES, 0, 0);
|
||||
return g_physhandle ? OK : -ENOMEM;
|
||||
return g_physhandle ? OK : -ENOMEM;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -187,6 +189,7 @@ return g_physhandle ? OK : -ENOMEM;
|
||||
* environment when a task/thread exits.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_addrenv_create
|
||||
*
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* Virtual addresses */
|
||||
@ -100,7 +101,7 @@
|
||||
#define Z180_BBR_VALUE ((CONFIG_Z180_BANKAREA_PHYSBASE >> 12) & 0xff)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -182,33 +182,33 @@ static const struct z180_dev_s g_escca_priv =
|
||||
|
||||
static uart_dev_t g_escca_port =
|
||||
{
|
||||
0, /* open_count */
|
||||
false, /* xmitwaiting */
|
||||
false, /* recvwaiting */
|
||||
0, /* open_count */
|
||||
false, /* xmitwaiting */
|
||||
false, /* recvwaiting */
|
||||
#ifdef CONFIG_Z180_ESCCA_SERIAL_CONSOLE
|
||||
true, /* isconsole */
|
||||
true, /* isconsole */
|
||||
#else
|
||||
false, /* isconsole */
|
||||
false, /* isconsole */
|
||||
#endif
|
||||
{ 0 }, /* closesem */
|
||||
{ 0 }, /* xmitsem */
|
||||
{ 0 }, /* recvsem */
|
||||
{ 0 }, /* closesem */
|
||||
{ 0 }, /* xmitsem */
|
||||
{ 0 }, /* recvsem */
|
||||
{
|
||||
{ 0 }, /* xmit.sem */
|
||||
0, /* xmit.head */
|
||||
0, /* xmit.tail */
|
||||
{ 0 }, /* xmit.sem */
|
||||
0, /* xmit.head */
|
||||
0, /* xmit.tail */
|
||||
CONFIG_Z180_ESCCA_TXBUFSIZE, /* xmit.size */
|
||||
g_escca_txbuffer, /* xmit.buffer */
|
||||
g_escca_txbuffer, /* xmit.buffer */
|
||||
},
|
||||
{
|
||||
{ 0 }, /* recv.sem */
|
||||
0, /* recv.head */
|
||||
0, /* recv.tail */
|
||||
{ 0 }, /* recv.sem */
|
||||
0, /* recv.head */
|
||||
0, /* recv.tail */
|
||||
CONFIG_Z180_ESCCA_RXBUFSIZE, /* recv.size */
|
||||
g_escca_rxbuffer, /* recv.buffer */
|
||||
g_escca_rxbuffer, /* recv.buffer */
|
||||
},
|
||||
&g_uart_ops, /* ops */
|
||||
&g_escca_priv, /* priv */
|
||||
&g_uart_ops, /* ops */
|
||||
&g_escca_priv, /* priv */
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -240,26 +240,26 @@ static uart_dev_t g_escca_port =
|
||||
{ 0 }, /* xmitsem */
|
||||
{ 0 }, /* recvsem */
|
||||
{
|
||||
{ 0 }, /* xmit.sem */
|
||||
0, /* xmit.head */
|
||||
0, /* xmit.tail */
|
||||
{ 0 }, /* xmit.sem */
|
||||
0, /* xmit.head */
|
||||
0, /* xmit.tail */
|
||||
CONFIG_Z180_ESCCA_TXBUFSIZE, /* xmit.size */
|
||||
g_escca_txbuffer, /* xmit.buffer */
|
||||
g_escca_txbuffer, /* xmit.buffer */
|
||||
},
|
||||
{
|
||||
{ 0 }, /* recv.sem */
|
||||
0, /* recv.head */
|
||||
0, /* recv.tail */
|
||||
{ 0 }, /* recv.sem */
|
||||
0, /* recv.head */
|
||||
0, /* recv.tail */
|
||||
CONFIG_Z180_ESCCA_RXBUFSIZE, /* recv.size */
|
||||
g_escca_rxbuffer, /* recv.buffer */
|
||||
g_escca_rxbuffer, /* recv.buffer */
|
||||
},
|
||||
&g_uart_ops, /* ops */
|
||||
&g_escca_priv, /* priv */
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Now, which one with be tty0/console and which tty1? NOTE: SCC and ESCCA/B and
|
||||
* mutually exclusive.
|
||||
/* Now, which one with be tty0/console and which tty1? NOTE: SCC and ESCCA/B
|
||||
* and mutually exclusive.
|
||||
*/
|
||||
|
||||
#undef CONSOLE_DEV
|
||||
@ -389,14 +389,15 @@ static void z180_shutdown(struct uart_dev_s *dev)
|
||||
* Name: z180_attach
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART to operation in interrupt driven mode. This method is
|
||||
* called when the serial port is opened. Normally, this is just after the
|
||||
* Configure the UART to operation in interrupt driven mode. This method
|
||||
* is called when the serial port is opened. Normally, this is just after
|
||||
* the setup() method is called, however, the serial console may operate in
|
||||
* a non-interrupt driven mode during the boot phase.
|
||||
*
|
||||
* RX and TX interrupts are not enabled when by the attach method (unless the
|
||||
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
||||
* interrupts are not enabled until the txint() and rxint() methods are called.
|
||||
* RX and TX interrupts are not enabled when by the attach method (unless
|
||||
* the hardware supports multiple levels of interrupt enabling). The RX
|
||||
* and TX interrupts are not enabled until the txint() and rxint() methods
|
||||
* are called.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -410,8 +411,8 @@ static int z180_attach(struct uart_dev_s *dev)
|
||||
*
|
||||
* Description:
|
||||
* Detach UART interrupts. This method is called when the serial port is
|
||||
* closed normally just before the shutdown method is called. The exception
|
||||
* is the serial console which is never shutdown.
|
||||
* closed normally just before the shutdown method is called. The
|
||||
* exception is the serial console which is never shutdown.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@ -34,8 +34,8 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -38,6 +38,7 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* "The Z180 contains a two channel 16-bit Programmable Reload Timer. Each
|
||||
* PRT channel contains a 16-bit down counter and a 16-bit reload register."
|
||||
* Channel 0 is dedicated as the system timer.
|
||||
@ -71,9 +72,9 @@
|
||||
|
||||
static int z180_timerisr(int irq, chipreg_t *regs, void *arg)
|
||||
{
|
||||
/* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt
|
||||
* request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and
|
||||
* the higher or lower byte of TMDR0 is read."
|
||||
/* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an
|
||||
* interrupt request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR
|
||||
* is read and the higher or lower byte of TMDR0 is read."
|
||||
*/
|
||||
|
||||
inp(Z180_PRT_TCR);
|
||||
@ -104,10 +105,11 @@ void up_timer_initialize(void)
|
||||
uint8_t regval;
|
||||
|
||||
/* Configure PRT0 to interrupt at the requested rate */
|
||||
|
||||
/* First stop PRT0 and disable interrupts */
|
||||
|
||||
regval = inp(Z180_PRT_TCR);
|
||||
regval &= (PRT_TCR_TIF0|PRT_TCR_TIE0|PRT_TCR_TDE0);
|
||||
regval &= (PRT_TCR_TIF0 | PRT_TCR_TIE0 | PRT_TCR_TDE0);
|
||||
outp(Z180_PRT_TCR, regval);
|
||||
|
||||
/* Set the timer reload value so that the timer will interrupt at the
|
||||
|
||||
@ -85,7 +85,7 @@
|
||||
#define Z8_TIMERCTL_GATED _HX(06)
|
||||
#define Z8_TIMERCTL_CAPCMP _HX(07)
|
||||
|
||||
/* UART Register Offsets *************************************************************/
|
||||
/* UART Register Offsets ************************************************************/
|
||||
|
||||
#define Z8_UART_TXD _HX(00) /* 8-bits: UART Transmit Data */
|
||||
#define Z8_UART_RXD _HX(00) /* 8-bits: UART Receive Data */
|
||||
|
||||
@ -39,7 +39,8 @@
|
||||
/* Z8_IRQSTATE_* definitions ********************************************************
|
||||
* These are used in the state field of 'struct z8_irqstate_s' structure to define
|
||||
* the current state of the interrupt handling. These definition support "lazy"
|
||||
* interrupt context saving. See comments below associated with s'truct z8_irqstate_s'.
|
||||
* interrupt context saving. See comments below associated with s'truct
|
||||
* z8_irqstate_s'.
|
||||
*/
|
||||
|
||||
#define Z8_IRQSTATE_NONE 0 /* Not handling an interrupt */
|
||||
@ -228,7 +229,8 @@ void z8_restorecontext(FAR chipreg_t *regs);
|
||||
|
||||
/* Defined in z8_sigsetup.c */
|
||||
|
||||
void z8_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
|
||||
void z8_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver,
|
||||
FAR chipreg_t *regs);
|
||||
|
||||
/* Defined in z8_registerdump.c */
|
||||
|
||||
|
||||
@ -282,7 +282,9 @@ static int z8_i2c_read_transfer(FAR struct z8_i2cdev_s *priv,
|
||||
I2CCTL |= I2C_CTL_NAK;
|
||||
}
|
||||
|
||||
/* If this was the last byte, then set STOP and return success */
|
||||
/* If this was the last byte, then set STOP and return
|
||||
* success
|
||||
*/
|
||||
|
||||
else if (count == 1)
|
||||
{
|
||||
|
||||
@ -36,7 +36,9 @@
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This structure holds information about the current interrupt processing state */
|
||||
/* This structure holds information about the current interrupt processing
|
||||
* state
|
||||
*/
|
||||
|
||||
struct z8_irqstate_s g_z8irqstate;
|
||||
|
||||
|
||||
@ -76,10 +76,11 @@ void z8_registerdump(void)
|
||||
switch (g_z8irqstate.state)
|
||||
{
|
||||
case Z8_IRQSTATE_ENTRY:
|
||||
|
||||
/* Calculate the source address based on the saved RP value */
|
||||
|
||||
rp = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS] >> 8;
|
||||
regs = (FAR uint16_t*)(rp & 0xf0);
|
||||
regs = (FAR uint16_t *)(rp & 0xf0);
|
||||
|
||||
/* Then dump the register values */
|
||||
|
||||
|
||||
@ -78,10 +78,12 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
|
||||
/* Calculate the source address based on the saved RP value */
|
||||
|
||||
uint16_t rp = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS] >> 8;
|
||||
FAR chipreg_t *src = (FAR uint16_t*)(rp & 0xf0);
|
||||
FAR chipreg_t *src = (FAR uint16_t *)(rp & 0xf0);
|
||||
FAR chipreg_t *dest = ®s[XCPT_RR0];
|
||||
|
||||
/* Copy the interrupted tasks register into the TCB register save area. */
|
||||
/* Copy the interrupted tasks register into the TCB register save
|
||||
* area.
|
||||
*/
|
||||
|
||||
int i;
|
||||
for (i = 0; i < XCPTCONTEXT_REGS; i++)
|
||||
@ -89,7 +91,9 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Since the task was interrupted, we know that interrupts were enabled */
|
||||
/* Since the task was interrupted, we know that interrupts were
|
||||
* enabled
|
||||
*/
|
||||
|
||||
regs[XCPT_IRQCTL] = 0x0080; /* IRQE bit will enable interrupts */
|
||||
|
||||
@ -107,8 +111,8 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
|
||||
regs[XCPT_RPFLAGS] = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS];
|
||||
regs[XCPT_PC] = g_z8irqstate.regs[Z8_IRQSAVE_PC];
|
||||
|
||||
/* Now update the IRQ save area so that we will know that we have already
|
||||
* done this.
|
||||
/* Now update the IRQ save area so that we will know that we have
|
||||
* already done this.
|
||||
*/
|
||||
|
||||
g_z8irqstate.state = Z8_IRQSTATE_SAVED;
|
||||
|
||||
@ -60,15 +60,15 @@ extern uint32_t get_freq(void);
|
||||
|
||||
struct z8_uart_s
|
||||
{
|
||||
uint8_t volatile far* uartbase; /* Base address of UART registers */
|
||||
uint32_t baud; /* Configured baud */
|
||||
bool rxenabled; /* RX interrupt enabled */
|
||||
bool txenabled; /* TX interrupt enabled */
|
||||
uint8_t rxirq; /* RX IRQ associated with this UART */
|
||||
uint8_t txirq; /* RX IRQ associated with this UART */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits
|
||||
* (instead of 1) */
|
||||
uint8_t volatile far * uartbase; /* Base address of UART registers */
|
||||
uint32_t baud; /* Configured baud */
|
||||
bool rxenabled; /* RX interrupt enabled */
|
||||
bool txenabled; /* TX interrupt enabled */
|
||||
uint8_t rxirq; /* RX IRQ associated with this UART */
|
||||
uint8_t txirq; /* RX IRQ associated with this UART */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits
|
||||
* (instead of 1) */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -255,10 +255,12 @@ static inline uint8_t z8_getuart(FAR struct z8_uart_s *priv, uint8_t offset)
|
||||
|
||||
static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
irqstate_t flags = enter_critical_section();
|
||||
uint8_t state = priv->rxenabled ? STATE_RXENABLED : STATE_DISABLED | \
|
||||
priv->txenabled ? STATE_TXENABLED : STATE_DISABLED;
|
||||
uint8_t state = priv->rxenabled ?
|
||||
STATE_RXENABLED : STATE_DISABLED | \
|
||||
priv->txenabled ?
|
||||
STATE_TXENABLED : STATE_DISABLED;
|
||||
|
||||
z8_txint(dev, false);
|
||||
z8_rxint(dev, false);
|
||||
@ -287,7 +289,7 @@ static void z8_restoreuartirq(FAR struct uart_dev_s *dev, uint8_t state)
|
||||
|
||||
static void z8_consoleput(uint8_t ch)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)CONSOLE_DEV.priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)CONSOLE_DEV.priv;
|
||||
int tmp;
|
||||
|
||||
for (tmp = 1000 ; tmp > 0 ; tmp--)
|
||||
@ -297,6 +299,7 @@ static void z8_consoleput(uint8_t ch)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
z8_putuart(priv, ch, Z8_UART_TXD);
|
||||
}
|
||||
|
||||
@ -353,7 +356,7 @@ void z8_uartconfigure(void)
|
||||
static int z8_setup(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
uint32_t freq = get_freq();
|
||||
uint16_t brg;
|
||||
uint8_t ctl0;
|
||||
@ -363,7 +366,7 @@ static int z8_setup(FAR struct uart_dev_s *dev)
|
||||
* BRG = (freq + baud * 8)/(baud * 16)
|
||||
*/
|
||||
|
||||
brg = (freq + (priv->baud << 3))/(priv->baud << 4);
|
||||
brg = (freq + (priv->baud << 3)) / (priv->baud << 4);
|
||||
z8_putuart(priv, brg >> 8, Z8_UART_BRH);
|
||||
z8_putuart(priv, brg & 0xff, Z8_UART_BRL);
|
||||
|
||||
@ -379,7 +382,7 @@ static int z8_setup(FAR struct uart_dev_s *dev)
|
||||
|
||||
if (priv->parity == 1)
|
||||
{
|
||||
ctl0 |= (Z8_UARTCTL0_PEN|Z8_UARTCTL0_PSEL);
|
||||
ctl0 |= (Z8_UARTCTL0_PEN | Z8_UARTCTL0_PSEL);
|
||||
}
|
||||
else if (priv->parity == 2)
|
||||
{
|
||||
@ -391,7 +394,7 @@ static int z8_setup(FAR struct uart_dev_s *dev)
|
||||
|
||||
/* Enable UART receive (REN) and transmit (TEN) */
|
||||
|
||||
ctl0 |= (Z8_UARTCTL0_TEN|Z8_UARTCTL0_REN);
|
||||
ctl0 |= (Z8_UARTCTL0_TEN | Z8_UARTCTL0_REN);
|
||||
z8_putuart(priv, ctl0, Z8_UART_CTL0);
|
||||
#endif
|
||||
return OK;
|
||||
@ -415,20 +418,21 @@ static void z8_shutdown(FAR struct uart_dev_s *dev)
|
||||
* Name: z8_attach
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART to operation in interrupt driven mode. This method is
|
||||
* called when the serial port is opened. Normally, this is just after the
|
||||
* the setup() method is called, however, the serial console may operate in
|
||||
* a non-interrupt driven mode during the boot phase.
|
||||
* Configure the UART to operation in interrupt driven mode. This method
|
||||
* is called when the serial port is opened. Normally, this is just after
|
||||
* the the setup() method is called, however, the serial console may
|
||||
* operate in a non-interrupt driven mode during the boot phase.
|
||||
*
|
||||
* RX and TX interrupts are not enabled when by the attach method (unless the
|
||||
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
||||
* interrupts are not enabled until the txint() and rxint() methods are called.
|
||||
* RX and TX interrupts are not enabled when by the attach method (unless
|
||||
* the hardware supports multiple levels of interrupt enabling). The RX
|
||||
* and TX interrupts are not enabled until the txint() and rxint() methods
|
||||
* are called.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int z8_attach(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
int ret;
|
||||
|
||||
/* Attach the RX IRQ */
|
||||
@ -444,6 +448,7 @@ static int z8_attach(FAR struct uart_dev_s *dev)
|
||||
irq_detach(priv->rxirq);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -452,14 +457,14 @@ static int z8_attach(FAR struct uart_dev_s *dev)
|
||||
*
|
||||
* Description:
|
||||
* Detach UART interrupts. This method is called when the serial port is
|
||||
* closed normally just before the shutdown method is called. The exception is
|
||||
* the serial console which is never shutdown.
|
||||
* closed normally just before the shutdown method is called. The
|
||||
* exception is the serial console which is never shutdown.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void z8_detach(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
up_disable_irq(priv->rxirq);
|
||||
up_disable_irq(priv->txirq);
|
||||
irq_detach(priv->rxirq);
|
||||
@ -482,7 +487,7 @@ static int z8_rxinterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
uint8_t status;
|
||||
|
||||
DEBUGASSERT(dev != NULL && dev->priv != NULL);
|
||||
priv = (struct z8_uart_s*)dev->priv;
|
||||
priv = (struct z8_uart_s *)dev->priv;
|
||||
|
||||
/* Check the LIN-UART status 0 register to determine whether the source of
|
||||
* the interrupt is error, break, or received data
|
||||
@ -500,6 +505,7 @@ static int z8_rxinterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
|
||||
uart_recvchars(dev);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -519,7 +525,7 @@ static int z8_txinterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
uint8_t status;
|
||||
|
||||
DEBUGASSERT(dev != NULL && dev->priv != NULL);
|
||||
priv = (struct z8_uart_s*)dev->priv;
|
||||
priv = (struct z8_uart_s *)dev->priv;
|
||||
|
||||
/* Verify that the transmit data register is empty */
|
||||
|
||||
@ -530,6 +536,7 @@ static int z8_txinterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
|
||||
uart_xmitchars(dev);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -558,7 +565,7 @@ static int z8_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
|
||||
|
||||
static int z8_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
uint8_t rxd;
|
||||
uint8_t stat0;
|
||||
|
||||
@ -578,7 +585,7 @@ static int z8_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status)
|
||||
|
||||
static void z8_rxint(FAR struct uart_dev_s *dev, bool enable)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
irqstate_t flags = enter_critical_section();
|
||||
|
||||
if (enable)
|
||||
@ -606,7 +613,7 @@ static void z8_rxint(FAR struct uart_dev_s *dev, bool enable)
|
||||
|
||||
static bool z8_rxavailable(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
return ((z8_getuart(priv, Z8_UART_STAT0) & Z8_UARTSTAT0_RDA) != 0);
|
||||
}
|
||||
|
||||
@ -620,7 +627,7 @@ static bool z8_rxavailable(FAR struct uart_dev_s *dev)
|
||||
|
||||
static void z8_send(FAR struct uart_dev_s *dev, int ch)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
z8_putuart(priv, ch, Z8_UART_TXD);
|
||||
}
|
||||
|
||||
@ -634,7 +641,7 @@ static void z8_send(FAR struct uart_dev_s *dev, int ch)
|
||||
|
||||
static void z8_txint(FAR struct uart_dev_s *dev, bool enable)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
irqstate_t flags = enter_critical_section();
|
||||
|
||||
if (enable)
|
||||
@ -662,7 +669,7 @@ static void z8_txint(FAR struct uart_dev_s *dev, bool enable)
|
||||
|
||||
static bool z8_txready(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
return ((z8_getuart(priv, Z8_UART_STAT0) & Z8_UARTSTAT0_TDRE) != 0);
|
||||
}
|
||||
|
||||
@ -676,7 +683,7 @@ static bool z8_txready(FAR struct uart_dev_s *dev)
|
||||
|
||||
static bool z8_txempty(FAR struct uart_dev_s *dev)
|
||||
{
|
||||
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
|
||||
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
|
||||
return ((z8_getuart(priv, Z8_UART_STAT0) & Z8_UARTSTAT0_TXE) != 0);
|
||||
}
|
||||
|
||||
@ -694,12 +701,13 @@ static bool z8_txempty(FAR struct uart_dev_s *dev)
|
||||
|
||||
void z80_serial_initialize(void)
|
||||
{
|
||||
/* Disable all UART interrupts */
|
||||
/* Disable all UART interrupts */
|
||||
|
||||
z8_disableuartirq(&TTYS0_DEV);
|
||||
z8_disableuartirq(&TTYS1_DEV);
|
||||
|
||||
/* Initialize the console for early use */
|
||||
|
||||
CONSOLE_DEV.isconsole = true;
|
||||
z8_setup(&CONSOLE_DEV);
|
||||
|
||||
|
||||
@ -87,7 +87,7 @@ void up_timer_initialize(void)
|
||||
* divide by 4.
|
||||
*/
|
||||
|
||||
putreg8((Z8_TIMERCTL_DIV4|Z8_TIMERCTL_CONT), T0CTL);
|
||||
putreg8((Z8_TIMERCTL_DIV4 | Z8_TIMERCTL_CONT), T0CTL);
|
||||
|
||||
/* Write to the timer high and low byte registers to set a starting
|
||||
* count value (this effects only the first pass in continuous mode)
|
||||
@ -109,14 +109,14 @@ void up_timer_initialize(void)
|
||||
* reload_value = system_clock_frequency / 400
|
||||
*/
|
||||
|
||||
reload = get_freq() / 400;
|
||||
putreg16((uint16_t)reload, T0R);
|
||||
reload = get_freq() / 400;
|
||||
putreg16((uint16_t)reload, T0R);
|
||||
|
||||
/* Write to the timer control register to enable the timer and to
|
||||
* initiate counting
|
||||
*/
|
||||
|
||||
putreg8((getreg8(T0CTL)|Z8_TIMERCTL_TEN), T0CTL);
|
||||
putreg8((getreg8(T0CTL) | Z8_TIMERCTL_TEN), T0CTL);
|
||||
|
||||
/* Set the timer priority */
|
||||
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
/* #include <nuttx/irq.h> */
|
||||
|
||||
#include "z80_internal.h"
|
||||
@ -61,7 +62,6 @@ void outp(char p, char c)
|
||||
__endasm;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Name: inpb
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user