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arch: z80: nxstyle fixes

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nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-29 21:21:50 +02:00 committed by David Sidrane
parent 4802b096c5
commit 106a471ef1
26 changed files with 346 additions and 202 deletions
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2
arch/z80/include/limits.h
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@ -22,7 +22,7 @@
#define __ARCH_Z80_INCLUDE_LIMITS_H #define __ARCH_Z80_INCLUDE_LIMITS_H
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Included Files
****************************************************************************/ ****************************************************************************/
#include <arch/chip/limits.h> #include <arch/chip/limits.h>

6
arch/z80/include/z180/arch.h
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@ -42,11 +42,13 @@
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
/* The z180 address environment is represented in hardware as the 8-bit /* The z180 address environment is represented in hardware as the 8-bit
* Common Base Register (CBR). CBR specifies the base address (on 4KB * Common Base Register (CBR). CBR specifies the base address (on 4KB
* boundaries) used to generate a 20-bit physical address for Common Area 1 * boundaries) used to generate a 20-bit physical address for Common Area 1
* accesses. CBR is the upper 8-bits of the 20-bit address; the lower 14-bits * accesses. CBR is the upper 8-bits of the 20-bit address; the lower
* of the base address are implicitly zero (hence the 4KB boundary alignment). * 14-bits of the base address are implicitly zero (hence the 4KB boundary
* alignment).
*/ */
#ifdef CONFIG_ARCH_ADDRENV #ifdef CONFIG_ARCH_ADDRENV

78
arch/z80/include/z180/chip.h
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@ -43,6 +43,7 @@
#define Z180_S_FLAG 0x80 /* Bit 7: Sign flag */ #define Z180_S_FLAG 0x80 /* Bit 7: Sign flag */
/* Z180 Chip Definitions ****************************************************/ /* Z180 Chip Definitions ****************************************************/
/* Z800180 /* Z800180
* *
* The 8-bit Z80180 MPU provides the benefits of reduced system costs and * The 8-bit Z80180 MPU provides the benefits of reduced system costs and
@ -121,10 +122,10 @@
# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ # define HAVE_NPAR8 0 /* No 8-bit parallel ports */
# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ # undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */
#elif defined(CONFIG_ARCH_CHIP_Z8018000XSO) #elif defined(CONFIG_ARCH_CHIP_Z8018000XSO)|| \
defined(CONFIG_ARCH_CHIP_Z8018010FEG) defined(CONFIG_ARCH_CHIP_Z8018010FEG)|| \
defined(CONFIG_ARCH_CHIP_Z8018000WSO) defined(CONFIG_ARCH_CHIP_Z8018000WSO)|| \
defined(CONFIG_ARCH_CHIP_Z8018008PEG) defined(CONFIG_ARCH_CHIP_Z8018008PEG)||
# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ # undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
# define HAVE_Z8X180 1 /* Z8x180 registers */ # define HAVE_Z8X180 1 /* Z8x180 registers */
@ -146,10 +147,11 @@
/* Z80181 /* Z80181
* *
* The Z80181 SAC Smart Access Controller is an 8-bit CMOS microprocessor that * The Z80181 SAC Smart Access Controller is an 8-bit CMOS microprocessor
* combines a Z180-compatible MPU, one channel of the Z85C30 Serial Communications * that combines a Z180-compatible MPU, one channel of the Z85C30 Serial
* Controller, a Z80 CTC, two 8-bit general-purpose parallel ports, and two Chip * Communications Controller, a Z80 CTC, two 8-bit general-purpose parallel
* Select signals, into a single 100-pin Quad Flat Pack package. * ports, and two Chip Select signals, into a single 100-pin Quad Flat Pack
* package.
* *
* Z80181 Features * Z80181 Features
* *
@ -187,11 +189,11 @@
/* Z80182 /* Z80182
* *
* The Z80182 and Z8L182 MPUs are smart peripheral controller ICs for modems, fax, * The Z80182 and Z8L182 MPUs are smart peripheral controller ICs for modems,
* voice messaging, and other communications applications. It uses the Z80180 * fax, voice messaging, and other communications applications. It uses the
* microprocessor linked with two channels of the industry-standard Z85230 ESCC, * Z80180 microprocessor linked with two channels of the industry-standard
* 24 bits of parallel I/O, and a 16550 MIMIC for direct connection to the IBM PC, * Z85230 ESCC, 24 bits of parallel I/O, and a 16550 MIMIC for direct
* XT, or AT bus * connection to the IBM PC, XT, or AT bus
* *
* Z80182 Features * Z80182 Features
* *
@ -203,7 +205,8 @@
* Clock Serial I/O * Clock Serial I/O
* Power-Down Mode * Power-Down Mode
* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options * Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options
* Enhanced Serial Communication Controller (ESCC) (2 Channels) with 32-Bit CRC * Enhanced Serial Communication Controller (ESCC)
* (2 Channels) with 32-Bit CRC
* 16550 MIMIC * 16550 MIMIC
* 24 Parallel I/O * 24 Parallel I/O
* 3.3 V and 5 V Version * 3.3 V and 5 V Version
@ -235,11 +238,12 @@
/* Z80195 /* Z80195
* *
* The Z80195 MPU is a smart peripheral controller device designed for general data * The Z80195 MPU is a smart peripheral controller device designed for
* communications applications, and architected specifically to accommodate all * general data communications applications, and architected specifically
* input and output (I/O) requirements for serial and parallel connectivity. * to accommodate all input and output (I/O) requirements for serial and
* Combining a high-performance CPU core with a variety of system and I/O * parallel connectivity. Combining a high-performance CPU core with a
* resources, the Z80195 is useful in a broad range of applications. * variety of system and I/O resources, the Z80195 is useful in a broad
* range of applications.
* *
* Z80195 Features * Z80195 Features
* *
@ -277,10 +281,10 @@
/* Z8L180 /* Z8L180
* *
* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models, * The enhanced Z8S180/Z8L180 significantly improves on previous Z80180
* while still providing full backward compatibility with existing ZiLOG Z80 * models, while still providing full backward compatibility with existing
* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving * ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds,
* modes, and EMI noise reduction. * power-saving modes, and EMI noise reduction.
* *
* Z8L180 Features * Z8L180 Features
* *
@ -322,12 +326,12 @@
/* Z8L182 /* Z8L182
* *
* The Z80182/Z8L182 is a smart peripheral controller IC for modem (in particular * The Z80182/Z8L182 is a smart peripheral controller IC for modem (in
* V. Fast applications), fax, voice messaging and other communications * particular V. Fast applications), fax, voice messaging and other
* applications. It uses the Z80180 microprocessor (Z8S180 MPU core) linked with * communications applications. It uses the Z80180 microprocessor (Z8S180
* two channels of the industry standard Z85230 ESCC (Enhanced Serial * MPU core) linked with two channels of the industry standard Z85230 ESCC
* Communications Controller), 24 bits of parallel I/O, and a 16550 MIMIC for * (Enhanced Serial Communications Controller), 24 bits of parallel I/O,
* direct connection to the IBM PC, XT, AT bus. * and a 16550 MIMIC for direct connection to the IBM PC, XT, AT bus.
* *
* Z8L182 Features * Z8L182 Features
* *
@ -369,14 +373,14 @@
/* Z8SL180 /* Z8SL180
* *
* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models, * The enhanced Z8S180/Z8L180 significantly improves on previous Z80180
* while still providing full backward compatibility with existing ZiLOG Z80 * models, while still providing full backward compatibility with existing
* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving * ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds,
* modes, and EMI noise reduction.This enhanced Z180 design also incorporates * power-saving modes, and EMI noise reduction.This enhanced Z180 design
* additional feature enhancements to the ASCIs, DMAs, and STANDBY mode power * also incorporates additional feature enhancements to the ASCIs, DMAs,
* consumption. With the addition of ESCC-like Baud Rate Generators (BRGs), the * and STANDBY mode power consumption. With the addition of ESCC-like
* two ASCIs offer the flexibility and capability to transfer data * Baud Rate Generators (BRGs), the two ASCIs offer the flexibility and
* asynchronously at rates of up to 512 Kbps. * capability to transfer data asynchronously at rates of up to 512 Kbps.
* *
* Z8S180 Features * Z8S180 Features
* *

2
arch/z80/include/z180/irq.h
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@ -38,7 +38,9 @@
****************************************************************************/ ****************************************************************************/
/* Z180 Interrupts */ /* Z180 Interrupts */
/* Resets */ /* Resets */
/* RST 0 is the power-up interrupt vector */ /* RST 0 is the power-up interrupt vector */
#define Z180_RST1 (0) /* RST 1 */ #define Z180_RST1 (0) /* RST 1 */
#define Z180_RST2 (1) /* RST 2 */ #define Z180_RST2 (1) /* RST 2 */

8
arch/z80/src/ez80/ez80_i2c.c
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@ -579,7 +579,9 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
else if (regval == I2C_SR_MDATARDNAK) else if (regval == I2C_SR_MDATARDNAK)
{ {
/* Since we just NACKed the incoming byte, it must be the last */ /* Since we just NACKed the incoming byte, it must be the
* last
*/
DEBUGASSERT(count <= 1); DEBUGASSERT(count <= 1);
@ -925,7 +927,9 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
ccr = ez80_i2c_getccr(100 * 1000); ccr = ez80_i2c_getccr(100 * 1000);
ez80_i2c_setccr(ccr); ez80_i2c_setccr(ccr);
/* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */ /* No GPIO setup is required -- I2C pints,
* SCL/SDA are not multiplexed
*/
/* This semaphore enforces serialized access for I2C transfers */ /* This semaphore enforces serialized access for I2C transfers */

8
arch/z80/src/ez80/ez80_serial.c
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@ -673,7 +673,9 @@ void z80_serial_initialize(void)
/* Configure pins for usage of UARTs */ /* Configure pins for usage of UARTs */
#ifdef CONFIG_EZ80_UART0 #ifdef CONFIG_EZ80_UART0
/* Set Port D, pins 0 and 1 for their alternate function (Mode 7) to enable UART0 */ /* Set Port D, pins 0 and 1 for their alternate function (Mode 7)
* to enable UART0
*/
regval = inp(EZ80_PD_DDR); regval = inp(EZ80_PD_DDR);
regval |= 3; regval |= 3;
@ -689,7 +691,9 @@ void z80_serial_initialize(void)
#endif #endif
#ifdef CONFIG_EZ80_UART1 #ifdef CONFIG_EZ80_UART1
/* Set Port C, pins 0 and 1 for their alternate function (Mode 7) to enable UART1 */ /* Set Port C, pins 0 and 1 for their alternate function (Mode 7)
* to enable UART1
*/
regval = inp(EZ80_PC_DDR); regval = inp(EZ80_PC_DDR);
regval |= 3; regval |= 3;

3
arch/z80/src/z180/switch.h
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@ -207,7 +207,8 @@ void z180_restoreusercontext(FAR chipreg_t *regs);
/* Defined in z180_sigsetup.c */ /* Defined in z180_sigsetup.c */
void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver,
FAR chipreg_t *regs);
/* Defined in z180_registerdump.c */ /* Defined in z180_registerdump.c */

3
arch/z80/src/z180/z180_config.h
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@ -34,6 +34,7 @@
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Verify that selected features match the capability of the selected CPU */ /* Verify that selected features match the capability of the selected CPU */
#ifndef HAVE_Z8X181 #ifndef HAVE_Z8X181
@ -212,7 +213,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_Z80_SRC_Z180_Z180_CONFIG_H */ #endif /* __ARCH_Z80_SRC_Z180_Z180_CONFIG_H */

1
arch/z80/src/z180/z180_io.c
View File

@ -61,7 +61,6 @@ void outp(char p, char c)
__endasm; __endasm;
} }
/**************************************************************************** /****************************************************************************
* Name: inpb * Name: inpb
* *

161
arch/z80/src/z180/z180_iomap.h
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@ -30,11 +30,13 @@
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Configuration ********************************************************************/ /* Configuration ********************************************************************/
/* These registers may be relocated to multiples of 0x40 by setting the IO Control /* These registers may be relocated to multiples of 0x40 by setting the IO
* Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The configuration setting, * Control Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The
* CONFIG_Z180_SFROFFSET, indicates that offset (but is not fully supported yet!) * configuration setting, CONFIG_Z180_SFROFFSET, indicates that offset
* (but is not fully supported yet!)
*/ */
#ifdef CONFIG_Z180_SFROFFSET #ifdef CONFIG_Z180_SFROFFSET
@ -44,6 +46,7 @@
#endif #endif
/* Z180 Register Bit addresses ******************************************************/ /* Z180 Register Bit addresses ******************************************************/
/* ASCI Registers */ /* ASCI Registers */
#define Z180_ASCI0_CNTLA (SFR_OFFSET+0x00) /* ASCI Control Register A Ch 0 */ #define Z180_ASCI0_CNTLA (SFR_OFFSET+0x00) /* ASCI Control Register A Ch 0 */
@ -105,6 +108,7 @@
#define Z180_DMA1_MARB (SFR_OFFSET+0x2a) /* DMA Memory Address Register Ch 1B */ #define Z180_DMA1_MARB (SFR_OFFSET+0x2a) /* DMA Memory Address Register Ch 1B */
#define Z180_DMA1_IARL (SFR_OFFSET+0x2b) /* DMA I/0 Address Register Ch 1L */ #define Z180_DMA1_IARL (SFR_OFFSET+0x2b) /* DMA I/0 Address Register Ch 1L */
#define Z180_DMA1_IARH (SFR_OFFSET+0x2c) /* DMA I/0 Address Register Ch 1H */ #define Z180_DMA1_IARH (SFR_OFFSET+0x2c) /* DMA I/0 Address Register Ch 1H */
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */ #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
# define Z180_DMA1_IARB (SFR_OFFSET+0x2d) /* DMA I/O Address Register Ch 1B */ # define Z180_DMA1_IARB (SFR_OFFSET+0x2d) /* DMA I/O Address Register Ch 1B */
#endif #endif
@ -138,6 +142,7 @@
#define Z180_ICR (SFR_OFFSET+0x3f) /* I/O Control Register */ #define Z180_ICR (SFR_OFFSET+0x3f) /* I/O Control Register */
/* The following registers are not relocatable */ /* The following registers are not relocatable */
/* Registers unique to Z8x181 class CPUs */ /* Registers unique to Z8x181 class CPUs */
#ifdef HAVE_Z8X181 #ifdef HAVE_Z8X181
@ -241,10 +246,12 @@
#endif #endif
/* [E]SCC Internal Register Definitions */ /* [E]SCC Internal Register Definitions */
/* Read Registers. The SCC contains eight read registers. To read the contents
* of a register (rather than RR0), the program must first initialize a pointer /* Read Registers. The SCC contains eight read registers. To read the
* to WR0 in exactly the same manner as a write operation. The next I/O read * contents of a register (rather than RR0), the program must first
* cycle will place the contents of the selected read registers onto the data bus * initialize a pointer to WR0 in exactly the same manner as a write
* operation. The next I/O read cycle will place the contents of the
* selected read registers onto the data bus
*/ */
#define Z18X_SCC_RR0 0x00 /* Transmit and Receive buffer status and external status */ #define Z18X_SCC_RR0 0x00 /* Transmit and Receive buffer status and external status */
@ -259,11 +266,12 @@
#define Z18X_SCC_RR13 0x0d /* Upper byte of baud rate generator time constant */ #define Z18X_SCC_RR13 0x0d /* Upper byte of baud rate generator time constant */
#define Z18X_SCC_RR15 0x0f /* External Status interrupt information */ #define Z18X_SCC_RR15 0x0f /* External Status interrupt information */
/* Write Registers. The SCC contains fifteen write registers that are programmed /* Write Registers. The SCC contains fifteen write registers that are
* to configure the operating modes of the channel. With the exception of WR0, programming * programmed to configure the operating modes of the channel. With the
* the write registers is a two step operation. The first operation is a pointer written to * exception of WR0, programming the write registers is a two step operation.
* WR0 that points to the selected register. The second operation is the actual control * The first operation is a pointer written to WR0 that points to the
* word that is written into the register to configure the SCC channel * selected register. The second operation is the actual control word that is
* written into the register to configure the SCC channel
*/ */
#define Z18X_SCC_WR0 0x00 /* Register Pointers, various initialization commands */ #define Z18X_SCC_WR0 0x00 /* Register Pointers, various initialization commands */
@ -284,8 +292,11 @@
#define Z18X_SCC_WR15 0x0f /* External status interrupt enable control */ #define Z18X_SCC_WR15 0x0f /* External status interrupt enable control */
/* Z180 Register Bit definitions ****************************************************/ /* Z180 Register Bit definitions ****************************************************/
/* ASCI Registers *******************************************************************/ /* ASCI Registers *******************************************************************/
/* ASCI Control Register A 0 (CNTLA0: 0x00) */ /* ASCI Control Register A 0 (CNTLA0: 0x00) */
/* ASCI Control Register A 1 (CNTLA1: 0x01) */ /* ASCI Control Register A 1 (CNTLA1: 0x01) */
#define ASCI_CNTRLA_MPE (0x80) /* Bit 7: Multi-Processor Mode Enable */ #define ASCI_CNTRLA_MPE (0x80) /* Bit 7: Multi-Processor Mode Enable */
@ -300,6 +311,7 @@
#define ASCI_CNTRLA_MOD0 (0x01) /* Bit 0: Parity enabled */ #define ASCI_CNTRLA_MOD0 (0x01) /* Bit 0: Parity enabled */
/* ASCI Control Register B 0 (CNTLB0: 0x02) */ /* ASCI Control Register B 0 (CNTLB0: 0x02) */
/* ASCI Control Register B 1 (CNTLB1: 0x03) */ /* ASCI Control Register B 1 (CNTLB1: 0x03) */
#define ASCI_CNTRLB_MPBT (0x80) /* Bit 7: Multiprocessor Bit Transmit */ #define ASCI_CNTRLB_MPBT (0x80) /* Bit 7: Multiprocessor Bit Transmit */
@ -321,6 +333,7 @@
# define ASCI_CNTRLB_SS_EXT (7 << ASCI_CNTRLB_SS_SHIFT) /* External clock */ # define ASCI_CNTRLB_SS_EXT (7 << ASCI_CNTRLB_SS_SHIFT) /* External clock */
/* ASCI Status Register 0 (STAT0: 0x04) */ /* ASCI Status Register 0 (STAT0: 0x04) */
/* ASCI Status Register 1 (STAT1: 0x05) */ /* ASCI Status Register 1 (STAT1: 0x05) */
#define ASCI_STAT_RFRF (0x80) /* Bit 7: Receive Data Register Full */ #define ASCI_STAT_RFRF (0x80) /* Bit 7: Receive Data Register Full */
@ -334,12 +347,20 @@
#define ASCI_STAT_TIE (0x01) /* Bit 0: Transmit Interrupt Enable */ #define ASCI_STAT_TIE (0x01) /* Bit 0: Transmit Interrupt Enable */
/* ASCI Transmit Data Register Ch. 0 (TDR0: 0x06) - 8-bit data */ /* ASCI Transmit Data Register Ch. 0 (TDR0: 0x06) - 8-bit data */
/* ASCI Transmit Data Register Ch. 1 (TDR1: 0x07) - 8-bit data */ /* ASCI Transmit Data Register Ch. 1 (TDR1: 0x07) - 8-bit data */
/* ASCI Receive Data Register Ch. 0 (RDR0: 0x08) - 8-bit data */ /* ASCI Receive Data Register Ch. 0 (RDR0: 0x08) - 8-bit data */
/* ASCI Receive Data Register Ch. 1 (RDR0: 0x09) - 8-bit data */ /* ASCI Receive Data Register Ch. 1 (RDR0: 0x09) - 8-bit data */
/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */ /* ASCI0 Extension Control Register (I/O Address: 0x12)
/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */ * (Z8S180/L180-Class Processors Only)
*/
/* ASCI1 Extension Control Register (I/O Address: 0x13)
* (Z8S180/L180-Class Processors Only)
*/
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */ #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
# define ASCI_ASEXT_RDRF (0x80) /* Bit 7: RDRF Interrupt Inhibit */ # define ASCI_ASEXT_RDRF (0x80) /* Bit 7: RDRF Interrupt Inhibit */
@ -352,12 +373,24 @@
# define ASCI_ASEXT_SNDBRK (0x80) /* Bit 0: Send Break */ # define ASCI_ASEXT_SNDBRK (0x80) /* Bit 0: Send Break */
#endif #endif
/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */ /* ASCI0 Time Constant Low Register (I/O Address: 0x1a)
/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */ * (Z8S180/L180-Class Processors Only) -- 8-bit data
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */ */
/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
/* ASCI0 Time Constant High Register (I/O Address: 0x1b)
* (Z8S180/L180-Class Processors Only) -- 8-bit data
*/
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c)
* (Z8S180/L180-Class Processors Only) -- 8-bit data
*/
/* ASCI1 Time Constant High Register (I/O Address: 0x1d)
* (Z8S180/L180-Class Processors Only) -- 8-bit data
*/
/* CSI/O Registers ******************************************************************/ /* CSI/O Registers ******************************************************************/
/* CSI/O Control/Status Register (CNTR: 0x0a) */ /* CSI/O Control/Status Register (CNTR: 0x0a) */
#define CSIO_CNTR_EF (0x80) /* Bit 7: End Flag */ #define CSIO_CNTR_EF (0x80) /* Bit 7: End Flag */
@ -375,12 +408,17 @@
# define CSIO_CNTR_DIV1280 (6 << CSIO_CNTR_SS_SHIFT) /* Divide Ratio: 1280 Baud: 3125 */ # define CSIO_CNTR_DIV1280 (6 << CSIO_CNTR_SS_SHIFT) /* Divide Ratio: 1280 Baud: 3125 */
# define CSIO_CNTR_EXT (7 << CSIO_CNTR_SS_SHIFT) /* External Clock input (less than 20) */ # define CSIO_CNTR_EXT (7 << CSIO_CNTR_SS_SHIFT) /* External Clock input (less than 20) */
/* Baud at Phi = 4 MHz */ /* Baud at Phi = 4 MHz */
/* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */ /* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */
/* Timer Registers ******************************************************************/ /* Timer Registers ******************************************************************/
/* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */ /* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */
/* Timer Data Register 0H (TMDR0H: 0x0d) -- 8-bit data */ /* Timer Data Register 0H (TMDR0H: 0x0d) -- 8-bit data */
/* Timer Reload Register Channel 0L (RLDR0L: 0x0e) -- 8-bit data */ /* Timer Reload Register Channel 0L (RLDR0L: 0x0e) -- 8-bit data */
/* Timer Reload Register Channel 0H (RLDR0H: 0x0f) -- 8-bit data */ /* Timer Reload Register Channel 0H (RLDR0H: 0x0f) -- 8-bit data */
/* Programmable Reload Timer (PTR) Control Register (TCR: 0x10) */ /* Programmable Reload Timer (PTR) Control Register (TCR: 0x10) */
@ -395,18 +433,36 @@
#define PRT_TCR_TDE0 (0x01) /* Bit 0: Timer 0 Down Count Enable */ #define PRT_TCR_TDE0 (0x01) /* Bit 0: Timer 0 Down Count Enable */
/* Timer Data Register 1L (TMDR1L: 0x14) -- 8-bit data */ /* Timer Data Register 1L (TMDR1L: 0x14) -- 8-bit data */
/* Timer Data Register 1H (TMDR1H: 0x15) -- 8-bit data */ /* Timer Data Register 1H (TMDR1H: 0x15) -- 8-bit data */
/* Timer Reload Register Channel 1L (RLDR1L: 0x16) -- 8-bit data */ /* Timer Reload Register Channel 1L (RLDR1L: 0x16) -- 8-bit data */
/* Timer Reload Register Channel 1H (RLDR1H: 0x17) -- 8-bit data */ /* Timer Reload Register Channel 1H (RLDR1H: 0x17) -- 8-bit data */
/* Free Running counter (FRC: 0x18) -- 8-bit data */ /* Free Running counter (FRC: 0x18) -- 8-bit data */
/* DMA Registers ********************************************************************/ /* DMA Registers ********************************************************************/
/* DMA Destination Address Register Channel 0 (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data */
/* DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
/* DMA Memory Address Register Channel 1 (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data */
/* DMA I/O Address Register Channel 1 (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data */
/* DMA I/O Address Register Ch. 1 (IAR1B: 0x2d) (Z8S180/L180-Class Processor Only) */ /* DMA Destination Address Register Channel 0
* (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data
*/
/* DMA Byte Count Register Channel 0
* (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data
*/
/* DMA Memory Address Register Channel 1
* (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data
*/
/* DMA I/O Address Register Channel 1
* (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data
*/
/* DMA I/O Address Register Ch. 1
* (IAR1B: 0x2d) (Z8S180/L180-Class Processor Only)
*/
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */ #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
# define IAR1B_ALTCH (0x80) /* Bit 7: Alternating Channels */ # define IAR1B_ALTCH (0x80) /* Bit 7: Alternating Channels */
@ -422,7 +478,9 @@
# define IAR1B_IO_PIA (7 << IAR1B_IO_SHIFT) /* DMA1 PIA27-20 (P1284) */ # define IAR1B_IO_PIA (7 << IAR1B_IO_SHIFT) /* DMA1 PIA27-20 (P1284) */
#endif #endif
/* DMA Byte Count Register Channel 1 (BCR1: I/O Address = 0x2e to 0x2f) -- 8-bit data */ /* DMA Byte Count Register Channel 1
* (BCR1: I/O Address = 0x2e to 0x2f) -- 8-bit data
*/
/* DMA Status Register (DSTAT: 0x30) */ /* DMA Status Register (DSTAT: 0x30) */
@ -442,12 +500,14 @@
# define DMODE_DM_MEMDECR (1 << DMODE_DM_SHIFT) /* Memory with address decrement */ # define DMODE_DM_MEMDECR (1 << DMODE_DM_SHIFT) /* Memory with address decrement */
# define DMODE_DM_MEM (2 << DMODE_DM_SHIFT) /* Memory with fixed address */ # define DMODE_DM_MEM (2 << DMODE_DM_SHIFT) /* Memory with fixed address */
# define DMODE_DM_IO (3 << DMODE_DM_SHIFT) /* I/O */ # define DMODE_DM_IO (3 << DMODE_DM_SHIFT) /* I/O */
#define DMODE_SM_SHIFT (2) /* Bits 2-3: Source Mode Channel */ #define DMODE_SM_SHIFT (2) /* Bits 2-3: Source Mode Channel */
#define DMODE_SM_MASK (3 << DMODE_SM_SHIFT) #define DMODE_SM_MASK (3 << DMODE_SM_SHIFT)
# define DMODE_SM_MEMINCR (0 << DMODE_SM_SHIFT) /* Memory with address increment */ # define DMODE_SM_MEMINCR (0 << DMODE_SM_SHIFT) /* Memory with address increment */
# define DMODE_SM_MEMDECR (1 << DMODE_SM_SHIFT) /* Memory with address decrement */ # define DMODE_SM_MEMDECR (1 << DMODE_SM_SHIFT) /* Memory with address decrement */
# define DMODE_SM_MEM (2 << DMODE_SM_SHIFT) /* Memory with fixed address */ # define DMODE_SM_MEM (2 << DMODE_SM_SHIFT) /* Memory with fixed address */
# define DMODE_SM_IO (3 << DMODE_SM_SHIFT) /* I/O */ # define DMODE_SM_IO (3 << DMODE_SM_SHIFT) /* I/O */
#define DMODE_MMODE (0x01) /* Bit 0: DMA Memory Mode Channel 0 */ #define DMODE_MMODE (0x01) /* Bit 0: DMA Memory Mode Channel 0 */
/* DMA/WAIT Control Register (DCNTL: 0x32) */ /* DMA/WAIT Control Register (DCNTL: 0x32) */
@ -468,7 +528,10 @@
# define DCNTL_DIM_IO2MD (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */ # define DCNTL_DIM_IO2MD (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */
/* System Control Registers *********************************************************/ /* System Control Registers *********************************************************/
/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
/* Clock Multiplier Register (CMR: 0x1e)
* (Z8S180/L180-Class Processors Only)
*/
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */ #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
# define CMR_CMM (0x80) /* Bit 7: X2 Clock Multiplier Mode */ # define CMR_CMM (0x80) /* Bit 7: X2 Clock Multiplier Mode */
@ -515,6 +578,7 @@
# define RCR_CYC1 (2 << RCR_CYC_SHIFT) # define RCR_CYC1 (2 << RCR_CYC_SHIFT)
/* MMU Common Base Register (CBR: 0x38) - 8-bit base address of Common Area 1 */ /* MMU Common Base Register (CBR: 0x38) - 8-bit base address of Common Area 1 */
/* MMU Bank Base Register (BBR: 0x39) - 8-bit address of Bank area */ /* MMU Bank Base Register (BBR: 0x39) - 8-bit address of Bank area */
/* MMU Common/Bank Area Register (CBAR: 0x3a) */ /* MMU Common/Bank Area Register (CBAR: 0x3a) */
@ -542,12 +606,15 @@
#ifdef HAVE_Z8X181 #ifdef HAVE_Z8X181
/* PIA Registers */ /* PIA Registers */
/* PIAn Data Direction and Data Registers */ /* PIAn Data Direction and Data Registers */
# define PIA(n) (1 << (n)) # define PIA(n) (1 << (n))
/* CTC Registers */ /* CTC Registers */
/* CTC Channel Control/Vector Registers */ /* CTC Channel Control/Vector Registers */
/* Control Bit Definitions */ /* Control Bit Definitions */
# define CTC_IE (0x80) /* Bit 7: Interrupt Enable */ # define CTC_IE (0x80) /* Bit 7: Interrupt Enable */
@ -570,8 +637,11 @@
/* SCC Registers -- See interface description below */ /* SCC Registers -- See interface description below */
/* System Control Registers */ /* System Control Registers */
/* RAM Upper Boundary Address Register -- 8-bit address (A12-A19) */ /* RAM Upper Boundary Address Register -- 8-bit address (A12-A19) */
/* RAM Lower Boundary Address Register -- 8-bit address (A12-A19) */ /* RAM Lower Boundary Address Register -- 8-bit address (A12-A19) */
/* ROM Address Boundary Register -- 8-bit address (A12-A19) */ /* ROM Address Boundary Register -- 8-bit address (A12-A19) */
/* System Configuration Register */ /* System Configuration Register */
@ -587,6 +657,7 @@
#ifdef HAVE_Z8X182 #ifdef HAVE_Z8X182
/* PIA Registers */ /* PIA Registers */
/* Pn Data Direction and Data Register */ /* Pn Data Direction and Data Register */
# define PIA(n) (1 << (n)) # define PIA(n) (1 << (n))
@ -605,11 +676,13 @@
# define SCR_DC (0x01) /* Bit 0: Daisy Chain */ # define SCR_DC (0x01) /* Bit 0: Daisy Chain */
/* 16550 MIMIC Registers */ /* 16550 MIMIC Registers */
/* To be provided */ /* To be provided */
#endif #endif
/* [E]SCC Internal Register Definitions *********************************************/ /* [E]SCC Internal Register Definitions *********************************************/
/* Read Registers */ /* Read Registers */
/* RR0: Transmit and Receive buffer status and external status */ /* RR0: Transmit and Receive buffer status and external status */
@ -642,7 +715,10 @@
#define RR3_TX (0x10) /* Bit 4: Tx IP */ #define RR3_TX (0x10) /* Bit 4: Tx IP */
#define RR3_EXT (0x08) /* Bit 3: Ext/Status IP */ #define RR3_EXT (0x08) /* Bit 3: Ext/Status IP */
/* RR6: SDLC FIFO byte counter lower byte (only when enabled) -- 8-bit counter value */ /* RR6: SDLC FIFO byte counter lower byte (only when enabled) --
* 8-bit counter value
*/
/* RR7: SDLC FIFO byte count and status (only when enabled) */ /* RR7: SDLC FIFO byte count and status (only when enabled) */
#define RR7_BC_SHIFT (0) /* Bits 0-5 : Upper 6-bits of counter */ #define RR7_BC_SHIFT (0) /* Bits 0-5 : Upper 6-bits of counter */
@ -651,6 +727,7 @@
#define RR7_FOS (0x80) /* Bit 7: FIFO Overflow Status */ #define RR7_FOS (0x80) /* Bit 7: FIFO Overflow Status */
/* RR8: Receive buffer */ /* RR8: Receive buffer */
/* RR10: Miscellaneous status bits */ /* RR10: Miscellaneous status bits */
#define RR10_1MISS (0x80) /* Bit 7: One Clock Missing */ #define RR10_1MISS (0x80) /* Bit 7: One Clock Missing */
@ -658,8 +735,13 @@
#define RR10_SEND (0x10) /* Bit 4: Loop Sending */ #define RR10_SEND (0x10) /* Bit 4: Loop Sending */
#define RR10_ON (0x02) /* Bit 1: On Loop */ #define RR10_ON (0x02) /* Bit 1: On Loop */
/* RR12: Lower byte of baud rate generator time constant -- 8-bit time constant value */ /* RR12: Lower byte of baud rate generator time constant --
/* RR13: Upper byte of baud rate generator time constant -- 8-bit time constant value */ * 8-bit time constant value
*/
/* RR13: Upper byte of baud rate generator time constant --
* 8-bit time constant value
*/
/* RR15: External Status interrupt information */ /* RR15: External Status interrupt information */
@ -683,6 +765,7 @@
# define WR0_CMD1_RXCRCRST (1 << WR0_CMD1_SHIFT); /* Reset Rx CRC Checker */ # define WR0_CMD1_RXCRCRST (1 << WR0_CMD1_SHIFT); /* Reset Rx CRC Checker */
# define WR0_CMD1_TXCRCRST (2 << WR0_CMD1_SHIFT); /* Reset Tx CRC Generator */ # define WR0_CMD1_TXCRCRST (2 << WR0_CMD1_SHIFT); /* Reset Tx CRC Generator */
# define WR0_CMD1_TXURRST (3 << WR0_CMD1_SHIFT); /* Reset Tx Underrun/EOM Latch */ # define WR0_CMD1_TXURRST (3 << WR0_CMD1_SHIFT); /* Reset Tx Underrun/EOM Latch */
#define WR0_CMD2_SHIFT (3) /* Bits 3-5: Command */ #define WR0_CMD2_SHIFT (3) /* Bits 3-5: Command */
#define WR0_CMD2_MASK (3 << WR0_CMD2_SHIFT); #define WR0_CMD2_MASK (3 << WR0_CMD2_SHIFT);
# define WR0_CMD2_NULL (0 << WR0_CMD2_SHIFT); /* Null Code */ # define WR0_CMD2_NULL (0 << WR0_CMD2_SHIFT); /* Null Code */
@ -693,6 +776,7 @@
# define WR0_CMD2_TXPRST (5 << WR0_CMD2_SHIFT); /* Reset Tx Int Pending */ # define WR0_CMD2_TXPRST (5 << WR0_CMD2_SHIFT); /* Reset Tx Int Pending */
# define WR0_CMD2_ERRRST (6 << WR0_CMD2_SHIFT); /* Error Reset */ # define WR0_CMD2_ERRRST (6 << WR0_CMD2_SHIFT); /* Error Reset */
# define WR0_CMD2_IUSRST (7 << WR0_CMD2_SHIFT); /* Reset Highest IUS */ # define WR0_CMD2_IUSRST (7 << WR0_CMD2_SHIFT); /* Reset Highest IUS */
#define WR0_REG_SHIFT (0) /* Bits 0-2 : Register address */ #define WR0_REG_SHIFT (0) /* Bits 0-2 : Register address */
#define WR0_REG_MASK (7 << WR0_REG_SHIFT); #define WR0_REG_MASK (7 << WR0_REG_SHIFT);
@ -707,6 +791,7 @@
# define WR1_CMD_RXINT1ST (1 << WR1_CMD_SHIFT) /* Rx Int On First Character or Special Condition */ # define WR1_CMD_RXINT1ST (1 << WR1_CMD_SHIFT) /* Rx Int On First Character or Special Condition */
# define WR1_CMD_RXINTALL (2 << WR1_CMD_SHIFT) /* Int On All Rx Characters or Special Condition */ # define WR1_CMD_RXINTALL (2 << WR1_CMD_SHIFT) /* Int On All Rx Characters or Special Condition */
# define WR1_CMD_RXINTSPEC (3 << WR1_CMD_SHIFT) /* Rx Int On Special Condition Only */ # define WR1_CMD_RXINTSPEC (3 << WR1_CMD_SHIFT) /* Rx Int On Special Condition Only */
#define WR1_PSPEC (0x04) /* Bit 2: Parity is Special Condition */ #define WR1_PSPEC (0x04) /* Bit 2: Parity is Special Condition */
#define WR1_TXIE (0x02) /* Bit 1: Tx Int Enable */ #define WR1_TXIE (0x02) /* Bit 1: Tx Int Enable */
#define WR1_EXTIE (0x01) /* Bit 0: Ext Int Enable */ #define WR1_EXTIE (0x01) /* Bit 0: Ext Int Enable */
@ -721,6 +806,7 @@
# define WR3_BPC_7 (1 << WR3_BPC_SHIFT) /* Rx 7 Bits/Character */ # define WR3_BPC_7 (1 << WR3_BPC_SHIFT) /* Rx 7 Bits/Character */
# define WR3_BPC_6 (2 << WR3_BPC_SHIFT) /* Rx 6 Bits/Character */ # define WR3_BPC_6 (2 << WR3_BPC_SHIFT) /* Rx 6 Bits/Character */
# define WR3_BPC_8 (3 << WR3_BPC_SHIFT) /* Rx 8 Bits/Character */ # define WR3_BPC_8 (3 << WR3_BPC_SHIFT) /* Rx 8 Bits/Character */
#define WR3_AE (0x20) /* Bit 5: Auto Enables */ #define WR3_AE (0x20) /* Bit 5: Auto Enables */
#define WR3_EHM (0x10) /* Bit 4: Enter Hunt Mode */ #define WR3_EHM (0x10) /* Bit 4: Enter Hunt Mode */
#define WR3_RXCRCEN (0x08) /* Bit 3: Rx CRC Enable */ #define WR3_RXCRCEN (0x08) /* Bit 3: Rx CRC Enable */
@ -736,18 +822,21 @@
# define WR4_CM_X16 (1 << WR4_CM_SHIFT) /* X16 Clock Mode */ # define WR4_CM_X16 (1 << WR4_CM_SHIFT) /* X16 Clock Mode */
# define WR4_CM_X32 (2 << WR4_CM_SHIFT) /* X32 Clock Mode */ # define WR4_CM_X32 (2 << WR4_CM_SHIFT) /* X32 Clock Mode */
# define WR4_CM_X64 (3 << WR4_CM_SHIFT) /* X64 Clock Mode */ # define WR4_CM_X64 (3 << WR4_CM_SHIFT) /* X64 Clock Mode */
#define WR4_SM_SHIFT (4) /* Bits 4-5: Sync mode */ #define WR4_SM_SHIFT (4) /* Bits 4-5: Sync mode */
#define WR4_SM_MASK (3 << WR4_SM_SHIFT) #define WR4_SM_MASK (3 << WR4_SM_SHIFT)
# define WR4_SM_8BIT (0 << WR4_SM_SHIFT) /* 8-Bit Sync Character */ # define WR4_SM_8BIT (0 << WR4_SM_SHIFT) /* 8-Bit Sync Character */
# define WR4_SM_16BIT (1 << WR4_SM_SHIFT) /* 16-Bit Sync Character */ # define WR4_SM_16BIT (1 << WR4_SM_SHIFT) /* 16-Bit Sync Character */
# define WR4_SM_SDLC (2 << WR4_SM_SHIFT) /* SDLC Mode (01111110 Flag) */ # define WR4_SM_SDLC (2 << WR4_SM_SHIFT) /* SDLC Mode (01111110 Flag) */
# define WR4_SM_EXT (3 << WR4_SM_SHIFT) /* External Sync Mode */ # define WR4_SM_EXT (3 << WR4_SM_SHIFT) /* External Sync Mode */
#define WR4_SB_SHIFT (2) /* Bits 2-3: Sync mode enables */ #define WR4_SB_SHIFT (2) /* Bits 2-3: Sync mode enables */
#define WR4_SB_MASK (3 << WR4_SB_SHIFT) #define WR4_SB_MASK (3 << WR4_SB_SHIFT)
# define WR4_SB_SME (0 << WR4_SB_SHIFT) /* Sync Modes Enable */ # define WR4_SB_SME (0 << WR4_SB_SHIFT) /* Sync Modes Enable */
# define WR4_SB_STOP1 (1 << WR4_SB_SHIFT) /* 1 Stop Bit/Character */ # define WR4_SB_STOP1 (1 << WR4_SB_SHIFT) /* 1 Stop Bit/Character */
# define WR4_SB_STOP1p5 (2 << WR4_SB_SHIFT) /* 1 1/2 Stop Bits/Character */ # define WR4_SB_STOP1p5 (2 << WR4_SB_SHIFT) /* 1 1/2 Stop Bits/Character */
# define WR4_SB_STOP2 (3 << WR4_SB_SHIFT) /* 2 Stop Bits/Character */ # define WR4_SB_STOP2 (3 << WR4_SB_SHIFT) /* 2 Stop Bits/Character */
#define WR4_PEO (0x02) /* Bit 1: Parity EVEN//ODD */ #define WR4_PEO (0x02) /* Bit 1: Parity EVEN//ODD */
#define WR4_PEN (0x01) /* Bit : Parity Enable */ #define WR4_PEN (0x01) /* Bit : Parity Enable */
@ -760,14 +849,20 @@
# define WR5_TXBITS_7 (1 << WR5_TXBITS_SHIFT) /* Tx 7 Bits/Character */ # define WR5_TXBITS_7 (1 << WR5_TXBITS_SHIFT) /* Tx 7 Bits/Character */
# define WR5_TXBITS_6 (2 << WR5_TXBITS_SHIFT) /* Tx 6 Bits/Character */ # define WR5_TXBITS_6 (2 << WR5_TXBITS_SHIFT) /* Tx 6 Bits/Character */
# define WR5_TXBITS_8 (3 << WR5_TXBITS_SHIFT) /* Tx 8 Bits/Character */ # define WR5_TXBITS_8 (3 << WR5_TXBITS_SHIFT) /* Tx 8 Bits/Character */
#define WR5_SENDBRK (0x10) /* Bit 4: Send Break */ #define WR5_SENDBRK (0x10) /* Bit 4: Send Break */
#define WR5_TXEN (0x08) /* Bit 3: Tx Enable */ #define WR5_TXEN (0x08) /* Bit 3: Tx Enable */
#define WR5_CRC16 (0x04) /* Bit 2: /SDLC/CRC-16 */ #define WR5_CRC16 (0x04) /* Bit 2: /SDLC/CRC-16 */
#define WR5_RTS (0x02) /* Bit 1: RTS */ #define WR5_RTS (0x02) /* Bit 1: RTS */
#define WR5_TXCRCEN (0x01) /* Bit 0: Tx CRC Enable */ #define WR5_TXCRCEN (0x01) /* Bit 0: Tx CRC Enable */
/* WR6: Sync Character or SDLC address -- 8-bit Monosync, Bisync, or SDLC value */ /* WR6: Sync Character or SDLC address --
/* WR7: Sync Character or SDLC flag -- 8-bit Monosync, Bisync, or SDLC value */ * 8-bit Monosync, Bisync, or SDLC value
*/
/* WR7: Sync Character or SDLC flag --
* 8-bit Monosync, Bisync, or SDLC value
*/
#define WR7_SDLC_SYNC (0x7e) #define WR7_SDLC_SYNC (0x7e)
@ -791,6 +886,7 @@
# define WR9_RST_NONE (0 << WR9_RST_SHIFT) /* No Reset */ # define WR9_RST_NONE (0 << WR9_RST_SHIFT) /* No Reset */
# define WR9_RST_CHAN (2 << WR9_RST_SHIFT) /* Channel Reset */ # define WR9_RST_CHAN (2 << WR9_RST_SHIFT) /* Channel Reset */
# define WR9_RST_HWRST (3 << WR9_RST_SHIFT) /* Force Hardware Reset */ # define WR9_RST_HWRST (3 << WR9_RST_SHIFT) /* Force Hardware Reset */
#ifdef HAVE_Z8X182 /* ESCC only */ #ifdef HAVE_Z8X182 /* ESCC only */
# define WR9_INTACKEN (0x20) /* Bit 5: Software INTACK Enable */ # define WR9_INTACKEN (0x20) /* Bit 5: Software INTACK Enable */
#endif #endif
@ -809,6 +905,7 @@
# define WR10_NRZI (1 << WR10_NRZFM_SHIFT) /* NRZI */ # define WR10_NRZI (1 << WR10_NRZFM_SHIFT) /* NRZI */
# define WR10_FM1 (2 << WR10_NRZFM_SHIFT) /* FM1 (Transition = 1) */ # define WR10_FM1 (2 << WR10_NRZFM_SHIFT) /* FM1 (Transition = 1) */
# define WR10_FM0 (3 << WR10_NRZFM_SHIFT) /* FM0 (Transition = 0) */ # define WR10_FM0 (3 << WR10_NRZFM_SHIFT) /* FM0 (Transition = 0) */
#define WR10_ACTPOLL (0x10) /* Bit 4: Go Active On Poll */ #define WR10_ACTPOLL (0x10) /* Bit 4: Go Active On Poll */
#define WR10_IDLE (0x08) /* Bit 3: Mark/Flag Idle */ #define WR10_IDLE (0x08) /* Bit 3: Mark/Flag Idle */
#define WR10_URABORT (0x04) /* Bit 2: Abort/Flag On Underrun */ #define WR10_URABORT (0x04) /* Bit 2: Abort/Flag On Underrun */
@ -824,12 +921,14 @@
# define WR11_RCLK_TRXC (1 << WR11_RCLK_SHIFT) /* Receive Clock = /TRxC Pin */ # define WR11_RCLK_TRXC (1 << WR11_RCLK_SHIFT) /* Receive Clock = /TRxC Pin */
# define WR11_RCLK_BRG (2 << WR11_RCLK_SHIFT) /* Receive Clock = BR Generator Output */ # define WR11_RCLK_BRG (2 << WR11_RCLK_SHIFT) /* Receive Clock = BR Generator Output */
# define WR11_RCLK_DPLL (3 << WR11_RCLK_SHIFT) /* Receive Clock = DPLL Output */ # define WR11_RCLK_DPLL (3 << WR11_RCLK_SHIFT) /* Receive Clock = DPLL Output */
#define WR11_TCLK_SHIFT (3) /* Bits 3-4: Transmit Clock */ #define WR11_TCLK_SHIFT (3) /* Bits 3-4: Transmit Clock */
#define WR11_TCLK_MASK (3 << WR11_TCLK_SHIFT) #define WR11_TCLK_MASK (3 << WR11_TCLK_SHIFT)
# define WR11_TCLK_RTXC (0 << WR11_TCLK_SHIFT) /* Transmit Clock = /RTxC Pin */ # define WR11_TCLK_RTXC (0 << WR11_TCLK_SHIFT) /* Transmit Clock = /RTxC Pin */
# define WR11_TCLK_TRXC (1 << WR11_TCLK_SHIFT) /* Transmit Clock = /TRxC Pin */ # define WR11_TCLK_TRXC (1 << WR11_TCLK_SHIFT) /* Transmit Clock = /TRxC Pin */
# define WR11_TCLK_BRG (2 << WR11_TCLK_SHIFT) /* Transmit Clock = BR Generator Output */ # define WR11_TCLK_BRG (2 << WR11_TCLK_SHIFT) /* Transmit Clock = BR Generator Output */
# define WR11_TCLK_DPLL (3 << WR11_TCLK_SHIFT) /* Transmit Clock = DPLL Output */ # define WR11_TCLK_DPLL (3 << WR11_TCLK_SHIFT) /* Transmit Clock = DPLL Output */
#define WR11_TRXCIO (0x04) /* Bit 2: /TRxC O/I */ #define WR11_TRXCIO (0x04) /* Bit 2: /TRxC O/I */
#define WR11_TRXCO_SHIFT (0) /* Bits 0-1 : /TRxC Out */ #define WR11_TRXCO_SHIFT (0) /* Bits 0-1 : /TRxC Out */
#define WR11_TRXO_MASK (3 << WR11_TRXCO_SHIFT) #define WR11_TRXO_MASK (3 << WR11_TRXCO_SHIFT)
@ -839,6 +938,7 @@
# define WR11_TRXO_DPLL (3 << WR11_TRXCO_SHIFT) /* /TRxC Out = DPLL Output */ # define WR11_TRXO_DPLL (3 << WR11_TRXCO_SHIFT) /* /TRxC Out = DPLL Output */
/* WR12: Lower byte of baud rate generator -- 8-bit time constant value */ /* WR12: Lower byte of baud rate generator -- 8-bit time constant value */
/* WR13: Upper byte of baud rate generator -- 8-bit time constant value */ /* WR13: Upper byte of baud rate generator -- 8-bit time constant value */
/* WR14: Miscellaneous control bits */ /* WR14: Miscellaneous control bits */
@ -853,6 +953,7 @@
# define WR14_CMD_SRCRTXC (5 << WR14_CMD_SHIFT) /* Set Source = /RTxC */ # define WR14_CMD_SRCRTXC (5 << WR14_CMD_SHIFT) /* Set Source = /RTxC */
# define WR14_CMD_FM (6 << WR14_CMD_SHIFT) /* Set FM Mode */ # define WR14_CMD_FM (6 << WR14_CMD_SHIFT) /* Set FM Mode */
# define WR14_CMD_NRZI (7 << WR14_CMD_SHIFT) /* Set NRZI Mode */ # define WR14_CMD_NRZI (7 << WR14_CMD_SHIFT) /* Set NRZI Mode */
#define WR14_LPBK (0x10) /* Bit 4: Local Loopback */ #define WR14_LPBK (0x10) /* Bit 4: Local Loopback */
#define WR14_AUTOECHO (0x08) /* Bit 3: Auto Echo */ #define WR14_AUTOECHO (0x08) /* Bit 3: Auto Echo */
#define WR14_DTRREQ (0x04) /* Bit 2: /DTR/Request Function */ #define WR14_DTRREQ (0x04) /* Bit 2: /DTR/Request Function */

6
arch/z80/src/z180/z180_irq.c
View File

@ -46,9 +46,9 @@
volatile chipreg_t *g_current_regs; volatile chipreg_t *g_current_regs;
/* This holds the value of the MMU's CBR register. This value is set to the /* This holds the value of the MMU's CBR register. This value is set to the
* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR if * interrupted tasks's CBR on interrupt entry, changed to the new task's CBR
* an interrupt level context switch occurs, and restored on interrupt exit. In * if an interrupt level context switch occurs, and restored on interrupt
* this way, the CBR is always correct on interrupt exit. * exit. In this way, the CBR is always correct on interrupt exit.
*/ */
uint8_t current_cbr; uint8_t current_cbr;

5
arch/z80/src/z180/z180_mmu.c
View File

@ -41,6 +41,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/ /* Configuration ************************************************************/
#ifndef CONFIG_ARCH_ADDRENV #ifndef CONFIG_ARCH_ADDRENV
@ -66,7 +67,8 @@ static struct z180_cbr_s g_cbrs[CONFIG_MAX_TASKS];
* Name: z180_mmu_alloccbr * Name: z180_mmu_alloccbr
* *
* Description: * Description:
* Find an unused structure in g_cbrs (i.e., one with reference count == 0). * Find an unused structure in g_cbrs
* (i.e., one with reference count == 0).
* If a structure is found, its reference count is set to one and a pointer * If a structure is found, its reference count is set to one and a pointer
* to the structure is returned. * to the structure is returned.
* *
@ -187,6 +189,7 @@ return g_physhandle ? OK : -ENOMEM;
* environment when a task/thread exits. * environment when a task/thread exits.
* *
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: up_addrenv_create * Name: up_addrenv_create
* *

3
arch/z80/src/z180/z180_mmu.h
View File

@ -34,6 +34,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/ /* Configuration ************************************************************/
/* Virtual addresses */ /* Virtual addresses */
@ -100,7 +101,7 @@
#define Z180_BBR_VALUE ((CONFIG_Z180_BANKAREA_PHYSBASE >> 12) & 0xff) #define Z180_BBR_VALUE ((CONFIG_Z180_BANKAREA_PHYSBASE >> 12) & 0xff)
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************

19
arch/z80/src/z180/z180_scc.c
View File

@ -258,8 +258,8 @@ static uart_dev_t g_escca_port =
}; };
#endif #endif
/* Now, which one with be tty0/console and which tty1? NOTE: SCC and ESCCA/B and /* Now, which one with be tty0/console and which tty1? NOTE: SCC and ESCCA/B
* mutually exclusive. * and mutually exclusive.
*/ */
#undef CONSOLE_DEV #undef CONSOLE_DEV
@ -389,14 +389,15 @@ static void z180_shutdown(struct uart_dev_s *dev)
* Name: z180_attach * Name: z180_attach
* *
* Description: * Description:
* Configure the UART to operation in interrupt driven mode. This method is * Configure the UART to operation in interrupt driven mode. This method
* called when the serial port is opened. Normally, this is just after the * is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in * the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase. * a non-interrupt driven mode during the boot phase.
* *
* RX and TX interrupts are not enabled when by the attach method (unless the * RX and TX interrupts are not enabled when by the attach method (unless
* hardware supports multiple levels of interrupt enabling). The RX and TX * the hardware supports multiple levels of interrupt enabling). The RX
* interrupts are not enabled until the txint() and rxint() methods are called. * and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
* *
****************************************************************************/ ****************************************************************************/
@ -410,8 +411,8 @@ static int z180_attach(struct uart_dev_s *dev)
* *
* Description: * Description:
* Detach UART interrupts. This method is called when the serial port is * Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception * closed normally just before the shutdown method is called. The
* is the serial console which is never shutdown. * exception is the serial console which is never shutdown.
* *
****************************************************************************/ ****************************************************************************/

2
arch/z80/src/z180/z180_serial.h
View File

@ -35,7 +35,7 @@
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************

8
arch/z80/src/z180/z180_timerisr.c
View File

@ -38,6 +38,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* "The Z180 contains a two channel 16-bit Programmable Reload Timer. Each /* "The Z180 contains a two channel 16-bit Programmable Reload Timer. Each
* PRT channel contains a 16-bit down counter and a 16-bit reload register." * PRT channel contains a 16-bit down counter and a 16-bit reload register."
* Channel 0 is dedicated as the system timer. * Channel 0 is dedicated as the system timer.
@ -71,9 +72,9 @@
static int z180_timerisr(int irq, chipreg_t *regs, void *arg) static int z180_timerisr(int irq, chipreg_t *regs, void *arg)
{ {
/* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt /* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an
* request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and * interrupt request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR
* the higher or lower byte of TMDR0 is read." * is read and the higher or lower byte of TMDR0 is read."
*/ */
inp(Z180_PRT_TCR); inp(Z180_PRT_TCR);
@ -104,6 +105,7 @@ void up_timer_initialize(void)
uint8_t regval; uint8_t regval;
/* Configure PRT0 to interrupt at the requested rate */ /* Configure PRT0 to interrupt at the requested rate */
/* First stop PRT0 and disable interrupts */ /* First stop PRT0 and disable interrupts */
regval = inp(Z180_PRT_TCR); regval = inp(Z180_PRT_TCR);

2
arch/z80/src/z8/chip.h
View File

@ -85,7 +85,7 @@
#define Z8_TIMERCTL_GATED _HX(06) #define Z8_TIMERCTL_GATED _HX(06)
#define Z8_TIMERCTL_CAPCMP _HX(07) #define Z8_TIMERCTL_CAPCMP _HX(07)
/* UART Register Offsets *************************************************************/ /* UART Register Offsets ************************************************************/
#define Z8_UART_TXD _HX(00) /* 8-bits: UART Transmit Data */ #define Z8_UART_TXD _HX(00) /* 8-bits: UART Transmit Data */
#define Z8_UART_RXD _HX(00) /* 8-bits: UART Receive Data */ #define Z8_UART_RXD _HX(00) /* 8-bits: UART Receive Data */

6
arch/z80/src/z8/switch.h
View File

@ -39,7 +39,8 @@
/* Z8_IRQSTATE_* definitions ******************************************************** /* Z8_IRQSTATE_* definitions ********************************************************
* These are used in the state field of 'struct z8_irqstate_s' structure to define * These are used in the state field of 'struct z8_irqstate_s' structure to define
* the current state of the interrupt handling. These definition support "lazy" * the current state of the interrupt handling. These definition support "lazy"
* interrupt context saving. See comments below associated with s'truct z8_irqstate_s'. * interrupt context saving. See comments below associated with s'truct
* z8_irqstate_s'.
*/ */
#define Z8_IRQSTATE_NONE 0 /* Not handling an interrupt */ #define Z8_IRQSTATE_NONE 0 /* Not handling an interrupt */
@ -228,7 +229,8 @@ void z8_restorecontext(FAR chipreg_t *regs);
/* Defined in z8_sigsetup.c */ /* Defined in z8_sigsetup.c */
void z8_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); void z8_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver,
FAR chipreg_t *regs);
/* Defined in z8_registerdump.c */ /* Defined in z8_registerdump.c */

4
arch/z80/src/z8/z8_i2c.c
View File

@ -282,7 +282,9 @@ static int z8_i2c_read_transfer(FAR struct z8_i2cdev_s *priv,
I2CCTL |= I2C_CTL_NAK; I2CCTL |= I2C_CTL_NAK;
} }
/* If this was the last byte, then set STOP and return success */ /* If this was the last byte, then set STOP and return
* success
*/
else if (count == 1) else if (count == 1)
{ {

4
arch/z80/src/z8/z8_irq.c
View File

@ -36,7 +36,9 @@
* Public Data * Public Data
****************************************************************************/ ****************************************************************************/
/* This structure holds information about the current interrupt processing state */ /* This structure holds information about the current interrupt processing
* state
*/
struct z8_irqstate_s g_z8irqstate; struct z8_irqstate_s g_z8irqstate;

1
arch/z80/src/z8/z8_registerdump.c
View File

@ -76,6 +76,7 @@ void z8_registerdump(void)
switch (g_z8irqstate.state) switch (g_z8irqstate.state)
{ {
case Z8_IRQSTATE_ENTRY: case Z8_IRQSTATE_ENTRY:
/* Calculate the source address based on the saved RP value */ /* Calculate the source address based on the saved RP value */
rp = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS] >> 8; rp = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS] >> 8;

12
arch/z80/src/z8/z8_saveirqcontext.c
View File

@ -81,7 +81,9 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
FAR chipreg_t *src = (FAR uint16_t *)(rp & 0xf0); FAR chipreg_t *src = (FAR uint16_t *)(rp & 0xf0);
FAR chipreg_t *dest = &regs[XCPT_RR0]; FAR chipreg_t *dest = &regs[XCPT_RR0];
/* Copy the interrupted tasks register into the TCB register save area. */ /* Copy the interrupted tasks register into the TCB register save
* area.
*/
int i; int i;
for (i = 0; i < XCPTCONTEXT_REGS; i++) for (i = 0; i < XCPTCONTEXT_REGS; i++)
@ -89,7 +91,9 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
*dest++ = *src++; *dest++ = *src++;
} }
/* Since the task was interrupted, we know that interrupts were enabled */ /* Since the task was interrupted, we know that interrupts were
* enabled
*/
regs[XCPT_IRQCTL] = 0x0080; /* IRQE bit will enable interrupts */ regs[XCPT_IRQCTL] = 0x0080; /* IRQE bit will enable interrupts */
@ -107,8 +111,8 @@ void z8_saveirqcontext(FAR chipreg_t *regs)
regs[XCPT_RPFLAGS] = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS]; regs[XCPT_RPFLAGS] = g_z8irqstate.regs[Z8_IRQSAVE_RPFLAGS];
regs[XCPT_PC] = g_z8irqstate.regs[Z8_IRQSAVE_PC]; regs[XCPT_PC] = g_z8irqstate.regs[Z8_IRQSAVE_PC];
/* Now update the IRQ save area so that we will know that we have already /* Now update the IRQ save area so that we will know that we have
* done this. * already done this.
*/ */
g_z8irqstate.state = Z8_IRQSTATE_SAVED; g_z8irqstate.state = Z8_IRQSTATE_SAVED;

30
arch/z80/src/z8/z8_serial.c
View File

@ -257,8 +257,10 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev)
{ {
struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv;
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
uint8_t state = priv->rxenabled ? STATE_RXENABLED : STATE_DISABLED | \ uint8_t state = priv->rxenabled ?
priv->txenabled ? STATE_TXENABLED : STATE_DISABLED; STATE_RXENABLED : STATE_DISABLED | \
priv->txenabled ?
STATE_TXENABLED : STATE_DISABLED;
z8_txint(dev, false); z8_txint(dev, false);
z8_rxint(dev, false); z8_rxint(dev, false);
@ -297,6 +299,7 @@ static void z8_consoleput(uint8_t ch)
break; break;
} }
} }
z8_putuart(priv, ch, Z8_UART_TXD); z8_putuart(priv, ch, Z8_UART_TXD);
} }
@ -415,14 +418,15 @@ static void z8_shutdown(FAR struct uart_dev_s *dev)
* Name: z8_attach * Name: z8_attach
* *
* Description: * Description:
* Configure the UART to operation in interrupt driven mode. This method is * Configure the UART to operation in interrupt driven mode. This method
* called when the serial port is opened. Normally, this is just after the * is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in * the the setup() method is called, however, the serial console may
* a non-interrupt driven mode during the boot phase. * operate in a non-interrupt driven mode during the boot phase.
* *
* RX and TX interrupts are not enabled when by the attach method (unless the * RX and TX interrupts are not enabled when by the attach method (unless
* hardware supports multiple levels of interrupt enabling). The RX and TX * the hardware supports multiple levels of interrupt enabling). The RX
* interrupts are not enabled until the txint() and rxint() methods are called. * and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
* *
****************************************************************************/ ****************************************************************************/
@ -444,6 +448,7 @@ static int z8_attach(FAR struct uart_dev_s *dev)
irq_detach(priv->rxirq); irq_detach(priv->rxirq);
} }
} }
return ret; return ret;
} }
@ -452,8 +457,8 @@ static int z8_attach(FAR struct uart_dev_s *dev)
* *
* Description: * Description:
* Detach UART interrupts. This method is called when the serial port is * Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is * closed normally just before the shutdown method is called. The
* the serial console which is never shutdown. * exception is the serial console which is never shutdown.
* *
****************************************************************************/ ****************************************************************************/
@ -500,6 +505,7 @@ static int z8_rxinterrupt(int irq, FAR void *context, FAR void *arg)
uart_recvchars(dev); uart_recvchars(dev);
} }
return OK; return OK;
} }
@ -530,6 +536,7 @@ static int z8_txinterrupt(int irq, FAR void *context, FAR void *arg)
uart_xmitchars(dev); uart_xmitchars(dev);
} }
return OK; return OK;
} }
@ -700,6 +707,7 @@ void z80_serial_initialize(void)
z8_disableuartirq(&TTYS1_DEV); z8_disableuartirq(&TTYS1_DEV);
/* Initialize the console for early use */ /* Initialize the console for early use */
CONSOLE_DEV.isconsole = true; CONSOLE_DEV.isconsole = true;
z8_setup(&CONSOLE_DEV); z8_setup(&CONSOLE_DEV);

2
arch/z80/src/z80/z80_io.c
View File

@ -24,6 +24,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
/* #include <nuttx/irq.h> */ /* #include <nuttx/irq.h> */
#include "z80_internal.h" #include "z80_internal.h"
@ -61,7 +62,6 @@ void outp(char p, char c)
__endasm; __endasm;
} }
/**************************************************************************** /****************************************************************************
* Name: inpb * Name: inpb
* *