Add Ethernet descriptor definitions and initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4158 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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@ -349,6 +349,7 @@
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#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */
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#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */
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#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM)
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/* Ethernet MAC address 0 high register */
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@ -643,12 +644,177 @@
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/* Ethernet DMA current host transmit buffer address register (32-bit address) */
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/* Ethernet DMA current host receive buffer address register (32-bit address) */
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/* DMA Descriptors **********************************************************************************/
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/* TDES0: Transmit descriptor Word0 */
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#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */
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#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */
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#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */
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#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */
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#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT)
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#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
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#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
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#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */
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#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */
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#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */
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#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
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#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
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#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
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#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */
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#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */
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#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */
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#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */
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#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */
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#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */
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#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT)
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# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */
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# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */
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# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */
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# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */
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#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */
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#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */
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#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */
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#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */
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#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */
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#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */
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#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */
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/* TDES1: Transmit descriptor Word1 */
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#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */
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#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT)
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#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */
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#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT)
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/* TDES2: Transmit descriptor Word2 (32-bit address) */
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/* TDES3: Transmit descriptor Word3 (32-bit address) */
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/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */
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/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */
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/* RDES0: Receive descriptor Word0 */
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#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */
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#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
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#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
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#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */
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#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */
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#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
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#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */
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#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */
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#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */
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#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */
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#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */
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#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */
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#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */
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#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
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#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */
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#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
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#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
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#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */
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#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
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#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT)
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#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */
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#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */
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/* RDES1: Receive descriptor Word1 */
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#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */
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#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT)
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#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */
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#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */
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#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */
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#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */
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#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT)
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/* RDES2: Receive descriptor Word2 (32-bit address) */
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/* RDES3: Receive descriptor Word3 (32-bit address) */
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/* RDES4: Receive descriptor Word4 */
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#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */
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#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */
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#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */
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#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT)
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# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */
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# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */
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# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */
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# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */
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# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */
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# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* 0101: Pdelay_Req (in peer-to-peer
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* transparent clock) or Announce (in
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* ordinary or boundary clock) */
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# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer
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* transparent clock) or Management (in
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* ordinary or boundary clock) */
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# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in
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* peer-to-peer transparent clock) or
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* Signaling (for ordinary or boundary
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* clock) */
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#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */
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#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */
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#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */
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#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */
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#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */
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#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */
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#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT)
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# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */
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# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */
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# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */
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/* RDES5: Receive descriptor Word5 - Reserved */
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/* RDES6: Receive descriptor Word6 (32-bit time stamp) */
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/* RDES7: Receive descriptor Word7 (32-bit time stamp) */
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/****************************************************************************************************
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* Public Functions
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* Public Types
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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/* Ethernet TX DMA Descriptor */
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struct eth_txdesc_s
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{
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/* Normal DMA descriptor words */
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volatile uint32_t tdes0; /* Status */
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volatile uint32_t tdes1; /* Control and buffer1/2 lengths */
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volatile uint32_t tdes2; /* Buffer1 address pointer */
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volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */
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/* Enhanced DMA descriptor words with time stamp */
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#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
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volatile uint32_t tdes4; /* Reserved */
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volatile uint32_t tdes5; /* Reserved */
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volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */
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volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */
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#endif
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};
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/* Ethernet RX DMA Descriptor */
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struct eth_rxdesc_s
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{
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volatile uint32_t rdes0; /* Status */
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volatile uint32_t rdes1; /* Control and buffer1/2 lengths */
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volatile uint32_t rdes2; /* Buffer1 address pointer */
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volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */
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/* Enhanced DMA descriptor words with time stamp and PTP support */
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#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
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volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */
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volatile uint32_t rdes5; /* Reserved */
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volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */
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volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */
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#endif
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};
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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@ -657,7 +823,6 @@ extern "C" {
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#define EXTERN extern
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* STM32_NETHERNET > 0 */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */
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@ -131,12 +131,13 @@
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# warning "CONFIG_STM32_ETH_PTP is not yet supported"
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#endif
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/* This driver always uses enhanced descriptors. However, this would not be
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* the cased if support is added for stamping and/or IPv4 checksum offload
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/* This driver does not use enhanced descriptors. Enhanced descriptors must
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* be used, however, if time stamping or and/or IPv4 checksum offload is
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* supported.
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*/
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#define CONFIG_STM32_ETH_ENHANCEDDESC 1
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#undef CONFIG_STM32_ETH_HWCHECKSUM
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#undef CONFIG_STM32_ETH_ENHANCEDDESC
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#undef CONFIG_STM32_ETH_HWCHECKSUM
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/* Ethernet buffer sizes and numbers */
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@ -462,6 +463,13 @@
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* Private Types
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****************************************************************************/
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struct eth_rxframe_info_s
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{
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volatile struct stm2_ethdesc_s *rxfirst; /* First Segment Rx Desc */
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volatile struct stm2_ethdesc_s *rxlast; /* Last Segment Rx Desc */
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volatile uint32_t segcount; /* Segment count */
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};
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/* The stm32_ethmac_s encapsulates all state information for a single hardware
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* interface
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*/
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@ -477,6 +485,26 @@ struct stm32_ethmac_s
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/* This holds the information visible to uIP/NuttX */
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struct uip_driver_s dev; /* Interface understood by uIP */
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/* Used to track transmit and receive descriptors */
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volatile struct eth_txdesc_s *txdesc;
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volatile struct eth_rxdesc_s *rxdesc;
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/* Frame info */
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struct eth_rxframe_info_s rxframe;
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volatile struct eth_rxframe_info_s *rxframeinfo;
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/* Descriptor allocations */
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struct eth_rxdesc_s rxtable[CONFIG_STM32_ETH_RXNBUFFERS];
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struct eth_txdesc_s txtable[CONFIG_STM32_ETH_TXNBUFFERS];
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/* Buffer allocations */
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uint8_t rxbuffer[CONFIG_STM32_ETH_RXNBUFFERS*CONFIG_STM32_ETH_RXBUFSIZE];
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uint8_t txbuffer[CONFIG_STM32_ETH_TXNBUFFERS*CONFIG_STM32_ETH_TXBUFSIZE];
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};
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/****************************************************************************
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@ -515,6 +543,11 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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#endif
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/* Descriptor Initialization */
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static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv);
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static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv);
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/* PHY Initialization */
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static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
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@ -526,6 +559,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv);
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static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv);
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static void stm32_ethreset(FAR struct stm32_ethmac_s *priv);
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static int stm32_macconfig(FAR struct stm32_ethmac_s *priv);
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static int stm32_macenable(FAR struct stm32_ethmac_s *priv);
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static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv);
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/****************************************************************************
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@ -1090,6 +1124,136 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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}
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#endif
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/****************************************************************************
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* Function: stm32_txdescinit
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*
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* Description:
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* Initializes the DMA TX descriptors in chain mode.
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*
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* Parameters:
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* priv - Reference to the driver state structure
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv)
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{
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struct eth_txdesc_s *txdesc;
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int i;
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/* Set the priv->txdesc pointer with the first descriptor in the table */
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priv->txdesc = priv->txtable;
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/* Initialize each TX descriptor */
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for (i = 0; i < CONFIG_STM32_ETH_TXNBUFFERS; i++)
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{
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txdesc = &priv->txtable[i];
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/* Set Second Address Chained bit */
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txdesc->tdes0 = ETH_TDES0_TCH;
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/* Set Buffer1 address pointer */
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txdesc->tdes2 = (uint32_t)(&priv->txbuffer[i*CONFIG_STM32_ETH_TXBUFSIZE]);
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/* Initialize the next descriptor with the Next Descriptor Polling Enable */
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if( i < (CONFIG_STM32_ETH_TXNBUFFERS-1))
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{
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/* Set next descriptor address register with next descriptor base
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* address
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*/
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txdesc->tdes3 = (uint32_t)&priv->txtable[i+1];
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}
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else
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{
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/* For last descriptor, set next descriptor address register equal
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* to the first descriptor base address
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*/
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txdesc->tdes3 = (uint32_t)priv->txtable;
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}
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}
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}
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/****************************************************************************
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* Function: stm32_rxdescinit
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*
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* Description:
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* Initializes the DMA RX descriptors in chain mode.
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*
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* Parameters:
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* priv - Reference to the driver state structure
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv)
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{
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struct eth_rxdesc_s *rxdesc;
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int i;
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/* Set the priv->rxdesc pointer with the first one of the table list */
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priv->rxdesc = priv->rxtable;
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/* Initialize each TX descriptor */
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for (i = 0; i < CONFIG_STM32_ETH_RXNBUFFERS; i++)
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{
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rxdesc = &priv->rxtable[i];
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/* Set Own bit of the Rx descriptor rdes0 */
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rxdesc->rdes0 = ETH_RDES0_OWN;
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/* Set Buffer1 size and Second Address Chained bit */
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rxdesc->rdes1 = ETH_RDES1_RCH | (uint32_t)CONFIG_STM32_ETH_RXBUFSIZE;
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/* Set Buffer1 address pointer */
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rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i*CONFIG_STM32_ETH_RXBUFSIZE];
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/* Initialize the next descriptor with the Next Descriptor Polling Enable */
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if( i < (CONFIG_STM32_ETH_RXNBUFFERS-1))
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{
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/* Set next descriptor address register with next descriptor base
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* address
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*/
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rxdesc->rdes3 = (uint32_t)&priv->rxtable[i+1];
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}
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else
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{
|
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/* For last descriptor, set next descriptor address register equal
|
||||
* to the first descriptor base address
|
||||
*/
|
||||
|
||||
rxdesc->rdes3 = (uint32_t)priv->rxtable;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Receive Descriptor List Address Register */
|
||||
|
||||
putreg32((uint32_t)priv->rxtable, STM32_ETH_DMARDLAR);
|
||||
|
||||
priv->rxframeinfo = &priv->rxframe;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_phyread
|
||||
*
|
||||
@ -1590,6 +1754,31 @@ static int stm32_macconfig(FAR struct stm32_ethmac_s *priv)
|
||||
regval |= DMABMR_SET_MASK;
|
||||
putreg32(regval, STM32_ETH_DMABMR);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_macenable
|
||||
*
|
||||
* Description:
|
||||
* Enable normal MAC operation.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_macenable(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
/* Enable RX and TX */
|
||||
#warning "Missing Logic"
|
||||
|
||||
|
||||
/* Enable Ethernet DMA interrupts.
|
||||
*
|
||||
* The STM32 hardware supports two interrupts: (1) one dedicated to normal
|
||||
@ -1599,8 +1788,11 @@ static int stm32_macconfig(FAR struct stm32_ethmac_s *priv)
|
||||
* The first Ethernet vector is reserved for interrupts generated by the
|
||||
* MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts,
|
||||
* neither of which are used by this driver.
|
||||
*
|
||||
* Ethernet DMA supports two classes of interrupts: Normal interrupt
|
||||
*/
|
||||
|
||||
putreg32(ETH_MACIMR_ALLINTS, STM32_ETH_MACIMR);
|
||||
|
||||
/* Ethernet DMA supports two classes of interrupts: Normal interrupt
|
||||
* summary (NIS) and Abnormal interrupt summary (AIS) with a variety
|
||||
* individual normal and abnormal interrupting events. Here only
|
||||
* the normal receive event is enabled (unless DEBUG is enabled). Transmit
|
||||
@ -1649,7 +1841,23 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
|
||||
|
||||
/* Initialize the MAC and DMA */
|
||||
|
||||
return stm32_macconfig(priv);
|
||||
ret = stm32_macconfig(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
|
||||
stm32_txdescinit(priv);
|
||||
|
||||
/* Initialize Rx Descriptors list: Chain Mode */
|
||||
|
||||
stm32_rxdescinit(priv);
|
||||
|
||||
/* Enable normal MAC operation */
|
||||
|
||||
return stm32_macenable(priv);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user