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Merged in paulpatience/nuttx/interrupts (pull request #80)

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efm32, lcp43, stm32, stm32l4: disable interrupts with NVIC_IRQ_CLEAR
This commit is contained in:
Gregory Nutt 2016-06-28 13:24:41 -06:00
commit 1072683892
4 changed files with 53 additions and 133 deletions
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64
arch/arm/src/efm32/efm32_irq.c
View File

@ -251,61 +251,25 @@ static inline void efm32_prioritize_syscall(int priority)
static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= EFM32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt or (a second level GPIO interrupt) */
/* Check for external interrupt or a second level GPIO interrupt */
if (irq >= EFM32_IRQ_INTERRUPTS)
{
/* Is this an external interrupt? */
if (irq < NR_VECTORS)
{
/* Yes.. We have support implemented for vectors 0-95 */
n = irq - EFM32_IRQ_INTERRUPTS;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
DEBUGASSERT(irq < (EFM32_IRQ_INTERRUPTS + 96));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
/* Check for vectors 0-31 */
if (irq < EFM32_IRQ_INTERRUPTS + 32)
#endif
while (n >= 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - EFM32_IRQ_INTERRUPTS);
n -= 32;
}
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
/* Yes.. Check for vectors 32-63 */
else
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
if (irq < EFM32_IRQ_INTERRUPTS + 64)
#endif
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 32);
}
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
/* Yes.. Check for vectors 64-95 */
else
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96)
/* Yes.. Check for vectors 64-95 */
if (irq < NR_VECTORS)
#endif
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 64);
}
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96)
else
{
return -EINVAL; /* We should never get here */
}
#endif
#endif
#endif
*bit = 1 << n;
}
else
{
@ -356,16 +320,14 @@ void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
putreg32(0, NVIC_IRQ32_63_ENABLE);
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
putreg32(0, NVIC_IRQ64_95_ENABLE);
#endif
#endif
for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
/* Colorize the interrupt stack for debug purposes */

56
arch/arm/src/lpc43xx/lpc43_irq.c
View File

@ -242,53 +242,23 @@ static inline void lpc43_prioritize_syscall(int priority)
static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= LPC43_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= LPC43_IRQ_EXTINT)
{
/* NOTE: We assume that there are at least 32 interrupts */
n = irq - LPC43_IRQ_EXTINT;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
if (irq < (LPC43_IRQ_EXTINT + 32))
while (n >= 32)
{
/* Interrupt in range {0-31} */
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT);
n -= 32;
}
#if LPC43M4_IRQ_NEXTINT > 95
# error Extension to interrupt logic needed
#elif LPC43M4_IRQ_NEXTINT > 63
else if (irq < (LPC43_IRQ_EXTINT + 64))
{
/* Interrupt in range {32-63} */
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
}
else if (irq < LPC43M4_IRQ_NIRQS)
{
/* Interrupt in range {64-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 95 */
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 64);
}
#else /* if LPC43M4_IRQ_NEXTINT > 31 */
else if (irq < LPC43M4_IRQ_NIRQS)
{
/* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
}
#endif
else
{
/* Interrupt >= LPC43M4_IRQ_NIRQS */
return ERROR; /* Invalid interrupt */
}
*bit = 1 << n;
}
/* Handle processor exceptions. Only a few can be disabled */
@ -342,16 +312,14 @@ void up_irqinitialize(void)
uint32_t regval;
#endif
int num_priority_registers;
int i;
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
#if LPC43M4_IRQ_NEXTINT > 31
putreg32(0, NVIC_IRQ32_63_ENABLE);
#if LPC43M4_IRQ_NEXTINT > 63
putreg32(0, NVIC_IRQ64_95_ENABLE);
#endif
#endif
for (i = 0; i < LPC43M4_IRQ_NEXTINT; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is

33
arch/arm/src/stm32/stm32_irq.c
View File

@ -245,31 +245,23 @@ static inline void stm32_prioritize_syscall(int priority)
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= STM32_IRQ_FIRST)
{
if (irq < STM32_IRQ_FIRST + 32)
n = irq - STM32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
while (n >= 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_FIRST);
}
else if (irq < STM32_IRQ_FIRST + 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_FIRST - 32);
}
else if (irq < NR_IRQS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_FIRST - 64);
}
else
{
return ERROR; /* Invalid interrupt */
n -= 32;
}
*bit = 1 << n;
}
/* Handle processor exceptions. Only a few can be disabled */
@ -315,11 +307,14 @@ void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
putreg32(0, NVIC_IRQ32_63_ENABLE);
for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Colorize the interrupt stack for debug purposes */

33
arch/arm/src/stm32l4/stm32l4_irq.c
View File

@ -244,31 +244,23 @@ static inline void stm32l4_prioritize_syscall(int priority)
static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= STM32L4_IRQ_FIRST)
{
if (irq < STM32L4_IRQ_FIRST + 32)
n = irq - STM32L4_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
while (n >= 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - STM32L4_IRQ_FIRST);
}
else if (irq < STM32L4_IRQ_FIRST + 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - STM32L4_IRQ_FIRST - 32);
}
else if (irq < NR_IRQS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - STM32L4_IRQ_FIRST - 64);
}
else
{
return ERROR; /* Invalid interrupt */
n -= 32;
}
*bit = 1 << n;
}
/* Handle processor exceptions. Only a few can be disabled */
@ -314,11 +306,14 @@ void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
putreg32(0, NVIC_IRQ32_63_ENABLE);
for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Colorize the interrupt stack for debug purposes */