diff --git a/arch/arm/src/armv7-m/arch_clean_dcache.c b/arch/arm/src/armv7-m/arch_clean_dcache.c new file mode 100644 index 0000000000..7813e0cc36 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_clean_dcache.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_clean_dcache.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void arch_clean_dcache(uintptr_t start, uintptr_t end) +{ + uint32_t ccsidr; + uint32_t smask; + uint32_t sshift; + uint32_t ways; + uint32_t wshift; + uint32_t ssize; + uint32_t set; + uint32_t sw; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCSW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + /* Clean the D-Cache over the range of addresses */ + + ssize = (1 << sshift); + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + int32_t tmpways = ways; + + /* Isolate the cache line associated with this address. For example + * if the cache line size is 32 bytes and the cache size is 16KB, then + * + * sshift = 5 : Offset to the beginning of the set field + * smask = 0x007f : Mask of the set field + */ + + set = ((uint32_t)start >> sshift) & smask; + + /* Clean and invalidate each way for this cacheline */ + + do + { + sw = ((tmpways << wshift) | (set << sshift)); + putreg32(sw, NVIC_DCCSW); + } + while (tmpways--); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_clean_dcache_all.c b/arch/arm/src/armv7-m/arch_clean_dcache_all.c new file mode 100644 index 0000000000..f3d3ef6029 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_clean_dcache_all.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_clean_dcache_all.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void arch_clean_dcache_all(void) +{ + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCSW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Clean the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCSW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_disable_dcache.c b/arch/arm/src/armv7-m/arch_disable_dcache.c new file mode 100644 index 0000000000..c21c8cb8f7 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_disable_dcache.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_disable_dcache.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arch_disable_dcache(void) +{ + uint32_t ccsidr; + uint32_t ccr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Disable the D-Cache */ + + ccr = getreg32(NVIC_CFGCON); + ccr &= ~NVIC_CFGCON_DC; + putreg32(ccr, NVIC_CFGCON); + + /* Clean and invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_enable_dcache.c b/arch/arm/src/armv7-m/arch_enable_dcache.c new file mode 100644 index 0000000000..ad0c82fef2 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_enable_dcache.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_enable_dcache.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arch_enable_dcache(void) +{ + uint32_t ccsidr; + uint32_t ccr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + /* Invalidate the entire D-Cache */ + + ARM_DSB(); + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCISW); + } + while (tmpways--); + } + while(sets--); + + ARM_DSB(); + + /* Enable the D-Cache */ + + ccr = getreg32(NVIC_CFGCON); + ccr |= NVIC_CFGCON_DC; + putreg32(ccr, NVIC_CFGCON); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_flush_dcache.c b/arch/arm/src/armv7-m/arch_flush_dcache.c new file mode 100644 index 0000000000..07fbae6245 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_flush_dcache.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_flush_dcache.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void arch_flush_dcache(uintptr_t start, uintptr_t end) +{ + uint32_t ccsidr; + uint32_t smask; + uint32_t sshift; + uint32_t ways; + uint32_t wshift; + uint32_t ssize; + uint32_t set; + uint32_t sw; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + /* Clean and invalidate the D-Cache over the range of addresses */ + + ssize = (1 << sshift); + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + int32_t tmpways = ways; + + /* Isolate the cache line associated with this address. For example + * if the cache line size is 32 bytes and the cache size is 16KB, then + * + * sshift = 5 : Offset to the beginning of the set field + * smask = 0x007f : Mask of the set field + */ + + set = ((uint32_t)start >> sshift) & smask; + + /* Clean and invalidate each way for this cacheline */ + + do + { + sw = ((tmpways << wshift) | (set << sshift)); + putreg32(sw, NVIC_DCCISW); + } + while (tmpways--); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_flush_dcache_all.c b/arch/arm/src/armv7-m/arch_flush_dcache_all.c new file mode 100644 index 0000000000..c25e665123 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_flush_dcache_all.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_flush_dcache_all.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void arch_flush_dcache_all(void) +{ + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Clean and invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_invalidate_dcache.c b/arch/arm/src/armv7-m/arch_invalidate_dcache.c new file mode 100644 index 0000000000..899252cde7 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_invalidate_dcache.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_invalidate_dcache.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void arch_invalidate_dcache(uintptr_t start, uintptr_t end) +{ + uint32_t ccsidr; + uint32_t smask; + uint32_t sshift; + uint32_t ways; + uint32_t wshift; + uint32_t ssize; + uint32_t set; + uint32_t sw; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + /* Invalidate the D-Cache over the range of addresses */ + + ssize = (1 << sshift); + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + int32_t tmpways = ways; + + /* Isolate the cache line associated with this address. For example + * if the cache line size is 32 bytes and the cache size is 16KB, then + * + * sshift = 5 : Offset to the beginning of the set field + * smask = 0x007f : Mask of the set field + */ + + set = ((uint32_t)start >> sshift) & smask; + + /* Clean and invalidate each way for this cacheline */ + + do + { + sw = ((tmpways << wshift) | (set << sshift)); + putreg32(sw, NVIC_DCISW); + } + while (tmpways--); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c b/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c new file mode 100644 index 0000000000..380d7d5015 --- /dev/null +++ b/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arch_invalidate_dcache_all.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "cache.h" + +#ifdef CONFIG_ARMV7M_DCACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arch_invalidate_dcache_all(void) +{ + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} + +#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/cache.h b/arch/arm/src/armv7-m/cache.h index b41dce7174..b1d2119288 100644 --- a/arch/arm/src/armv7-m/cache.h +++ b/arch/arm/src/armv7-m/cache.h @@ -54,7 +54,16 @@ * Pre-processor Definitions ****************************************************************************/ -/* Cache Size ID (CCSIDR) register macros used by inline function s*/ +/* Cache Size ID (CCSIDR) register macros used by inline functions + * Given the value of the CCSIDR reginer (n): + * + * CCSIDR_WAYS - Returns the (number of ways) - 1 + * CCSIDR_SETS - Returns the (number of sets) - 1 + * CCSIDR_LSSHIFT - Returns log2(cache line size in words) - 2 + * Eg. 0 -> 4 words + * 1 -> 8 words + * ... + */ #define CCSIDR_WAYS(n) \ (((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT) diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index a8f5049eec..3b5ca6007d 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -616,7 +616,7 @@ /* Cache Size Selection Register (Cortex-M7) */ #define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */ -# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instructin Cache */ +# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instruction Cache */ # define NVIC_CSSELR_IND_DCACHE (1 << 0) /* 1=Data Cache */ #define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */ diff --git a/arch/arm/src/armv7-m/up_dcache.c b/arch/arm/src/armv7-m/up_dcache.c deleted file mode 100644 index db6d899936..0000000000 --- a/arch/arm/src/armv7-m/up_dcache.c +++ /dev/null @@ -1,429 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/up_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#ifdef CONFIG_ARMV7M_DCACHE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_enable_dcache(void) -{ - uint32_t ccsidr; - uint32_t ccr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = arm_clz(ways) & 0x1f; - - /* Invalidate the D-Cache */ - - ARM_DSB(); - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCISW); - } - while (tmpways--); - } - while(sets--); - ARM_DSB(); - - /* Enable the D-Cache */ - - ccr = getreg32(NVIC_CFGCON); - ccr |= NVIC_CFGCON_DC; - putreg32(ccr, NVIC_CFGCON); - - ARM_DSB(); - ARM_ISB(); -} - -/**************************************************************************** - * Name: arch_disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_disable_dcache(void) -{ - uint32_t ccsidr; - uint32_t ccr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Disable the D-Cache */ - - ccr = getreg32(NVIC_CFGCON); - ccr &= ~NVIC_CFGCON_DC; - putreg32(ccr, NVIC_CFGCON); - - /* Clean and invalidate the D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -/**************************************************************************** - * Name: arch_invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#if 0 /* Not implemented */ -void arch_invalidate_dcache(uintptr_t start, uintptr_t end) -{ -#warning Missing logic -} -#endif - -/**************************************************************************** - * Name: arch_invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_invalidate_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Invalidate D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -/**************************************************************************** - * Name: arch_clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#if 0 /* Not implemented */ -void arch_clean_dcache(uintptr_t start, uintptr_t end) -{ -#warning Missing logic -} -#endif - -/**************************************************************************** - * Name: arch_clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_clean_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Clean D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCSW); - } - while (tmpways--); - } - while(sets--); - - ARM_DSB(); - ARM_ISB(); -} - -/**************************************************************************** - * Name: arch_flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#if 0 /* Not implemented */ -void arch_flush_dcache(uintptr_t start, uintptr_t end) -{ -#warning Missing logic -} -#endif - -/**************************************************************************** - * Name: arch_flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_flush_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Clean and invalidate D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 868621c931..e08bfa4437 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -65,7 +65,10 @@ CMN_CSRCS += up_vectors.c endif ifeq ($(CONFIG_ARMV7M_DCACHE),y) -CMN_CSRCS += up_dcache.c +CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c +CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c +CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c +CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c endif ifeq ($(CONFIG_ARCH_FPU),y)