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STM32 F3: Fix more SPI issues

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This commit is contained in:
Gregory Nutt 2016-08-12 19:00:34 -06:00
parent 3383a25c38
commit 10f90a1738
2 changed files with 49 additions and 18 deletions
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50
arch/arm/src/stm32/stm32_spi.c
View File

@ -624,7 +624,11 @@ static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t word)
static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv)
{
#ifdef CONFIG_STM32_STM32F30XX
return (priv->nbits > 8);
#else
return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0);
#endif
}
/************************************************************************************
@ -1179,10 +1183,32 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
#ifdef CONFIG_STM32_STM32F30XX
DEBUGASSERT(nbits >= 8 && nbits <= 16)'
/* Yes... Set CR2 appropriately */
/* Set the number of bits (valid range 4-16) */
if (nbits < 4 || nbits > 16)
{
return;
}
clrbits = SPI_CR2_DS_MASK;
setbits = SPI_CR2_DS(nbits);
/* If nbits is <=8, then we are in byte mode and FRXTH shall be set
* (else, transaction will not complete).
*/
if (nbits < 9)
{
setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
}
else
{
clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
}
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr2(priv, SPI_CR2_DS(nbits), SPI_CR2_DS_MASK);
spi_modifycr2(priv, setbits, clearbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#else
/* Yes... Set CR1 appropriately */
@ -1541,6 +1567,25 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
uint16_t setbits;
uint16_t clrbits;
#ifdef CONFIG_STM32_STM32F30XX
/* Configure CR1 and CR2. Default configuration:
* Mode 0: CR1.CPHA=0 and CR1.CPOL=0
* Master: CR1.MSTR=1
* 8-bit: CR2.DS=7
* MSB tranmitted first: CR1.LSBFIRST=0
* Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 (prevents MODF error)
* Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) and CR1.RXONLY=0
*/
clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST |
SPI_CR1_RXONLY | SPI_CR1_CRCL | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
spi_modifycr1(priv, setbits, clrbits);
clrbits = SPI_CR2_DS_MASK;
setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */
spi_modifycr2(priv, setbits, clrbits);
#else
/* Configure CR1. Default configuration:
* Mode 0: CPHA=0 and CPOL=0
* Master: MSTR=1
@ -1554,6 +1599,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
SPI_CR1_RXONLY | SPI_CR1_DFF | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
spi_modifycr1(priv, setbits, clrbits);
#endif
priv->frequency = 0;
priv->nbits = 8;

17
arch/arm/src/stm32l4/stm32l4_spi.c
View File

@ -567,22 +567,7 @@ static inline void spi_writebyte(FAR struct stm32l4_spidev_s *priv, uint8_t byte
static inline bool spi_16bitmode(FAR struct stm32l4_spidev_s *priv)
{
uint8_t bits = priv->nbits;
/* Get the real number of bits */
if (bits < 0)
{
bits = -bits;
}
return (bits > 8);
/* Should we read the hardware regs? seems to be equivalent ~~ sebastien lorquet
* (20160413)
*/
// return ((spi_getreg(priv, STM32L4_SPI_CR2_OFFSET) & SPI_CR2_DS_MASK) == SPI_CR2_DS_16BIT);
return (priv->nbits > 8);
}
/************************************************************************************