SAMA5D2: Update matrix header file for the SAMA5D2
This commit is contained in:
Gregory Nutt
parent
94bdeda28e
commit
114f353224
@ -50,6 +50,32 @@
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* Pre-processor Definitions
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****************************************************************************************/
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#ifdef ATSAMA5D2
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/* These are bits maps of PIDs in the H64MX SPSELR registers. These are used by
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* application code to quickly determine if a given PID is served by H32MX or H64MX
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* which, in turn, is needed to know if the peripheral secured in SPSELR).
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* Reference: "In Matrix" column of "Table 9-2. Peripheral identifiers."
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*
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* NOTE that these hard-code bit values must match the PID assignments in
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* arch/arm/include/sama5/sama5*_irq.h.
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*/
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/* ARM=2, XDMAC0=6, XDMAC1=7, AES=9, AESB=10, SHA=12, MPDDRC=13, MATRIX0=15,
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* SDMMC0=31
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*/
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# define H64MX_SPSELR0_PIDS 0x8000b6c4
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/* SDMMC1=32, LCDC=45, ISC=46, QSPI0=52, QSPI1=53, L2CC=63 */
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# define H64MX_SPSELR1_PIDS 0x80306001
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/* None */
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# define H64MX_SPSELR2_PIDS 0x00000000
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#endif
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#ifdef ATSAMA5D4
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# define H64MX_DDR_SLAVE_PORT0 3
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@ -90,9 +116,12 @@
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#define SAM_MATRIX_MCFG8_OFFSET 0x0020 /* Master Configuration Register 8 */
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#define SAM_MATRIX_MCFG9_OFFSET 0x0024 /* Master Configuration Register 9 */
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define SAM_MATRIX_MCFG10_OFFSET 0x0028 /* Master Configuration Register 10 */
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# define SAM_MATRIX_MCFG11_OFFSET 0x002c /* Master Configuration Register 11 */
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#endif
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#ifdef ATSAMA5D3
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# define SAM_MATRIX_MCFG12_OFFSET 0x0030 /* Master Configuration Register 12 */
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# define SAM_MATRIX_MCFG13_OFFSET 0x0034 /* Master Configuration Register 13 */
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# define SAM_MATRIX_MCFG14_OFFSET 0x0038 /* Master Configuration Register 14 */
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@ -114,9 +143,11 @@
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#define SAM_MATRIX_SCFG11_OFFSET 0x006c /* Slave Configuration Register 11 */
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#define SAM_MATRIX_SCFG12_OFFSET 0x0070 /* Slave Configuration Register 12 */
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define SAM_MATRIX_SCFG13_OFFSET 0x0074 /* Slave Configuration Register 13 */
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# define SAM_MATRIX_SCFG14_OFFSET 0x0078 /* Slave Configuration Register 14 */
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#ifdef ATSAMA5D3
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# define SAM_MATRIX_SCFG15_OFFSET 0x007c /* Slave Configuration Register 15 */
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#endif
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@ -149,17 +180,19 @@
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#define SAM_MATRIX_PRAS12_OFFSET 0x00e0 /* Priority Register A for Slave 12 */
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#define SAM_MATRIX_PRBS12_OFFSET 0x00e4 /* Priority Register B for Slave 12 */
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#ifdef ATSAMA5D3
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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# define SAM_MATRIX_PRAS13_OFFSET 0x00e8 /* Priority Register A for Slave 13 */
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# define SAM_MATRIX_PRBS13_OFFSET 0x00ec /* Priority Register B for Slave 13 */
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# define SAM_MATRIX_PRAS14_OFFSET 0x00f0 /* Priority Register A for Slave 14 */
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# define SAM_MATRIX_PRBS14_OFFSET 0x00f4 /* Priority Register B for Slave 14 */
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#ifdef ATSAMA5D3
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# define SAM_MATRIX_PRAS15_OFFSET 0x00f8 /* Priority Register A for Slave 15 */
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# define SAM_MATRIX_PRBS15_OFFSET 0x00fc /* Priority Register B for Slave 15 */
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# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
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#endif
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_MATRIX_MEIER_OFFSET 0x0150 /* Master Error Interrupt Enable Register */
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# define SAM_MATRIX_MEIDR_OFFSET 0x0154 /* Master Error Interrupt Disable Register */
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# define SAM_MATRIX_MEIMR_OFFSET 0x0158 /* Master Error Interrupt Mask Register */
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@ -175,12 +208,17 @@
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# define SAM_MATRIX_MEAR7_OFFSET 0x017c /* Master 7 Error Address Register */
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# define SAM_MATRIX_MEAR8_OFFSET 0x0180 /* Master 8 Error Address Register */
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# define SAM_MATRIX_MEAR9_OFFSET 0x0184 /* Master 9 Error Address Register */
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# ifdef ATSAMA5D2
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# define SAM_MATRIX_MEAR10_OFFSET 0x0188 /* Master 10 Error Address Register */
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# define SAM_MATRIX_MEAR11_OFFSET 0x018c /* Master 11 Error Address Register */
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# endif
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#endif
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#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
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#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_MATRIX_SSR_OFFSET(n) (0x0200+((n)<<2))
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# define SAM_MATRIX_SSR0_OFFSET 0x0200 /* Security Slave 0 Register */
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# define SAM_MATRIX_SSR1_OFFSET 0x0204 /* Security Slave 1 Register */
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@ -196,6 +234,11 @@
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# define SAM_MATRIX_SSR11_OFFSET 0x022c /* Security Slave 11 Register */
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# define SAM_MATRIX_SSR12_OFFSET 0x0230 /* Security Slave 12 Register */
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# ifdef ATSAMA5D2
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# define SAM_MATRIX_SSR13_OFFSET 0x0234 /* Security Slave 13 Register */
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# define SAM_MATRIX_SSR14_OFFSET 0x0238 /* Security Slave 14 Register */
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# endif
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# define SAM_MATRIX_SASSR_OFFSET(n) (0x0240+((n)<<2))
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# define SAM_MATRIX_SASSR0_OFFSET 0x0240 /* Security Areas Split Slave 0 Register */
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# define SAM_MATRIX_SASSR1_OFFSET 0x0244 /* Security Areas Split Slave 1 Register */
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@ -211,6 +254,11 @@
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# define SAM_MATRIX_SASSR11_OFFSET 0x026c /* Security Areas Split Slave 11 Register */
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# define SAM_MATRIX_SASSR12_OFFSET 0x0270 /* Security Areas Split Slave 12 Register */
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# ifdef ATSAMA5D2
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# define SAM_MATRIX_SASSR13_OFFSET 0x0274 /* Security Areas Split Slave 13 Register */
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# define SAM_MATRIX_SASSR14_OFFSET 0x0275 /* Security Areas Split Slave 14 Register */
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# endif
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# define SAM_MATRIX_SRTSR_OFFSET(n) (0x0280+((n)<<2))
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# define SAM_MATRIX_SRTSR1_OFFSET 0x0284 /* Security Region Top Slave 1 Register */
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# define SAM_MATRIX_SRTSR2_OFFSET 0x0288 /* Security Region Top Slave 2 Register */
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@ -225,6 +273,11 @@
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# define SAM_MATRIX_SRTSR11_OFFSET 0x02ac /* Security Region Top Slave 11 Register */
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# define SAM_MATRIX_SRTSR12_OFFSET 0x02b0 /* Security Region Top Slave 12 Register */
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# ifdef ATSAMA5D2
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# define SAM_MATRIX_SRTSR13_OFFSET 0x02b4 /* Security Region Top Slave 13 Register */
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# define SAM_MATRIX_SRTSR14_OFFSET 0x02b8 /* Security Region Top Slave 14 Register */
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# endif
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# define SAM_MATRIX_SPSELR_OFFSET(n) (0x02c0 + ((n) << 2))
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# define SAM_MATRIX_SPSELR1_OFFSET 0x02c0 /* Security Peripheral Select 1 Register */
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# define SAM_MATRIX_SPSELR2_OFFSET 0x02c4 /* Security Peripheral Select 2 Register */
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@ -312,7 +365,7 @@
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#endif /* ATSAMA5D3 */
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* HMATRIX0 (H64MX) */
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# define SAM_MATRIX0_MCFG(n)) (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG_OFFSET(n))
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@ -327,6 +380,11 @@
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# define SAM_MATRIX0_MCFG8 (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG8_OFFSET)
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# define SAM_MATRIX0_MCFG9 (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG9_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_MCFG10 (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG10_OFFSET)
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# define SAM_MATRIX0_MCFG11 (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG11_OFFSET)
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# endif
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# define SAM_MATRIX0_SCFG(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG_OFFSET(n))
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# define SAM_MATRIX0_SCFG0 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG0_OFFSET)
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# define SAM_MATRIX0_SCFG1 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG1_OFFSET)
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@ -342,6 +400,11 @@
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# define SAM_MATRIX0_SCFG11 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG11_OFFSET)
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# define SAM_MATRIX0_SCFG12 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_SCFG13 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG13_OFFSET)
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# define SAM_MATRIX0_SCFG14 (SAM_MATRIX64_VBASE+SAM_MATRIX_SCFG14_OFFSET)
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# endif
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# define SAM_MATRIX0_PRAS(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_PRAS_OFFSET(n))
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# define SAM_MATRIX0_PRBS(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_PRBS_OFFSET(n))
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# define SAM_MATRIX0_PRAS0 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRAS0_OFFSET)
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@ -371,6 +434,13 @@
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# define SAM_MATRIX0_PRAS12 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRAS12_OFFSET)
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# define SAM_MATRIX0_PRBS12 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRBS12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_PRAS13 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRAS13_OFFSET)
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# define SAM_MATRIX0_PRBS13 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRBS13_OFFSET)
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# define SAM_MATRIX0_PRAS14 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRAS14_OFFSET)
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# define SAM_MATRIX0_PRBS15 (SAM_MATRIX64_VBASE+SAM_MATRIX_PRBS15_OFFSET)
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# endif
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# define SAM_MATRIX0_MEIER (SAM_MATRIX64_VBASE+SAM_MATRIX_MEIER_OFFSET)
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# define SAM_MATRIX0_MEIDR (SAM_MATRIX64_VBASE+SAM_MATRIX_MEIDR_OFFSET
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# define SAM_MATRIX0_MEIMR (SAM_MATRIX64_VBASE+SAM_MATRIX_MEIMR_OFFSET)
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@ -387,6 +457,11 @@
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# define SAM_MATRIX0_MEAR8 (SAM_MATRIX64_VBASE+SAM_MATRIX_MEAR8_OFFSET)
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# define SAM_MATRIX0_MEAR9 (SAM_MATRIX64_VBASE+SAM_MATRIX_MEAR9_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_MEAR10 (SAM_MATRIX64_VBASE+SAM_MATRIX_MEAR10_OFFSET)
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# define SAM_MATRIX0_MEAR11 (SAM_MATRIX64_VBASE+SAM_MATRIX_MEAR11_OFFSET)
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# endif
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# define SAM_MATRIX0_WPMR (SAM_MATRIX64_VBASE+SAM_MATRIX_WPMR_OFFSET)
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# define SAM_MATRIX0_WPSR (SAM_MATRIX64_VBASE+SAM_MATRIX_WPSR_OFFSET)
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@ -405,6 +480,11 @@
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# define SAM_MATRIX0_SSR11 (SAM_MATRIX64_VBASE+SAM_MATRIX_SSR11_OFFSET)
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# define SAM_MATRIX0_SSR12 (SAM_MATRIX64_VBASE+SAM_MATRIX_SSR12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_SSR13 (SAM_MATRIX64_VBASE+SAM_MATRIX_SSR13_OFFSET)
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# define SAM_MATRIX0_SSR14 (SAM_MATRIX64_VBASE+SAM_MATRIX_SSR14_OFFSET)
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# endif
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# define SAM_MATRIX0_SASSR(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR_OFFSET(n))
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# define SAM_MATRIX0_SASSR0 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR0_OFFSET)
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# define SAM_MATRIX0_SASSR1 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR1_OFFSET)
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@ -420,6 +500,11 @@
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# define SAM_MATRIX0_SASSR11 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR11_OFFSET)
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# define SAM_MATRIX0_SASSR12 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_SASSR13 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR13_OFFSET)
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# define SAM_MATRIX0_SASSR14 (SAM_MATRIX64_VBASE+SAM_MATRIX_SASSR14_OFFSET)
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# endif
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# define SAM_MATRIX0_SRTSR(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR_OFFSET(n))
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# define SAM_MATRIX0_SRTSR1 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR1_OFFSET)
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# define SAM_MATRIX0_SRTSR2 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR2_OFFSET)
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@ -434,6 +519,11 @@
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# define SAM_MATRIX0_SRTSR11 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR11_OFFSET)
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# define SAM_MATRIX0_SRTSR12 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX0_SRTSR13 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR13_OFFSET)
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# define SAM_MATRIX0_SRTSR14 (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR14_OFFSET)
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# endif
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# define SAM_MATRIX0_SPSELR(n) (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR_OFFSET(n))
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# define SAM_MATRIX0_SPSELR1 (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR1_OFFSET)
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# define SAM_MATRIX0_SPSELR2 (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR2_OFFSET)
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@ -453,6 +543,11 @@
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# define SAM_MATRIX1_MCFG8 (SAM_MATRIX32_VBASE+SAM_MATRIX_MCFG8_OFFSET)
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# define SAM_MATRIX1_MCFG9 (SAM_MATRIX32_VBASE+SAM_MATRIX_MCFG9_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_MCFG10 (SAM_MATRIX32_VBASE+SAM_MATRIX_MCFG10_OFFSET)
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# define SAM_MATRIX1_MCFG11 (SAM_MATRIX32_VBASE+SAM_MATRIX_MCFG11_OFFSET)
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# endif
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# define SAM_MATRIX1_SCFG(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG_OFFSET(n))
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# define SAM_MATRIX1_SCFG0 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG0_OFFSET)
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# define SAM_MATRIX1_SCFG1 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG1_OFFSET)
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@ -468,6 +563,11 @@
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# define SAM_MATRIX1_SCFG11 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG11_OFFSET)
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# define SAM_MATRIX1_SCFG12 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_SCFG13 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG13_OFFSET)
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# define SAM_MATRIX1_SCFG14 (SAM_MATRIX32_VBASE+SAM_MATRIX_SCFG14_OFFSET)
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# endif
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# define SAM_MATRIX1_PRAS(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_PRAS_OFFSET(n))
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# define SAM_MATRIX1_PRBS(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_PRBS_OFFSET(n))
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# define SAM_MATRIX1_PRAS0 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRAS0_OFFSET)
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@ -497,6 +597,13 @@
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# define SAM_MATRIX1_PRAS12 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRAS12_OFFSET)
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# define SAM_MATRIX1_PRBS12 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRBS12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_PRAS13 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRAS13_OFFSET)
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# define SAM_MATRIX1_PRBS13 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRBS13_OFFSET)
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# define SAM_MATRIX1_PRAS14 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRAS14_OFFSET)
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# define SAM_MATRIX1_PRBS15 (SAM_MATRIX32_VBASE+SAM_MATRIX_PRBS15_OFFSET)
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# endif
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# define SAM_MATRIX1_MEIER (SAM_MATRIX32_VBASE+SAM_MATRIX_MEIER_OFFSET)
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# define SAM_MATRIX1_MEIDR (SAM_MATRIX32_VBASE+SAM_MATRIX_MEIDR_OFFSET
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# define SAM_MATRIX1_MEIMR (SAM_MATRIX32_VBASE+SAM_MATRIX_MEIMR_OFFSET)
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@ -513,6 +620,11 @@
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# define SAM_MATRIX1_MEAR8 (SAM_MATRIX32_VBASE+SAM_MATRIX_MEAR8_OFFSET)
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# define SAM_MATRIX1_MEAR9 (SAM_MATRIX32_VBASE+SAM_MATRIX_MEAR9_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_MEAR10 (SAM_MATRIX32_VBASE+SAM_MATRIX_MEAR10_OFFSET)
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# define SAM_MATRIX1_MEAR11 (SAM_MATRIX32_VBASE+SAM_MATRIX_MEAR11_OFFSET)
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# endif
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# define SAM_MATRIX1_WPMR (SAM_MATRIX32_VBASE+SAM_MATRIX_WPMR_OFFSET)
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# define SAM_MATRIX1_WPSR (SAM_MATRIX32_VBASE+SAM_MATRIX_WPSR_OFFSET)
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@ -531,6 +643,11 @@
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# define SAM_MATRIX1_SSR11 (SAM_MATRIX32_VBASE+SAM_MATRIX_SSR11_OFFSET)
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# define SAM_MATRIX1_SSR12 (SAM_MATRIX32_VBASE+SAM_MATRIX_SSR12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_SSR13 (SAM_MATRIX32_VBASE+SAM_MATRIX_SSR13_OFFSET)
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# define SAM_MATRIX1_SSR14 (SAM_MATRIX32_VBASE+SAM_MATRIX_SSR14_OFFSET)
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# endif
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# define SAM_MATRIX1_SASSR(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR_OFFSET(n))
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# define SAM_MATRIX1_SASSR0 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR0_OFFSET)
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# define SAM_MATRIX1_SASSR1 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR1_OFFSET)
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@ -546,6 +663,11 @@
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# define SAM_MATRIX1_SASSR11 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR11_OFFSET)
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# define SAM_MATRIX1_SASSR12 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR12_OFFSET)
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# ifdef ATSAMA5D2
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# define SAM_MATRIX1_SASSR13 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR13_OFFSET)
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# define SAM_MATRIX1_SASSR14 (SAM_MATRIX32_VBASE+SAM_MATRIX_SASSR14_OFFSET)
|
||||
# endif
|
||||
|
||||
# define SAM_MATRIX1_SRTSR(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR_OFFSET(n))
|
||||
# define SAM_MATRIX1_SRTSR1 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR1_OFFSET)
|
||||
# define SAM_MATRIX1_SRTSR2 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR2_OFFSET)
|
||||
@ -560,12 +682,17 @@
|
||||
# define SAM_MATRIX1_SRTSR11 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR11_OFFSET)
|
||||
# define SAM_MATRIX1_SRTSR12 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR12_OFFSET)
|
||||
|
||||
# ifdef ATSAMA5D2
|
||||
# define SAM_MATRIX1_SRTSR13 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR13_OFFSET)
|
||||
# define SAM_MATRIX1_SRTSR14 (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR14_OFFSET)
|
||||
# endif
|
||||
|
||||
# define SAM_MATRIX1_SPSELR(n) (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR_OFFSET(n))
|
||||
# define SAM_MATRIX1_SPSELR1 (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR1_OFFSET)
|
||||
# define SAM_MATRIX1_SPSELR2 (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR2_OFFSET)
|
||||
# define SAM_MATRIX1_SPSELR3 (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR3_OFFSET)
|
||||
|
||||
#endif /* ATSAMA5D4 */
|
||||
#endif /* ATSAMA5D2 || ATSAMA5D4 */
|
||||
|
||||
/* MATRIX register bit definitions ******************************************************/
|
||||
/* Master Configuration Registers */
|
||||
@ -637,13 +764,16 @@
|
||||
# define MATRIX_PRBS_M9PR_MASK (3 << MATRIX_PRBS_M9PR_SHIFT)
|
||||
# define MATRIX_PRBS_M9PR(n) ((uint32_t)(n) << MATRIX_PRBS_M9PR_SHIFT)
|
||||
|
||||
#ifdef ATSAMA5D3
|
||||
#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
|
||||
# define MATRIX_PRBS_M10PR_SHIFT (8) /* Bits 8-9: Master 10 Priority */
|
||||
# define MATRIX_PRBS_M10PR_MASK (3 << MATRIX_PRBS_M10PR_SHIFT)
|
||||
# define MATRIX_PRBS_M10PR(n) ((uint32_t)(n) << MATRIX_PRBS_M10PR_SHIFT)
|
||||
# define MATRIX_PRBS_M11PR_SHIFT (12) /* Bits 12-13: Master 11 Priority */
|
||||
# define MATRIX_PRBS_M11PR_MASK (3 << MATRIX_PRBS_M11PR_SHIFT)
|
||||
# define MATRIX_PRBS_M11PR(n) ((uint32_t)(n) << MATRIX_PRBS_M11PR_SHIFT)
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D3
|
||||
# define MATRIX_PRBS_M12PR_SHIFT (16) /* Bits 16-17: Master 12 Priority */
|
||||
# define MATRIX_PRBS_M12PR_MASK (3 << MATRIX_PRBS_M12PR_SHIFT)
|
||||
# define MATRIX_PRBS_M12PR(n) ((uint32_t)(n) << MATRIX_PRBS_M12PR_SHIFT)
|
||||
@ -680,7 +810,7 @@
|
||||
# define MATRIX_MRCR_RCB15 (1 << 15) /* Bit 15: Remap Command Bit for Master 15 */
|
||||
#endif
|
||||
|
||||
#ifdef ATSAMA5D4
|
||||
#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
|
||||
/* Master Error Interrupt Enable Register, Master Error Interrupt Disable Register,
|
||||
* Master Error Interrupt Mask Register, and Master Error Status Register
|
||||
*/
|
||||
@ -697,6 +827,11 @@
|
||||
# define MATRIX_MEINT_MERR8 (1 << 8) /* Master 8 Access Error */
|
||||
# define MATRIX_MEINT_MERR9 (1 << 9) /* Master 9 Access Error */
|
||||
|
||||
# ifdef ATSAMA5D2
|
||||
# define MATRIX_MEINT_MERR10 (1 << 10) /* Master 10 Access Error */
|
||||
# define MATRIX_MEINT_MERR11 (1 << 11) /* Master 11 Access Error */
|
||||
# endif
|
||||
|
||||
/* Master 0-9 Error Address Register (32-bit addresses) */
|
||||
#endif
|
||||
|
||||
@ -713,7 +848,7 @@
|
||||
#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
|
||||
#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
#ifdef ATSAMA5D4
|
||||
#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
|
||||
/* Security Slave 0-12 Registers */
|
||||
|
||||
# define MATRIX_SSR_LANSECH_SHIFT(n) (0) /* Bits 0-7: Low Area Not Secured in HSELn Security Region, n=0..7 */
|
||||
|
||||
@ -73,7 +73,7 @@
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* .... ...M MMMM CCCC CDDI II.V .PPB BBBB
|
||||
* .... ...M MMMM CCCC CDDI IISV .PPB BBBB
|
||||
*/
|
||||
|
||||
/* Input/Output mode:
|
||||
@ -134,6 +134,14 @@
|
||||
# define PIO_INT_LOWLEVEL (4 << PIO_INT_SHIFT)
|
||||
# define PIO_INT_HIGHLEVEL (5 << PIO_INT_SHIFT)
|
||||
|
||||
/* If the pin is an interrupt, then this determines if the pin is a secure:
|
||||
*
|
||||
* .... .... .... .... .... ..S. .... ....
|
||||
*/
|
||||
|
||||
#define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure PIO */
|
||||
#define PIO_INT_UNSECURE (0)
|
||||
|
||||
/* If the pin is an PIO output, then this identifies the initial output value:
|
||||
*
|
||||
* .... .... .... .... .... ...V .... ....
|
||||
|
||||
Loading…
Reference in New Issue
Block a user