MPU: Add support for separated vs. unified MPU
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@ -68,6 +68,7 @@ config ARCH_CHIP_KINETIS
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bool "Freescale Kinetis"
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bool "Freescale Kinetis"
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select ARCH_CORTEXM4
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_RAMFUNCS
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---help---
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---help---
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@ -84,6 +85,7 @@ config ARCH_CHIP_LM
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bool "TI/Luminary Stellaris"
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bool "TI/Luminary Stellaris"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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---help---
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---help---
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TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
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TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
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@ -91,6 +93,7 @@ config ARCH_CHIP_TIVA
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bool "TI Tiva"
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bool "TI Tiva"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FPU
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---help---
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---help---
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TI Tiva TM4C architectures (ARM Cortex-M4)
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TI Tiva TM4C architectures (ARM Cortex-M4)
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@ -107,6 +110,7 @@ config ARCH_CHIP_LPC17XX
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select ARCH_CORTEXM3
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select ARCH_CORTEXM3
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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---help---
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---help---
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NXP LPC17xx architectures (ARM Cortex-M3)
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NXP LPC17xx architectures (ARM Cortex-M3)
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@ -137,6 +141,7 @@ config ARCH_CHIP_LPC43XX
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FPU
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---help---
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---help---
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NPX LPC43XX architectures (ARM Cortex-M4).
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NPX LPC43XX architectures (ARM Cortex-M4).
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@ -178,6 +183,7 @@ config ARCH_CHIP_SAM34
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bool "Atmel SAM3/SAM4"
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bool "Atmel SAM3/SAM4"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_HAVE_STACKCHECK
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select ARMV7M_HAVE_STACKCHECK
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---help---
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---help---
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@ -189,6 +195,7 @@ config ARCH_CHIP_SAMV7
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select ARMV7M_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_TICKLESS
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select ARMV7M_HAVE_STACKCHECK
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select ARMV7M_HAVE_STACKCHECK
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@ -199,6 +206,7 @@ config ARCH_CHIP_STM32
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bool "STMicro STM32 F1/F2/F3/F4"
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bool "STMicro STM32 F1/F2/F3/F4"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_HEAPCHECK
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select ARMV7M_HAVE_STACKCHECK
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select ARMV7M_HAVE_STACKCHECK
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@ -211,6 +219,7 @@ config ARCH_CHIP_STM32F7
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select ARMV7M_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_HEAPCHECK
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select ARMV7M_HAVE_STACKCHECK
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select ARMV7M_HAVE_STACKCHECK
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@ -416,6 +425,10 @@ config ARCH_DPFPU
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Enable toolchain support for double precision (64-bit) floating
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Enable toolchain support for double precision (64-bit) floating
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point if both the toolchain and the hardware support it.
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point if both the toolchain and the hardware support it.
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config ARM_HAVE_MPU_UNIFIED
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bool
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default n
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config ARM_MPU
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config ARM_MPU
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bool "MPU support"
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bool "MPU support"
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default n
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default n
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@ -86,7 +86,15 @@
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/* MPU Region Number Register Bit Definitions */
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/* MPU Region Number Register Bit Definitions */
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#define MPU_RNR_MASK (0xff)
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#ifdef CONFIG_ARM_MPU_NREGIONS <= 8
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# define MPU_RNR_MASK (0x00000007)
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#elif CONFIG_ARM_MPU_NREGIONS <= 16
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# define MPU_RNR_MASK (0x0000000f)
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#elif CONFIG_ARM_MPU_NREGIONS <= 32
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# define MPU_RNR_MASK (0x0000001f)
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#else
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# error "FIXME: Unsupported number of MPU regions"
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#endif
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/* MPU Region Base Address Register Bit Definitions */
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/* MPU Region Base Address Register Bit Definitions */
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