esp32c6/scripts: Add simpleboot support for esp32c6
This commit is contained in:
Eren Terzioglu
Xiang Xiao
parent
0fe777abd4
commit
11a061cad8
@ -126,7 +126,7 @@ config ARCH_CHIP_ESP32C6
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_BOOTLOADER
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select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_RNG
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@ -156,7 +156,7 @@ menu "Bootloader and Image Configuration"
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config ESPRESSIF_SIMPLE_BOOT
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bool
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depends on !ESPRESSIF_BOOTLOADER_MCUBOOT
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default y if ESPRESSIF_ESP32C3
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default y if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
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config ESPRESSIF_BOOTLOADER_MCUBOOT
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bool "Enable MCUboot-bootable format"
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@ -95,7 +95,7 @@ endif
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ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
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ifndef ESP_HAL_3RDPARTY_VERSION
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ESP_HAL_3RDPARTY_VERSION = 7951b5b282384ec43858a28ddfabbef7b6b326cb
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ESP_HAL_3RDPARTY_VERSION = ca8717cdfa8754caa684a44949070b8da4b6048a
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endif
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ifndef ESP_HAL_3RDPARTY_URL
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@ -276,13 +276,15 @@ static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
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* is later invalidated by the elf2image command.
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*/
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if (IS_DROM(segment_hdr.load_addr))
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if (IS_DROM(segment_hdr.load_addr) &&
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segment_hdr.load_addr == (uint32_t)_image_drom_vma)
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{
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app_drom_start = offset + sizeof(esp_image_segment_header_t);
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app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
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}
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if (IS_IROM(segment_hdr.load_addr))
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if (IS_IROM(segment_hdr.load_addr) &&
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segment_hdr.load_addr == (uint32_t)_image_irom_vma)
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{
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app_irom_start = offset + sizeof(esp_image_segment_header_t);
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app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
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@ -52,6 +52,15 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/compone
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash
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ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/include
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/private_include
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/include
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash
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INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_app_format/include
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endif
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# Linker scripts
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ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld
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@ -84,6 +93,7 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHI
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_sleep.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk_init.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c
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@ -102,8 +112,12 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/lp_timer_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/rmt_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/cache_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mpu_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mmu_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/wdt_hal_iram.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c
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@ -113,3 +127,33 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/rmt_periph.c
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ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/src/bootloader_banner_wrap.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console_loader.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_${CHIP_SERIES}.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_init.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common_loader.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_${CHIP_SERIES}.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_init.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_loader.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_efuse.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_mem.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random_${CHIP_SERIES}.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/esp_image_format.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_soc.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_sha.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/flash_encrypt.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/${CHIP_SERIES}/uart_periph.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_uart.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_sys.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_spiflash.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_fields.c
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CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
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LDFLAGS += --wrap=bootloader_print_banner
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endif
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@ -34,11 +34,9 @@
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#define SRAM_IRAM_START 0x40800000
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#define SRAM_DRAM_START 0x40800000
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#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
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/* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_DRAM_END (0x4086e610 - I_D_SRAM_OFFSET)
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#define SRAM_DRAM_END (0x4086e610)
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#define SRAM_IRAM_ORG (SRAM_IRAM_START)
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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@ -54,6 +52,13 @@
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MEMORY
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{
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#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
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/* The 0x20 offset is a convenience for the app binary image generation */
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ROM (R) : org = 0x20,
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len = IDRAM0_2_SEG_SIZE - 0x20
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#endif
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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@ -0,0 +1,411 @@
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/****************************************************************************
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* boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Default entry point: */
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ENTRY(__start);
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SECTIONS
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{
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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KEEP(*(.exception_vectors.text));
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. = ALIGN(4);
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*(.iram1)
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*(.iram1.*)
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*libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
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*libarch.a:*brownout.*(.text .text.* .literal .literal.*)
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*libarch.a:*cpu.*(.text .text.* .literal .literal.*)
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*libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
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*libarch.a:*clk.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
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*libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*pmu_init.*(.text .text.* .literal .literal.*)
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*libarch.a:*modem_clock.*(.text .text.* .literal .literal.*)
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*libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
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*libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*)
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*libarch.a:*modem_clock_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_systimer.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
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*libarch.a:*ocode_init.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_regi2c_esp32c6.*(.text .text.* .literal .literal.*)
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*libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
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*libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
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*libarch.a:*pmu_sleep.*(.text .text.* .literal .literal.*)
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*libarch.a:*pmu_param.*(.text .text.* .literal .literal.*)
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*libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
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*libarch.a:*systimer.*(.text .text.* .literal .literal.*)
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*libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
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*libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_esp32c6.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_flash_config_esp32c6.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_random_esp32c6.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
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*libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
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*libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*)
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*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*)
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*libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*)
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*libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
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*libarch.a:*log.*(.text .text.* .literal .literal.*)
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*libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
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*libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
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esp_head.*(.literal .text .literal.* .text.*)
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esp_start.*(.literal .text .literal.* .text.*)
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} >iram0_0_seg AT > ROM
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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. = ALIGN (16);
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} >iram0_0_seg
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.iram0.data :
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{
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. = ALIGN(16);
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*(.iram.data)
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*(.iram.data*)
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} >iram0_0_seg
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(16);
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*(.iram.bss)
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*(.iram.bss*)
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. = ALIGN(16);
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_iram_end = ABSOLUTE(.);
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} >iram0_0_seg
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/* This section is required to skip .iram0.text area because iram0_0_seg
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* and dram0_0_seg reflect the same address space on different buses.
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*/
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.dram0.dummy (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} >dram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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_sbss = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN (8);
|
||||
_ebss = ABSOLUTE(.);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
/* This section contains data that is not initialized during load,
|
||||
* or during the application's initialization sequence.
|
||||
*/
|
||||
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >dram0_0_seg
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_data_start = ABSOLUTE(.);
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
*(.dram1)
|
||||
*(.dram1.*)
|
||||
*libsched.a:irq_dispatch.*(.rodata .rodata.*)
|
||||
|
||||
*libarch.a:*brownout.*(.rodata .rodata.*)
|
||||
*libarch.a:*cpu.*(.rodata .rodata.*)
|
||||
*libarch.a:*gpio_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*periph_ctrl.*(.rodata .rodata.*)
|
||||
*libarch.a:*clk.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_clk.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_clk_tree.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*)
|
||||
*libarch.a:*clk_tree_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*pmu_init.*(.rodata .rodata.*)
|
||||
*libarch.a:*modem_clock.*(.rodata .rodata.*)
|
||||
*libarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
|
||||
*libarch.a:*gpio_periph.*(.rodata .rodata.*)
|
||||
*libarch.a:*modem_clock_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_systimer.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
|
||||
*libarch.a:*ocode_init.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_regi2c_esp32c6.*(.rodata .rodata.*)
|
||||
*libarch.a:*rtc_clk.*(.rodata .rodata.*)
|
||||
*libarch.a:*rtc_clk_init.*(.rodata .rodata.*)
|
||||
*libarch.a:*pmu_param.*(.rodata .rodata.*)
|
||||
*libarch.a:*pmu_sleep.*(.rodata .rodata.*)
|
||||
*libarch.a:*rtc_time.*(.rodata .rodata.*)
|
||||
*libarch.a:*systimer.*(.rodata .rodata.*)
|
||||
*libarch.a:*systimer_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*uart_hal_iram.*(.rodata .rodata.*)
|
||||
*libarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_init.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_common.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_console.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_esp32c6.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_flash.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_flash_config_esp32c6.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_efuse.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_panic.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_mem.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_random.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_random_esp32c6.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_image_format.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_soc.*(.rodata .rodata.*)
|
||||
*libarch.a:*bootloader_sha.*(.rodata .rodata.*)
|
||||
*libarch.a:*flash_encrypt.*(.rodata .rodata.*)
|
||||
*libarch.a:*cache_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*uart_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*uart_periph.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_uart.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_sys.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_efuse_fields.*(.rodata .rodata.*)
|
||||
*libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*)
|
||||
*libarch.a:*efuse_hal.*(.rodata .rodata.*)
|
||||
*libarch.a:*log.*(.rodata .rodata.*)
|
||||
*libarch.a:*log_noos.*(.rodata .rodata.*)
|
||||
*libarch.a:esp_spiflash.*(.rodata .rodata.*)
|
||||
|
||||
esp_head.*(.rodata .rodata.*)
|
||||
esp_start.*(.rodata .rodata.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
_data_end = ABSOLUTE(.);
|
||||
|
||||
/* Heap starts at the end of .data */
|
||||
|
||||
_sheap = ABSOLUTE(.);
|
||||
} >dram0_0_seg AT > ROM
|
||||
|
||||
_image_irom_vma = ADDR(.flash.text);
|
||||
_image_irom_lma = LOADADDR(.flash.text);
|
||||
_image_irom_size = SIZEOF(.flash.text);
|
||||
|
||||
.flash.text_dummy (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(0x10000);
|
||||
} > ROM
|
||||
|
||||
.flash.text :
|
||||
{
|
||||
_stext = .;
|
||||
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} >default_code_seg AT > ROM
|
||||
|
||||
.flash_rodata_dummy (NOLOAD) :
|
||||
{
|
||||
. += SIZEOF(.flash.text);
|
||||
. = ALIGN(0x10000);
|
||||
} >default_rodata_seg AT > ROM
|
||||
|
||||
_image_drom_vma = ADDR(.flash.rodata);
|
||||
_image_drom_lma = LOADADDR(.flash.rodata);
|
||||
_image_drom_size = SIZEOF(.flash.rodata);
|
||||
|
||||
.flash.rodata :
|
||||
{
|
||||
_srodata = ABSOLUTE(.);
|
||||
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
*(.srodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ constructor and destructor tables:
|
||||
* RISC-V GCC is configured with --enable-initfini-array so it emits an
|
||||
* .init_array section instead.
|
||||
*/
|
||||
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
|
||||
_einit = ABSOLUTE(.);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
_erodata = ABSOLUTE(.);
|
||||
|
||||
/* Literals are also RO data. */
|
||||
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} >default_rodata_seg AT > ROM
|
||||
|
||||
/* RTC fast memory holds RTC wake stub code !*/
|
||||
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rtc.literal .rtc.text)
|
||||
} >rtc_iram_seg
|
||||
|
||||
/* RTC BSS section. */
|
||||
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
*(.rtc.bss)
|
||||
} >rtc_iram_seg
|
||||
|
||||
/* RTC data section holds RTC wake stub data/rodata. */
|
||||
|
||||
.rtc.data :
|
||||
{
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
} >rtc_iram_seg
|
||||
|
||||
/* This section holds RTC data that should have fixed addresses.
|
||||
* The data are not initialized at power-up and are retained during deep sleep.
|
||||
*/
|
||||
.rtc_reserved (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_reserved_start = ABSOLUTE(.);
|
||||
/* New data can only be added here to ensure existing data are not moved.
|
||||
Because data have adhered to the end of the segment and code is relied on it.
|
||||
>> put new data here << */
|
||||
|
||||
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
|
||||
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
|
||||
_rtc_reserved_end = ABSOLUTE(.);
|
||||
} > rtc_reserved_seg
|
||||
|
||||
_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
|
||||
ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
|
||||
"RTC reserved segment data does not fit.")
|
||||
|
||||
}
|
||||
|
||||
@ -31,9 +31,13 @@ CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
|
||||
# pick the common linker scripts.
|
||||
|
||||
ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld
|
||||
|
||||
ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld)
|
||||
ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld)
|
||||
|
||||
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
||||
ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld)
|
||||
else
|
||||
ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld)
|
||||
endif
|
||||
|
||||
ARCHPICFLAGS = -fpic
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user