Xtensa: Separate context save/restore from coprocessor functions. Making to changes to interrupt handling to support NuttX.
This commit is contained in:
Gregory Nutt
parent
d2d60a59bf
commit
11af1fc24c
@ -33,10 +33,10 @@
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/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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*
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*
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* Low-level Call0 functions for handling generic context save and restore of
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* Low-level Call0 functions for handling generic context save and restore
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* registers not specifically addressed by the interrupt vectors and handlers.
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* of registers not specifically addressed by the interrupt vectors and
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* Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
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* handlers. Those registers (not handled by these functions) are PC, PS,
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* Except for the calls to RTOS functions, this code is generic to Xtensa.
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* A0, A1 (SP).
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*
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*
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* Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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* Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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* save regs (A12-A15), which is always the case if the handlers are coded in C.
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* save regs (A12-A15), which is always the case if the handlers are coded in C.
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@ -71,44 +71,59 @@
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/****************************************************************************
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/****************************************************************************
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* Name: _xtensa_context_save
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* Name: _xtensa_context_save
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* _xtensa_full_context_save
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*
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*
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* Description:
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* Description:
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*
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*
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* NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION!
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* NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION!
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*
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*
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* Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13,
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* These functions save Xtensa processor state:
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* in the interrupt stack frame defined in xtensa_rtos.h. Its counterpart
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* is _xtensa_context_restore (which also restores A12, A13).
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*
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*
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* Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the
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* - _xtensa_full_context_save saves all registers except PC, PS, A0, and
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* frame. This function preserves A12 & A13 in order to provide the caller
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* A1 (SP)
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* with 2 scratch regs that need not be saved over the call to this
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* - _xtensa_context_save, in addition, does not save A12-A15 which
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* function. The choice of which 2 regs to provide is governed by
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* are preserved by the callee).
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* xthal_window_spill_nw and xthal_save_extra_nw, to avoid moving data
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* more than necessary. Caller can assign regs accordingly.
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*
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*
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* Entry Conditions:
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* Caller is expected to have saved PC, PS, A0, and A1 (SP).
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*
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* The counterparts to these functions are _xtensa_context_restore() and
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* xtensa_full_context_restore().
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*
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* Entry Conditions:
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* - A0 = Return address in caller.
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* - A0 = Return address in caller.
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* - A1 = Stack pointer of interrupted thread or handler ("interruptee").
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* - A1 = Stack pointer of calling thread or interrupt handler.
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* - Original A12, A13 have already been saved in the interrupt stack
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* - Other processor state except PC, PS, A0, and A1 (SP) are as at
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* frame.
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* - Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as a
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* the point of interruption.
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* the point of interruption.
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* - If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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* - If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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*
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*
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* Exit conditions:
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* Exit conditions:
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* - A0 = Return address in caller.
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* - A0 = Return address in caller.
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* - A1 = Stack pointer of interrupted thread or handler ("interruptee").
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* - A1 = Stack pointer of interrupted thread or handler ("interruptee").
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* - A12, A13 as at entry (preserved).
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* - A12-A15 as at entry (preserved).
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* - If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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* - If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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*
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*
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****************************************************************************/
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****************************************************************************/
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.global _xtensa_full_context_save
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.global _xtensa_context_save
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.global _xtensa_context_save
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.type _xtensa_full_context_save, @function
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.type _xtensa_context_save, @function
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.type _xtensa_context_save, @function
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.align 4
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.align 4
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.literal_position
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.literal_position
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.align 4
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.align 4
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_xtensa_full_context_save:
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#ifndef CONFIG_XTENSA_CALL0_ABI
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/* Save Call0 ABI callee-saved regs a12-15. */
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s32i a12, sp, (4 * REG_A12)
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s32i a13, sp, (4 * REG_A13)
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s32i a14, sp, (4 * REG_A14)
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s32i a15, sp, (4 * REG_A15)
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#endif
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_xtensa_context_save:
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_xtensa_context_save:
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s32i a2, sp, (4 * REG_A2)
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s32i a2, sp, (4 * REG_A2)
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@ -128,6 +143,8 @@ _xtensa_context_save:
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*/
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*/
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#ifndef CONFIG_XTENSA_CALL0_ABI
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#ifndef CONFIG_XTENSA_CALL0_ABI
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s32i a12, sp, (4 * REG_A12)
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s32i a13, sp, (4 * REG_A13)
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s32i a14, sp, (4 * REG_A14)
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s32i a14, sp, (4 * REG_A14)
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s32i a15, sp, (4 * REG_A15)
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s32i a15, sp, (4 * REG_A15)
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#endif
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#endif
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@ -216,35 +233,56 @@ _xtensa_context_save:
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/****************************************************************************
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/****************************************************************************
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* Name: _xtensa_context_restore
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* Name: _xtensa_context_restore
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* _xtensa_full_context_restore
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*
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*
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* Description:
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* Description:
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*
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*
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* NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION!
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* NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION!
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*
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*
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* Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in
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* These functions restores Xtensa processor state and differ in which
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* Call0 ABI, A14, A15 which are preserved by all interrupt handlers) from
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* registers are saved:
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* an interrupt stack frame defined in xtensa_rtos.h.
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* Its counterpart is _xtensa_context_save (whose caller saved A12, A13).
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*
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*
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* Caller is responsible to restore PC, PS, A0, A1 (SP).
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* - _xtensa_full_context_restore restores all registers except PC, PS,
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* A0, and A1 (SP)
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* - _xtensa_context_restore, in addition, does not restore A12-A15 which
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* are preserved by the callee).
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*
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* The caller is responsible for restoring PC, PS, A0, A1 (SP) in both cases.
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*
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* _xtensa_context_save and _xtensa_full_context_save are the counterparts
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* to these functions.
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*
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*
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* Entry Conditions:
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* Entry Conditions:
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* - A0 = Return address in caller.
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* - A0 = Return address in caller.
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* - A1 = Stack pointer of interrupted thread or handler ("interruptee").
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* - A1 = Stack pointer of calling thread or interrupt handler.
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*
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*
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* Exit conditions:
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* Exit conditions:
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* - A0 = Return address in caller.
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* - A0 = Return address in caller.
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* - A1 = Stack pointer of interrupted thread or handler ("interruptee").
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* - A1 = Stack pointer of calling thread or interrupt handler.
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* - Other processor state except PC, PS, A0, A1 (SP), is as at the point
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* - Other registers are restored as detailed above.
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* of interruption.
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*
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*
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****************************************************************************/
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****************************************************************************/
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.global _xtensa_full_context_restore
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.global _xtensa_context_restore
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.global _xtensa_context_restore
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.type _xtensa_full_context_restore,@function
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.type _xtensa_context_restore,@function
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.type _xtensa_context_restore,@function
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.align 4
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.align 4
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.literal_position
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.literal_position
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.align 4
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.align 4
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_xtensa_full_context_restore:
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#ifndef CONFIG_XTENSA_CALL0_ABI
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/* Restore Call0 ABI callee-saved regs a12-15. */
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l32i a12, sp, (4 * REG_A12)
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l32i a13, sp, (4 * REG_A13)
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l32i a14, sp, (4 * REG_A14)
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l32i a15, sp, (4 * REG_A15)
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#endif
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_xtensa_context_restore:
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_xtensa_context_restore:
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#if XCHAL_EXTRA_SA_SIZE > 0
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#if XCHAL_EXTRA_SA_SIZE > 0
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@ -259,6 +297,7 @@ _xtensa_context_restore:
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mov a13, a0 /* Preserve ret addr */
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mov a13, a0 /* Preserve ret addr */
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addi a2, sp, (4 * REG_EXTRA) /* Where to find it */
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addi a2, sp, (4 * REG_EXTRA) /* Where to find it */
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#if XCHAL_EXTRA_SA_ALIGN > 16
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#if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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and a2, a2, a3 /* Align dynamically >16 bytes */
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and a2, a2, a3 /* Align dynamically >16 bytes */
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@ -322,339 +361,11 @@ _xtensa_context_restore:
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* so need to be restored anyway, despite being callee-saved in Call0.
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* so need to be restored anyway, despite being callee-saved in Call0.
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*/
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*/
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#ifndef CONFIG_XTENSA_CALL0_ABI
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l32i a12, sp, (4 * REG_A12)
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l32i a12, sp, (4 * REG_A12)
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l32i a13, sp, (4 * REG_A13)
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l32i a13, sp, (4 * REG_A13)
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#ifndef CONFIG_XTENSA_CALL0_ABI
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l32i a14, sp, (4 * REG_A14)
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l32i a14, sp, (4 * REG_A14)
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l32i a15, sp, (4 * REG_A15)
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l32i a15, sp, (4 * REG_A15)
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#endif
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#endif
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ret
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ret
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/****************************************************************************
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* Name: _xt_coproc_init
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*
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* Description:
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* Initializes global co-processor management data, setting all co-
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* processors to "unowned". Leaves CPENABLE as it found it (does NOT clear
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* it).
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*
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* Called during initialization of the RTOS, before any threads run.
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*
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* This may be called from normal Xtensa single-threaded application code
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* which might use co-processors. The Xtensa run-time initialization enables
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* all co-processors. They must remain enabled here, else a co-processor
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* exception might occur outside of a thread, which the exception handler
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* doesn't expect.
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*
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* Entry Conditions:
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* - Xtensa single-threaded run-time environment is in effect.
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* No thread is yet running.
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*
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* Exit conditions:
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* - None.
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*
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* Obeys ABI conventions per prototype:
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* void _xt_coproc_init(void)
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.global _xt_coproc_init
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.type _xt_coproc_init,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_init:
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ENTRY0
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/* Initialize thread co-processor ownerships to 0 (unowned). */
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movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
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addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */
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movi a4, 0 /* a4 = 0 (unowned) */
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1: s32i a4, a2, 0
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addi a2, a2, 4
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bltu a2, a3, 1b
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RET0
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#endif
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/****************************************************************************
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* Name: _xt_coproc_release
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*
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* Description:
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* Releases any and all co-processors owned by a given thread. The thread
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* is identified by it's co-processor state save area defined in
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* xtensa_context.h.
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*
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* Must be called before a thread's co-proc save area is deleted to avoid
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* memory corruption when the exception handler tries to save the state.
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* May be called when a thread terminates or completes but does not delete
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* the co-proc save area, to avoid the exception handler having to save
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* the thread's co-proc state before another thread can use it
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* (optimization).
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*
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* Entry Conditions:
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* - A2 = Pointer to base of co-processor state save area.
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*
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* Exit conditions:
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* - None.
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*
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* Obeys ABI conventions per prototype:
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* void _xt_coproc_release(void * coproc_sa_base)
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.global _xt_coproc_release
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.type _xt_coproc_release,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_release:
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ENTRY0 /* a2 = base of save area */
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getcoreid a5
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movi a3, XCHAL_CP_MAX << 2
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mull a5, a5, a3
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movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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add a3, a3, a5
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addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
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movi a5, 0 /* a5 = 0 (unowned) */
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rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */
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1: l32i a7, a3, 0 /* a7 = owner at a3 */
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bne a2, a7, 2f /* if (coproc_sa_base == owner) */
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s32i a5, a3, 0 /* owner = unowned */
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2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */
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bltu a3, a4, 1b /* Repeat until end of array */
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3: wsr a6, PS /* Restore interrupts */
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RET0
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#endif
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/****************************************************************************
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* Name: _xt_coproc_savecs
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*
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* Description:
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* If there is a current thread and it has a coprocessor state save area,
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* then save all callee-saved state into this area. This function is called
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* from the solicited context switch handler. It calls a system-specific
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* function to get the coprocessor save area base address.
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*
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* Entry conditions:
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* - The thread being switched out is still the current thread.
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* - CPENABLE state reflects which coprocessors are active.
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* - Registers have been saved/spilled already.
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*
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* Exit conditions:
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* - All necessary CP callee-saved state has been saved.
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* - Registers a2-a7, a13-a15 have been trashed.
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*
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* Must be called from assembly code only, using CALL0.
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.extern _xt_coproc_sa_offset /* external reference */
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.global _xt_coproc_savecs
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.type _xt_coproc_savecs,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_savecs:
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/* At entry, CPENABLE should be showing which CPs are enabled. */
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rsr a2, CPENABLE /* a2 = which CPs are enabled */
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beqz a2, .Ldone /* quick exit if none */
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mov a14, a0 /* save return address */
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call0 XT_RTOS_CP_STATE /* get address of CP save area */
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mov a0, a14 /* restore return address */
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beqz a15, .Ldone /* if none then nothing to do */
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s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
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movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
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l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
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#if XCHAL_CP0_SA_SIZE
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bbci.l a2, 0, 2f /* CP 0 not enabled */
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l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
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|
||||||
add a3, a14, a15 /* a3 = save area for CP 0 */
|
|
||||||
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP1_SA_SIZE
|
|
||||||
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
|
||||||
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
|
||||||
add a3, a14, a15 /* a3 = save area for CP 1 */
|
|
||||||
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP2_SA_SIZE
|
|
||||||
bbci.l a2, 2, 2f
|
|
||||||
l32i a14, a13, 8
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP3_SA_SIZE
|
|
||||||
bbci.l a2, 3, 2f
|
|
||||||
l32i a14, a13, 12
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP4_SA_SIZE
|
|
||||||
bbci.l a2, 4, 2f
|
|
||||||
l32i a14, a13, 16
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP5_SA_SIZE
|
|
||||||
bbci.l a2, 5, 2f
|
|
||||||
l32i a14, a13, 20
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP6_SA_SIZE
|
|
||||||
bbci.l a2, 6, 2f
|
|
||||||
l32i a14, a13, 24
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP7_SA_SIZE
|
|
||||||
bbci.l a2, 7, 2f
|
|
||||||
l32i a14, a13, 28
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.Ldone:
|
|
||||||
ret
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: _xt_coproc_restorecs
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Restore any callee-saved coprocessor state for the incoming thread.
|
|
||||||
* This function is called from coprocessor exception handling, when
|
|
||||||
* giving ownership to a thread that solicited a context switch earlier.
|
|
||||||
* It calls a system-specific function to get the coprocessor save area
|
|
||||||
* base address.
|
|
||||||
*
|
|
||||||
* Entry conditions:
|
|
||||||
* - The incoming thread is set as the current thread.
|
|
||||||
* - CPENABLE is set up correctly for all required coprocessors.
|
|
||||||
* - a2 = mask of coprocessors to be restored.
|
|
||||||
*
|
|
||||||
* Exit conditions:
|
|
||||||
* - All necessary CP callee-saved state has been restored.
|
|
||||||
* - CPENABLE - unchanged.
|
|
||||||
* - Registers a2-a7, a13-a15 have been trashed.
|
|
||||||
*
|
|
||||||
* Must be called from assembly code only, using CALL0.
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
|
||||||
.global _xt_coproc_restorecs
|
|
||||||
.type _xt_coproc_restorecs,@function
|
|
||||||
.align 4
|
|
||||||
.literal_position
|
|
||||||
.align 4
|
|
||||||
_xt_coproc_restorecs:
|
|
||||||
|
|
||||||
mov a14, a0 /* Save return address */
|
|
||||||
call0 XT_RTOS_CP_STATE /* Get address of CP save area */
|
|
||||||
mov a0, a14 /* Restore return address */
|
|
||||||
beqz a15, .Ldone2 /* If none then nothing to do */
|
|
||||||
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
|
|
||||||
xor a3, a3, a2 /* Clear the ones being restored */
|
|
||||||
s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */
|
|
||||||
movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */
|
|
||||||
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
|
||||||
|
|
||||||
#if XCHAL_CP0_SA_SIZE
|
|
||||||
bbci.l a2, 0, 2f /* CP 0 not enabled */
|
|
||||||
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
|
||||||
add a3, a14, a15 /* a3 = save area for CP 0 */
|
|
||||||
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP1_SA_SIZE
|
|
||||||
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
|
||||||
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
|
||||||
add a3, a14, a15 /* a3 = save area for CP 1 */
|
|
||||||
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP2_SA_SIZE
|
|
||||||
bbci.l a2, 2, 2f
|
|
||||||
l32i a14, a13, 8
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP3_SA_SIZE
|
|
||||||
bbci.l a2, 3, 2f
|
|
||||||
l32i a14, a13, 12
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP4_SA_SIZE
|
|
||||||
bbci.l a2, 4, 2f
|
|
||||||
l32i a14, a13, 16
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP5_SA_SIZE
|
|
||||||
bbci.l a2, 5, 2f
|
|
||||||
l32i a14, a13, 20
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP6_SA_SIZE
|
|
||||||
bbci.l a2, 6, 2f
|
|
||||||
l32i a14, a13, 24
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if XCHAL_CP7_SA_SIZE
|
|
||||||
bbci.l a2, 7, 2f
|
|
||||||
l32i a14, a13, 28
|
|
||||||
add a3, a14, a15
|
|
||||||
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
|
||||||
2:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.Ldone2:
|
|
||||||
ret
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|||||||
397
arch/xtensa/src/common/xtensa_coproc.S
Normal file
397
arch/xtensa/src/common/xtensa_coproc.S
Normal file
@ -0,0 +1,397 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
* arch/xtensa/src/common/xtensa_coproc.S
|
||||||
|
*
|
||||||
|
* Adapted from use in NuttX by:
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Derives from logic originally provided by Cadence Design Systems Inc.
|
||||||
|
*
|
||||||
|
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||||||
|
* a copy of this software and associated documentation files (the
|
||||||
|
* "Software"), to deal in the Software without restriction, including
|
||||||
|
* without limitation the rights to use, copy, modify, merge, publish,
|
||||||
|
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||||||
|
* the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included
|
||||||
|
* in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||||
|
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||||
|
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||||
|
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||||
|
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
|
||||||
|
*
|
||||||
|
* Low-level Call0 functions for handling generic context save and restore of
|
||||||
|
* registers not specifically addressed by the interrupt vectors and handlers.
|
||||||
|
* Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
|
||||||
|
* Except for the calls to RTOS functions, this code is generic to Xtensa.
|
||||||
|
*
|
||||||
|
* Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
|
||||||
|
* save regs (A12-A15), which is always the case if the handlers are coded in C.
|
||||||
|
* However A12, A13 are made available as scratch registers for interrupt dispatch
|
||||||
|
* code, so are presumed saved anyway, and are always restored even in Call0 ABI.
|
||||||
|
* Only A14, A15 are truly handled as callee-save regs.
|
||||||
|
*
|
||||||
|
* Because Xtensa is a configurable architecture, this port supports all user
|
||||||
|
* generated configurations (except restrictions stated in the release notes).
|
||||||
|
* This is accomplished by conditional compilation using macros and functions
|
||||||
|
* defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
|
||||||
|
* Only the processor state included in your configuration is saved and restored,
|
||||||
|
* including any processor state added by user configuration options or TIE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Included Files
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#include "xtensa_context.h"
|
||||||
|
|
||||||
|
#ifdef CONFIG_XTENSA_USE_OVLY
|
||||||
|
# include <xtensa/overlay_os_asm.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
.text
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: _xt_coproc_init
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Initializes global co-processor management data, setting all co-
|
||||||
|
* processors to "unowned". Leaves CPENABLE as it found it (does NOT clear
|
||||||
|
* it).
|
||||||
|
*
|
||||||
|
* Called during initialization of the RTOS, before any threads run.
|
||||||
|
*
|
||||||
|
* This may be called from normal Xtensa single-threaded application code
|
||||||
|
* which might use co-processors. The Xtensa run-time initialization enables
|
||||||
|
* all co-processors. They must remain enabled here, else a co-processor
|
||||||
|
* exception might occur outside of a thread, which the exception handler
|
||||||
|
* doesn't expect.
|
||||||
|
*
|
||||||
|
* Entry Conditions:
|
||||||
|
* - Xtensa single-threaded run-time environment is in effect.
|
||||||
|
* No thread is yet running.
|
||||||
|
*
|
||||||
|
* Exit conditions:
|
||||||
|
* - None.
|
||||||
|
*
|
||||||
|
* Obeys ABI conventions per prototype:
|
||||||
|
* void _xt_coproc_init(void)
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
||||||
|
.global _xt_coproc_init
|
||||||
|
.type _xt_coproc_init,@function
|
||||||
|
.align 4
|
||||||
|
.literal_position
|
||||||
|
.align 4
|
||||||
|
_xt_coproc_init:
|
||||||
|
ENTRY0
|
||||||
|
|
||||||
|
/* Initialize thread co-processor ownerships to 0 (unowned). */
|
||||||
|
|
||||||
|
movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
|
||||||
|
addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */
|
||||||
|
movi a4, 0 /* a4 = 0 (unowned) */
|
||||||
|
1: s32i a4, a2, 0
|
||||||
|
addi a2, a2, 4
|
||||||
|
bltu a2, a3, 1b
|
||||||
|
|
||||||
|
RET0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: _xt_coproc_release
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Releases any and all co-processors owned by a given thread. The thread
|
||||||
|
* is identified by it's co-processor state save area defined in
|
||||||
|
* xtensa_context.h.
|
||||||
|
*
|
||||||
|
* Must be called before a thread's co-proc save area is deleted to avoid
|
||||||
|
* memory corruption when the exception handler tries to save the state.
|
||||||
|
* May be called when a thread terminates or completes but does not delete
|
||||||
|
* the co-proc save area, to avoid the exception handler having to save
|
||||||
|
* the thread's co-proc state before another thread can use it
|
||||||
|
* (optimization).
|
||||||
|
*
|
||||||
|
* Entry Conditions:
|
||||||
|
* - A2 = Pointer to base of co-processor state save area.
|
||||||
|
*
|
||||||
|
* Exit conditions:
|
||||||
|
* - None.
|
||||||
|
*
|
||||||
|
* Obeys ABI conventions per prototype:
|
||||||
|
* void _xt_coproc_release(void * coproc_sa_base)
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
||||||
|
.global _xt_coproc_release
|
||||||
|
.type _xt_coproc_release,@function
|
||||||
|
.align 4
|
||||||
|
.literal_position
|
||||||
|
.align 4
|
||||||
|
_xt_coproc_release:
|
||||||
|
ENTRY0 /* a2 = base of save area */
|
||||||
|
|
||||||
|
getcoreid a5
|
||||||
|
movi a3, XCHAL_CP_MAX << 2
|
||||||
|
mull a5, a5, a3
|
||||||
|
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
|
||||||
|
add a3, a3, a5
|
||||||
|
|
||||||
|
addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
|
||||||
|
movi a5, 0 /* a5 = 0 (unowned) */
|
||||||
|
|
||||||
|
rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */
|
||||||
|
|
||||||
|
1: l32i a7, a3, 0 /* a7 = owner at a3 */
|
||||||
|
bne a2, a7, 2f /* if (coproc_sa_base == owner) */
|
||||||
|
s32i a5, a3, 0 /* owner = unowned */
|
||||||
|
2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */
|
||||||
|
bltu a3, a4, 1b /* Repeat until end of array */
|
||||||
|
|
||||||
|
3: wsr a6, PS /* Restore interrupts */
|
||||||
|
|
||||||
|
RET0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: _xt_coproc_savecs
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* If there is a current thread and it has a coprocessor state save area,
|
||||||
|
* then save all callee-saved state into this area. This function is called
|
||||||
|
* from the solicited context switch handler. It calls a system-specific
|
||||||
|
* function to get the coprocessor save area base address.
|
||||||
|
*
|
||||||
|
* Entry conditions:
|
||||||
|
* - The thread being switched out is still the current thread.
|
||||||
|
* - CPENABLE state reflects which coprocessors are active.
|
||||||
|
* - Registers have been saved/spilled already.
|
||||||
|
*
|
||||||
|
* Exit conditions:
|
||||||
|
* - All necessary CP callee-saved state has been saved.
|
||||||
|
* - Registers a2-a7, a13-a15 have been trashed.
|
||||||
|
*
|
||||||
|
* Must be called from assembly code only, using CALL0.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
||||||
|
.extern _xt_coproc_sa_offset /* external reference */
|
||||||
|
.global _xt_coproc_savecs
|
||||||
|
.type _xt_coproc_savecs,@function
|
||||||
|
.align 4
|
||||||
|
.literal_position
|
||||||
|
.align 4
|
||||||
|
_xt_coproc_savecs:
|
||||||
|
|
||||||
|
/* At entry, CPENABLE should be showing which CPs are enabled. */
|
||||||
|
|
||||||
|
rsr a2, CPENABLE /* a2 = which CPs are enabled */
|
||||||
|
beqz a2, .Ldone /* quick exit if none */
|
||||||
|
mov a14, a0 /* save return address */
|
||||||
|
call0 XT_RTOS_CP_STATE /* get address of CP save area */
|
||||||
|
mov a0, a14 /* restore return address */
|
||||||
|
beqz a15, .Ldone /* if none then nothing to do */
|
||||||
|
s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
|
||||||
|
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
|
||||||
|
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
||||||
|
|
||||||
|
#if XCHAL_CP0_SA_SIZE
|
||||||
|
bbci.l a2, 0, 2f /* CP 0 not enabled */
|
||||||
|
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
||||||
|
add a3, a14, a15 /* a3 = save area for CP 0 */
|
||||||
|
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP1_SA_SIZE
|
||||||
|
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
||||||
|
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
||||||
|
add a3, a14, a15 /* a3 = save area for CP 1 */
|
||||||
|
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP2_SA_SIZE
|
||||||
|
bbci.l a2, 2, 2f
|
||||||
|
l32i a14, a13, 8
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP3_SA_SIZE
|
||||||
|
bbci.l a2, 3, 2f
|
||||||
|
l32i a14, a13, 12
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP4_SA_SIZE
|
||||||
|
bbci.l a2, 4, 2f
|
||||||
|
l32i a14, a13, 16
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP5_SA_SIZE
|
||||||
|
bbci.l a2, 5, 2f
|
||||||
|
l32i a14, a13, 20
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP6_SA_SIZE
|
||||||
|
bbci.l a2, 6, 2f
|
||||||
|
l32i a14, a13, 24
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP7_SA_SIZE
|
||||||
|
bbci.l a2, 7, 2f
|
||||||
|
l32i a14, a13, 28
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.Ldone:
|
||||||
|
ret
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: _xt_coproc_restorecs
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Restore any callee-saved coprocessor state for the incoming thread.
|
||||||
|
* This function is called from coprocessor exception handling, when
|
||||||
|
* giving ownership to a thread that solicited a context switch earlier.
|
||||||
|
* It calls a system-specific function to get the coprocessor save area
|
||||||
|
* base address.
|
||||||
|
*
|
||||||
|
* Entry conditions:
|
||||||
|
* - The incoming thread is set as the current thread.
|
||||||
|
* - CPENABLE is set up correctly for all required coprocessors.
|
||||||
|
* - a2 = mask of coprocessors to be restored.
|
||||||
|
*
|
||||||
|
* Exit conditions:
|
||||||
|
* - All necessary CP callee-saved state has been restored.
|
||||||
|
* - CPENABLE - unchanged.
|
||||||
|
* - Registers a2-a7, a13-a15 have been trashed.
|
||||||
|
*
|
||||||
|
* Must be called from assembly code only, using CALL0.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
||||||
|
.global _xt_coproc_restorecs
|
||||||
|
.type _xt_coproc_restorecs,@function
|
||||||
|
.align 4
|
||||||
|
.literal_position
|
||||||
|
.align 4
|
||||||
|
_xt_coproc_restorecs:
|
||||||
|
|
||||||
|
mov a14, a0 /* Save return address */
|
||||||
|
call0 XT_RTOS_CP_STATE /* Get address of CP save area */
|
||||||
|
mov a0, a14 /* Restore return address */
|
||||||
|
beqz a15, .Ldone2 /* If none then nothing to do */
|
||||||
|
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
|
||||||
|
xor a3, a3, a2 /* Clear the ones being restored */
|
||||||
|
s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */
|
||||||
|
movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */
|
||||||
|
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
||||||
|
|
||||||
|
#if XCHAL_CP0_SA_SIZE
|
||||||
|
bbci.l a2, 0, 2f /* CP 0 not enabled */
|
||||||
|
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
||||||
|
add a3, a14, a15 /* a3 = save area for CP 0 */
|
||||||
|
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP1_SA_SIZE
|
||||||
|
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
||||||
|
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
||||||
|
add a3, a14, a15 /* a3 = save area for CP 1 */
|
||||||
|
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP2_SA_SIZE
|
||||||
|
bbci.l a2, 2, 2f
|
||||||
|
l32i a14, a13, 8
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP3_SA_SIZE
|
||||||
|
bbci.l a2, 3, 2f
|
||||||
|
l32i a14, a13, 12
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP4_SA_SIZE
|
||||||
|
bbci.l a2, 4, 2f
|
||||||
|
l32i a14, a13, 16
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP5_SA_SIZE
|
||||||
|
bbci.l a2, 5, 2f
|
||||||
|
l32i a14, a13, 20
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP6_SA_SIZE
|
||||||
|
bbci.l a2, 6, 2f
|
||||||
|
l32i a14, a13, 24
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_CP7_SA_SIZE
|
||||||
|
bbci.l a2, 7, 2f
|
||||||
|
l32i a14, a13, 28
|
||||||
|
add a3, a14, a15
|
||||||
|
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||||
|
2:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.Ldone2:
|
||||||
|
ret
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/xtensa/src/common/xtensa_vectors.S
|
* arch/xtensa/src/common/xtensa_intvectors.S
|
||||||
*
|
*
|
||||||
* Adapted from use in NuttX by:
|
* Adapted from use in NuttX by:
|
||||||
*
|
*
|
||||||
@ -40,7 +40,7 @@ HEAD_CSRC = esp32_start.c
|
|||||||
|
|
||||||
# Common XTENSA files (arch/xtensa/src/common)
|
# Common XTENSA files (arch/xtensa/src/common)
|
||||||
|
|
||||||
CMN_ASRCS = xtensa_irq.S xtensa_vectors.S
|
CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S
|
||||||
CMN_CSRCS = xtensa_assert.c xtensa_copystate.c
|
CMN_CSRCS = xtensa_assert.c xtensa_copystate.c
|
||||||
CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
|
CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
|
||||||
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
|
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user