Trivial, cosmetic changes from review of last PR.
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7329c81503
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@ -87,7 +87,6 @@
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#include "chip.h"
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#include "stm32_rcc.h"
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#include "stm32_gpio.h"
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/* #include "stm32_dma.h" */
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#include "stm32_spi.h"
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#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \
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@ -127,9 +126,9 @@
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# error "Unknown STM32 DMA"
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# endif
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#if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
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# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
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# error "Illegal value for CONFIG_SPI_DMAPRIO"
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#endif
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# endif
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/* DMA channel configuration */
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@ -768,7 +767,6 @@ static void spi_dumpregs(FAR struct stm32_spidev_s *priv)
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spi_getreg(priv, STM32_SPI_IER_OFFSET),
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spi_getreg(priv, STM32_SPI_SR_OFFSET),
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spi_getreg(priv, STM32_SPI_I2SCFGR_OFFSET));
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}
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#endif
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@ -1883,9 +1881,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
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* Master: CFG2.MSTR=1
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* 8-bit: CFG1.DSIZE=7
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* MSB tranmitted first: CFG2.LSBFRST=0
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* Replace NSS with SSI & SSI=1: CR1.SSI=1 CFG2.SSM=1 (prevents MODF error)
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* Two lines full duplex: CFG2.COMM=0
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*/
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@ -160,8 +160,7 @@
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#define STM32_PLL3Q_FREQUENCY
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#define STM32_PLL3R_FREQUENCY
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/*
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* SYSCLK = PLL1P = 400 MHz
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/* SYSCLK = PLL1P = 400 MHz
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* CPUCLK = SYSCLK / 1 = 400 MHz
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*/
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@ -79,7 +79,9 @@ void stm32_spidev_initialize(void)
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#ifdef CONFIG_STM32H7_SPI3
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# ifdef CONFIG_WL_NRF24L01
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/* Configure the SPI-based NRF24L01 chip select GPIO */
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spiinfo("Configure GPIO for SPI3/CS\n");
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stm32_configgpio(GPIO_NRF24L01_CS);
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stm32_gpiowrite(GPIO_NRF24L01_CS, true);
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# endif
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@ -757,10 +757,6 @@ static void nrf24l01_worker(FAR void *arg)
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nxsem_post(&dev->sem_tx);
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}
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else
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{
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/* wlerr("invalid length in rx: %d\n", (int)pktlen); */
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}
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}
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if (dev->state == ST_RX)
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@ -253,7 +253,7 @@ struct sockaddr_storage
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struct sockaddr
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{
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sa_family_t sa_family; /* Address family: See AF_* definitions */
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char sa_data[14]; /* 14-bytes of address data */
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char sa_data[14]; /* 14-bytes data (actually variable length) */
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};
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/* Used with the SO_LINGER socket option */
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