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Changed the pci bus for arm architecture

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Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
yangshuyong 2024-02-04 09:47:12 +08:00 committed by Xiang Xiao
parent cec3b5c0fb
commit 125884ae95
8 changed files with 5923 additions and 887 deletions
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12
drivers/pci/Kconfig
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@ -8,4 +8,14 @@ menuconfig PCI
default n
---help---
Enables support for the PCI bus.
Backend bust be provided by per-arch or per-board implementation.
Backend must be provided by per-arch or per-board implementation.
if PCI
config PCI_ASSIGN_ALL_BUSES
bool "Assign resource to all buses"
default !ARCH_X86 && !ARCH_X86_64
---help---
Assign resources to all buses. This is required for some
platforms that have multiple PCI buses.
endif

2
drivers/pci/Make.defs
View File

@ -20,7 +20,7 @@
ifeq ($(CONFIG_PCI),y)
CSRCS += pci.c
CSRCS += pci.c pci_ecam.c
# Include PCI device driver build support

1531
drivers/pci/pci.c
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File diff suppressed because it is too large Load Diff

323
drivers/pci/pci_ecam.c Normal file
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@ -0,0 +1,323 @@
/****************************************************************************
* drivers/pci/pci_ecam.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <errno.h>
#include <nuttx/kmalloc.h>
#include <nuttx/pci/pci.h>
#include <nuttx/pci/pci_ecam.h>
#include <nuttx/nuttx.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define readb(a) (*(FAR volatile uint8_t *)(a))
#define writeb(v,a) (*(FAR volatile uint8_t *)(a) = (v))
#define readw(a) (*(FAR volatile uint16_t *)(a))
#define writew(v,a) (*(FAR volatile uint16_t *)(a) = (v))
#define readl(a) (*(FAR volatile uint32_t *)(a))
#define writel(v,a) (*(FAR volatile uint32_t *)(a) = (v))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define IS_ALIGNED(x, a) (((x) & ((a) - 1)) == 0)
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int pci_ecam_read_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, FAR uint32_t *val);
static int pci_ecam_write_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, uint32_t val);
/****************************************************************************
* Private Types
****************************************************************************/
struct pci_ecam_s
{
struct pci_controller_s ctrl;
struct pci_resource_s cfg;
};
/****************************************************************************
* Private Data
****************************************************************************/
static const struct pci_ops_s g_pci_ecam_ops =
{
.read = pci_ecam_read_config,
.write = pci_ecam_write_config,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: pci_ecam_from_controller
*
* Description:
* To get the ecam type from ctrl type.
*
* Input Parameters:
* ctrl - The pci controller
*
* Returned Value:
* Return the struct pci_ecam_pcie s address
*
****************************************************************************/
static inline FAR struct pci_ecam_s *
pci_ecam_from_controller(FAR struct pci_controller_s *ctrl)
{
return container_of(ctrl, struct pci_ecam_s, ctrl);
}
/****************************************************************************
* Name: pci_ecam_conf_address
*
* Description:
* This function is used to get the specify reg address of a function
* configuration space.
*
* Input Parameters:
* bus - PCI bus type private data
* devfn - Specify a BDF
* where - Which ID in configuration space
*
****************************************************************************/
static FAR void *pci_ecam_conf_address(FAR const struct pci_bus_s *bus,
uint32_t devfn, int where)
{
FAR struct pci_ecam_s *ecam = pci_ecam_from_controller(bus->ctrl);
FAR void *addr;
addr = (FAR void *)ecam->cfg.start;
addr += bus->number << 20;
addr += PCI_SLOT(devfn) << 15;
addr += PCI_FUNC(devfn) << 12;
addr += where;
return addr;
}
/****************************************************************************
* Name: pci_ecam_addr_valid
*
* Description:
* To check the bus number whether or not valid.
*
* Input Parameters:
* bus - The bus private data
* devfn - Get a specify dev by devfn
*
* Returned Value:
* True if success, false if failed
*
****************************************************************************/
static bool pci_ecam_addr_valid(FAR const struct pci_bus_s *bus,
uint32_t devfn)
{
FAR struct pci_ecam_s *ecam = pci_ecam_from_controller(bus->ctrl);
int num_buses = DIV_ROUND_UP(pci_resource_size(&ecam->cfg), 1 << 20);
return bus->number < num_buses;
}
/****************************************************************************
* Name: pci_ecam_read_config
*
* Description:
* Read data from the speicfy register.
*
* Input Parameters:
* bus - The bus on this to read reg data
* devfn - BDF
* where - Which cfg space ID
* size - Data size
* val - Return value to this var
*
* Returned Value:
* Return the specify enum result of operation
*
****************************************************************************/
static int pci_ecam_read_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, FAR uint32_t *val)
{
FAR void *addr;
if (!pci_ecam_addr_valid(bus, devfn))
{
return -ENODEV;
}
addr = pci_ecam_conf_address(bus, devfn, where);
if (!IS_ALIGNED((uintptr_t)addr, size))
{
*val = 0;
return -EINVAL;
}
if (size == 4)
{
*val = readl(addr);
}
else if (size == 2)
{
*val = readw(addr);
}
else if (size == 1)
{
*val = readb(addr);
}
else
{
*val = 0;
return -EINVAL;
}
return OK;
}
/****************************************************************************
* Name: pci_ecam_write_config
*
* Description:
* Write data into speicfy register.
*
* Input Parameters:
* bus - The specify bus private data
* devfn - BDF
* where - Which ID in configuration space
* size - Data Size
* val - The value to be written
*
* Returned Value:
* Return the specify enum result of operation
*
****************************************************************************/
static int pci_ecam_write_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, uint32_t val)
{
FAR void *addr;
if (!pci_ecam_addr_valid(bus, devfn))
{
return -ENODEV;
}
addr = pci_ecam_conf_address(bus, devfn, where);
if (!IS_ALIGNED((uintptr_t)addr, size))
{
return -EINVAL;
}
if (size == 4)
{
writel(val, addr);
}
else if (size == 2)
{
writew(val, addr);
}
else if (size == 1)
{
writeb(val, addr);
}
else
{
return -EINVAL;
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pci_ecam_register
*
* Description:
* This function is used to register an ecam driver for pci.
*
* Input Parameters:
* cfg - Configuration space data
* io - I/O space data
* mem - No-prefetchable space data
* mem_pref - Prefetchable space data
*
* Returned Value:
* Return 0 if success, nageative if failed
*
****************************************************************************/
int pci_ecam_register(FAR const struct pci_resource_s *cfg,
FAR const struct pci_resource_s *io,
FAR const struct pci_resource_s *mem,
FAR const struct pci_resource_s *mem_pref)
{
FAR struct pci_ecam_s *ecam;
if (cfg == NULL || (io == NULL && mem == NULL && mem_pref == NULL))
{
return -EINVAL;
}
ecam = kmm_zalloc(sizeof(*ecam));
if (ecam == NULL)
{
return -ENOMEM;
}
memcpy(&ecam->cfg, cfg, sizeof(*cfg));
if (io != NULL)
{
memcpy(&ecam->ctrl.io, io, sizeof(*io));
}
if (mem != NULL)
{
memcpy(&ecam->ctrl.mem, mem, sizeof(*mem));
}
if (mem_pref != NULL)
{
memcpy(&ecam->ctrl.mem_pref, mem_pref, sizeof(*mem_pref));
}
ecam->ctrl.ops = &g_pci_ecam_ops;
return pci_register_controller(&ecam->ctrl);
}

723
include/nuttx/pci/pci.h
View File

@ -21,452 +21,595 @@
#ifndef __INCLUDE_NUTTX_PCI_PCI_H
#define __INCLUDE_NUTTX_PCI_PCI_H
#ifdef CONFIG_PCI
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/list.h>
#include <nuttx/pci/pci_ids.h>
#include <nuttx/pci/pci_regs.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PCI config common registers */
#define PCI_RESOURCE_IO 0x00000001
#define PCI_RESOURCE_MEM 0x00000002
#define PCI_RESOURCE_MEM_64 0x00000004
#define PCI_RESOURCE_PREFETCH 0x00000008 /* No side effects */
#define PCI_CONFIG_VENDOR 0x00
#define PCI_CONFIG_DEVICE 0x02
#define PCI_CONFIG_COMMAND 0x04
#define PCI_CONFIG_REV_ID 0x08
#define PCI_CONFIG_PROG_IF 0x09
#define PCI_CONFIG_SUBCLASS 0x0A
#define PCI_CONFIG_CLASS 0x0B
#define PCI_CONFIG_CACHE_LINE_SIZE 0x0C
#define PCI_CONFIG_LATENCY_TIMER 0x0D
#define PCI_CONFIG_HEADER_TYPE 0x0E
#define PCI_CONFIG_BIST 0x0F
/* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
* in a single byte as follows:
*
* 7:3 = slot
* 2:0 = function
*/
/* PCI config header types */
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn) ((devfn) & 0x07)
#define PCI_HEADER_NORMAL 0x00
#define PCI_HEADER_BRIDGE 0x01
#define PCI_HEADER_CARDBUS 0x02
#define PCI_HEADER_TYPE_MASK 0x3F
#define PCI_HEADER_MASK_MULTI 0x80
#define PCI_ANY_ID (~0)
/* PCI config registers type 0 (Normal devices) */
/* PCI_DEFINE_DEVICE_TABLE - macro used to describe a pci device table
* table: device table name
*
* This macro is used to create a struct pci_device_id_s array (a device
* table)in a generic manner.
*/
#define PCI_HEADER_NORM_BAR0 0x10
#define PCI_HEADER_NORM_BAR1 0x14
#define PCI_HEADER_NORM_BAR2 0x18
#define PCI_HEADER_NORM_BAR3 0x1C
#define PCI_HEADER_NORM_BAR4 0x20
#define PCI_HEADER_NORM_BAR5 0x24
#define PCI_HEADER_NORM_CB_CIS 0x28
#define PCI_HEADER_NORM_SUB_VID 0x2C
#define PCI_HEADER_NORM_SUB_ID 0x2E
#define PCI_HEADER_NORM_EXP_ROM 0x30
#define PCI_HEADER_NORM_CAP 0x34
#define PCI_HEADER_NORM_INT_LINE 0x3C
#define PCI_HEADER_NORM_INT_PIN 0x3D
#define PCI_HEADER_NORM_MIN_GRANT 0x3E
#define PCI_HEADER_NORM_MAX_LAT 0x3E
#define PCI_DEFINE_DEVICE_TABLE(table) \
static const struct pci_device_id_s table[]
/* PCI config registers type 1 (PCI-PCI bridge) */
/* PCI_DEVICE - macro used to describe a specific pci device
* vend: the 16 bit PCI Vendor ID
* dev: the 16 bit PCI Device ID
*
* This macro is used to create a struct pci_device_id_s that matches a
* specific device. The subvendor and subdevice fields will be set to
* PCI_ANY_ID.
*/
#define PCI_CONFIG_SEC_BUS 0x19
#define PCI_DEVICE(vend, dev) \
.vendor = (vend), .device = (dev), \
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
/* PCI config registers type 2 (CardBus) */
/* PCI_DEVICE_SUB - macro used to describe a specific PCI device with
* subsystem
*
* vend: the 16 bit PCI Vendor ID
* dev: the 16 bit PCI Device ID
* subvend: the 16 bit PCI Subvendor ID
* subdev: the 16 bit PCI Subdevice ID
*
* This macro is used to create a struct pci_device_id_s that matches a
* specific device with subsystem information.
*/
/* PCI Base Class Codes */
#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
.vendor = (vend), .device = (dev), \
.subvendor = (subvend), .subdevice = (subdev)
#define PCI_CLASS_BASE_UNCLASSIFIED 0x00
#define PCI_CLASS_BASE_MASS_STORAGE_CTRL 0x01
#define PCI_CLASS_BASE_NETWORK_CTRL 0x02
#define PCI_CLASS_BASE_DISPLAY_CTRL 0x03
#define PCI_CLASS_BASE_MULTIMEDIA_CTRL 0x04
#define PCI_CLASS_BASE_MEM_CTRL 0x05
#define PCI_CLASS_BASE_BRG_DEV 0x06
#define PCI_CLASS_BASE_SMPL_COM_CTRL 0x07
#define PCI_CLASS_BASE_BSP 0x08
#define PCI_CLASS_BASE_INPUT_DEV_CTRL 0x09
#define PCI_CLASS_BASE_DOCK_STN 0x0A
#define PCI_CLASS_BASE_PROCESSOR 0x0B
#define PCI_CLASS_BASE_SBC 0x0C
#define PCI_CLASS_BASE_WIRELESS_CTRL 0x0D
#define PCI_CLASS_BASE_INTL_CTRL 0x0E
#define PCI_CLASS_BASE_SAT_COM_CTRL 0x0F
#define PCI_CLASS_BASE_ENCRYPT_CTRL 0x10
#define PCI_CLASS_BASE_SPC 0x11
#define PCI_CLASS_BASE_PROC_ACCEL 0x12
#define PCI_CLASS_BASE_NON_ES_INST 0x13
/* PCI_DEVICE_CLASS - macro used to describe a specific pci device class
* dev_class: the class, subclass, prog-if triple for this device
* dev_class_mask: the class mask for this device
*
* This macro is used to create a struct pci_device_id_s that matches a
* specific PCI class. The vendor, device, subvendor, and subdevice
* fields will be set to PCI_ANY_ID.
*/
/* Reserved 0x14-0x3F */
#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
.class = (dev_class), .class_mask = (dev_class_mask), \
.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
#define PCI_CLASS_BASE_CO_PROC 0x40
/* PCI_VDEVICE - macro used to describe a specific pci device in short form
* vend: the vendor name
* dev: the 16 bit PCI Device ID
*
* This macro is used to create a struct pci_device_id_s that matches a
* specific PCI device. The subvendor, and subdevice fields will be set
* to PCI_ANY_ID. The macro allows the next field to follow as the device
* private data.
*/
/* Reserved 0x41-0xFE */
#define PCI_VDEVICE(vend, dev) \
.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
#define PCI_CLASS_BASE_UNASSIGNED 0xFF
/* These helpers provide future and backwards compatibility
* for accessing popular PCI BAR info
*/
/* PCI Sub Class Codes (most missing) */
#define pci_resource_size(res) \
(((res)->start == 0 && (res)->end == 0) ? 0 : \
((res)->end - (res)->start + 1))
/* Bridge Class */
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
#define pci_resource_len(dev, bar) pci_resource_size(&((dev)->resource[(bar)]))
#define PCI_CLASS_SUB_HOST_BRG 0x00
#define PCI_CLASS_SUB_ISA_BRG 0x01
#define PCI_CLASS_SUB_EISA_BRG 0x02
#define PCI_CLASS_SUB_MCA_BRG 0x03
#define PCI_CLASS_SUB_PCI_BRG 0x04
#define PCI_CLASS_SUB_PCMCIA_BRG 0x05
#define PCI_CLASS_SUB_NUBUS_BRG 0x06
#define PCI_CLASS_SUB_CARDBUS_BRG 0x07
#define PCI_CLASS_SUB_RACEWAY_BRG 0x08
#define PCI_CLASS_SUB_PCI_TRNSP_BRG 0x09
#define PCI_CLASS_SUB_INFINI_BRG 0x0A
#define PCI_CLASS_SUB_NUBUS_BRG 0x80
#define pci_read_config_byte(dev, where, val) \
pci_bus_read_config_byte((dev)->bus, (dev)->devfn, where, val)
#define PCI_ID_ANY 0xffff
#define pci_read_config_word(dev, where, val) \
pci_bus_read_config_word((dev)->bus, (dev)->devfn, where, val)
/* PCI Command Register Bitmasks */
#define pci_read_config_dword(dev, where, val) \
pci_bus_read_config_dword((dev)->bus, (dev)->devfn, where, val)
#define PCI_CMD_IO_SPACE 0x0001
#define PCI_CMD_MEM_SPACE 0x0002
#define PCI_CMD_BUS_MSTR 0x0004
#define PCI_CMD_SPECIAL_CYC 0x0008
#define PCI_CMD_MEM_INV 0x0030
#define PCI_CMD_VGA_PLT 0x0040
#define PCI_CMD_PAR_ERR 0x0080
#define PCI_CMD_SERR 0x0100
#define PCI_CMD_FST_B2B 0x0200
#define PCI_CMD_INT 0x0400
#define pci_write_config_byte(dev, where, val) \
pci_bus_write_config_byte((dev)->bus, (dev)->devfn, where, val)
/* PCI BAR Bitmasks */
#define pci_write_config_word(dev, where, val) \
pci_bus_write_config_word((dev)->bus, (dev)->devfn, where, val)
#define PCI_BAR_LAYOUT_MASK 0x00000001
#define PCI_BAR_TYPE_MASK 0x00000006
#define PCI_BAR_MEM_PF_MASK 0x00000008
#define PCI_BAR_MEM_BASE_MASK 0xfffffff0
#define PCI_BAR_IO_BASE_MASK 0xfffffffc
/* PCI BAR OFFSETS */
#define PCI_BAR_LAYOUT_OFFSET 0
#define PCI_BAR_TYPE_OFFSET 1
#define PCI_BAR_MEM_PF_OFFSET 3
#define PCI_BAR_MEM_BASE_OFFSET 4
#define PCI_BAR_IO_BASE_OFFSET 2
/* PCI BAR */
#define PCI_BAR_CNT 6
#define PCI_BAR_INVALID 0
#define PCI_BAR_LAYOUT_MEM 0
#define PCI_BAR_LAYOUT_IO 1
#define PCI_BAR_TYPE_32 0x00
#define PCI_BAR_TYPE_16 0x01 /* This mode is not used */
#define PCI_BAR_TYPE_64 0x02
/* PCI CAP */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOT 0x04 /* Slot ID */
#define PCI_CAP_ID_MSI 0x05 /* MSI */
#define PCI_CAP_ID_CHP 0x06 /* CompactPCI Hot-Swap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
#define PCI_CAP_ID_VNDR 0x09 /* Vendor */
#define PCI_CAP_ID_DBG 0x0A /* Debug */
#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
#define PCI_CAP_ID_HOT 0x0C /* Hot-Plug Controller */
#define PCI_CAP_ID_BRG_VID 0x0D /* Bridge Vendor/Device ID */
#define PCI_CAP_ID_AGP_BRG 0x0E /* AGP PCI-PCI Bridge */
#define PCI_CAP_ID_SEC_DEV 0x0F /* Secure Device */
#define PCI_CAP_ID_PCIE 0x10 /* PCIe */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_ID_SATA 0x12 /* SATA */
#define PCI_CAP_ID_ADVF 0x13 /* Advanced Features */
#define PCI_CAP_ID_END PCI_CAP_ID_ADVF
/* Resource types used by PCI devices */
#define PCI_SYS_RES_IOPORT 0x00
#define PCI_SYS_RES_MEM 0x01
#define pci_write_config_dword(dev, where, val) \
pci_bus_write_config_dword((dev)->bus, (dev)->devfn, where, val)
/****************************************************************************
* Public Types
****************************************************************************/
/* The PCI driver interface */
struct pci_bus_s;
struct pci_dev_type_s;
struct pci_dev_s;
/* Bus related operations */
struct pci_bus_ops_s
struct pci_resource_s
{
/* Write 8, 16, 32, 64 bits data to PCI-E configuration space of device
* specified by dev.
*/
CODE void (*pci_cfg_write)(FAR struct pci_dev_s *dev, int reg,
uint32_t val, int width);
/* Read 8, 16, 32, 64 bits data to PCI-E configuration space of device
* specified by dev.
*/
CODE uint32_t (*pci_cfg_read)(FAR struct pci_dev_s *dev, int reg,
int width);
/* Map address in a 32 bits bar in the memory address space */
CODE int (*pci_map_bar)(uint64_t addr, uint64_t len);
/* Read from IO port */
CODE uint32_t (*pci_io_read)(FAR const volatile void *addr, int width);
/* Write to IO port */
CODE void (*pci_io_write)(FAR const volatile void *addr, uint32_t val,
int width);
uintptr_t start;
uintptr_t end;
unsigned int flags;
};
/* PCI bus private data. */
/* For PCI devices, the region numbers are assigned this way: */
enum
{
/* #0-5: Standard PCI resources */
PCI_STD_RESOURCES,
PCI_STD_RESOURCE_END = 5,
/* #6: Expansion ROM resource */
PCI_ROM_RESOURCE,
/* Total resources associated with a PCI device */
PCI_NUM_RESOURCES,
};
/* The pci_device_s structure is used to describe PCI devices. */
struct pci_device_s
{
struct list_node node;
struct list_node bus_list; /* Node in per-bus list */
FAR struct pci_bus_s *bus; /* Bus this device is on */
FAR struct pci_bus_s *subordinate; /* Bus this device bridges to */
uint32_t devfn; /* Encoded device & function index */
uint16_t vendor; /* Vendor id */
uint16_t device; /* Device id */
uint16_t subsystem_vendor;
uint16_t subsystem_device;
uint32_t class; /* 3 bytes: (base,sub,prog-if) */
uint8_t revision; /* PCI revision, low byte of class word */
uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */
/* I/O and memory regions + expansion ROMs */
struct pci_resource_s resource[PCI_NUM_RESOURCES];
FAR struct pci_driver_s *drv;
FAR void *priv; /* Used by pci driver */
};
struct pci_bus_s
{
FAR const struct pci_bus_ops_s *ops; /* operations */
FAR struct pci_controller_s *ctrl; /* Associated host controller */
FAR struct pci_bus_s *parent_bus; /* Parent bus */
struct list_node node; /* Node in list of buses */
struct list_node children; /* List of child buses */
struct list_node devices; /* List of devices on this bus */
uint8_t number; /* Bus number */
};
/* PCI device type, defines by vendor ID and device ID */
/* Low-level architecture-dependent routines */
struct pci_dev_type_s
struct pci_ops_s
{
uint16_t vendor; /* Device vendor ID */
uint16_t device; /* Device ID */
uint32_t class_rev; /* Device reversion */
const char *name; /* Human readable name */
CODE int (*read)(FAR struct pci_bus_s *bus, unsigned int devfn, int where,
int size, FAR uint32_t *val);
CODE int (*write)(FAR struct pci_bus_s *bus, unsigned int devfn, int where,
int size, uint32_t val);
/* Call back function when a device is probed */
/* Return memory address for pci resource */
CODE int (*probe)(FAR struct pci_bus_s *bus,
FAR const struct pci_dev_type_s *type, uint16_t bdf);
CODE uintptr_t (*map)(FAR struct pci_bus_s *bus, uintptr_t start,
uintptr_t end);
};
/* PCI device private data. */
/* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_dev_s
struct pci_controller_s
{
FAR struct pci_bus_s *bus;
FAR const struct pci_dev_type_s *type;
uint32_t bdf;
struct pci_resource_s io;
struct pci_resource_s mem;
struct pci_resource_s mem_pref;
FAR const struct pci_ops_s *ops;
FAR struct pci_bus_s *bus;
uint8_t busno;
};
struct pci_device_id_s
{
uint16_t vendor; /* Vendor id */
uint16_t device; /* Device id */
uint32_t subvendor; /* Sub vendor id */
uint32_t subdevice; /* Sub device id */
uint32_t class; /* (Class, subclass, prog-if) triplet */
uint32_t class_mask;
};
struct pci_driver_s
{
FAR const struct pci_device_id_s *id_table;
/* New device inserted */
CODE int (*probe)(FAR struct pci_device_s *dev);
/* Device removed (NULL if not a hot-plug capable driver) */
CODE void (*remove)(FAR struct pci_device_s *dev);
struct list_node node;
};
/****************************************************************************
* Public Functions Prototypes
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: pci_initialize
* Name: pci_set_master
*
* Description:
* Initialize the PCI bus and enumerate the devices with give devices
* type array
* Enables bus-mastering for device
*
* Input Parameters:
* bus - An PCI bus
* types - A array of PCI device types
* dev - The PCI device to enable
*
****************************************************************************/
void pci_set_master(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_clear_master
*
* Description:
* Disables bus-mastering for device
*
* Input Parameters:
* dev - The PCI device to disable
*
****************************************************************************/
void pci_clear_master(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_enable_device
*
* Description:
* Initialize device before it's used by a driver by setting command
* register.
*
* Input Parameters:
* dev - PCI device to be initialized
*pci_bus_ops_s
* Returned Value:
* Zero if success, otherwise nagative
*
****************************************************************************/
int pci_enable_device(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_disable_device
*
* Description:
* Disable pci device before it's unused by a driver by setting command
* register.
*
* Input Parameters:
* dev - PCI device to be Disable
*
* Returned Value:
* OK if the driver was successfully register; A negated errno value is
* returned on any failure.
* Zero if success, otherwise nagative
*
****************************************************************************/
int pci_initialize(FAR struct pci_bus_s *bus);
int pci_disable_device(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_enable_io
* Name: pci_select_bars
*
* Description:
* Enable MMIO or IOPORT
* Make BAR mask from the type of resource
* This helper routine makes bar mask from the type of resource.
*
* Input Parameters:
* dev - device
* space - which resource is being enabled
* PCI_SYS_RES_IOPORT for io port address decoding or
* PCI_RES_MEM for memory
*
* Return value:
* -EINVAL: error
* OK: OK
* dev - The PCI device for which BAR mask is made
* flags - Resource type mask to be selected
*
****************************************************************************/
int pci_enable_io(FAR struct pci_dev_s *dev, int res);
int pci_select_bars(FAR struct pci_device_s *dev, unsigned int flags);
/****************************************************************************
* Name: pci_disable_io
* Name: pci_map_bar
*
* Description:
* Enable MMIO or IOPORT
* Create a virtual mapping for a PCI BAR.
*
* Using this function you will get an address to your device BAR.
* These functions hide the details if this is a MMIO or PIO address
* space and will just do what you expect from them in the correct way.
*
* Input Parameters:
* dev - device
* space - which resource is being disabled
* PCI_SYS_RES_IOPORT for io port address decoding or
* PCI_SYS_RES_MEM for memory
* dev - PCI device that owns the BAR
* bar - BAR number
*
* Return value:
* -EINVAL: error
* OK: OK
* Returned Value:
* IO address or zero if failed
*
****************************************************************************/
int pci_disable_io(FAR struct pci_dev_s *dev, int res);
FAR void *pci_map_bar(FAR struct pci_device_s *dev, int bar);
/****************************************************************************
* Name: pci_enable_bus_master
* Name: pci_find_capability
*
* Description:
* Enable bus mastering for device so it can perform PCI accesses
* Query for devices' capabilities
*
* Tell if a device supports a given PCI capability.
*
* Input Parameters:
* dev - device
* dev - PCI device to query
* cap - Capability code
*
* Return value:
* -EINVAL: error
* OK: OK
* Returned Value:
* Returns the address of the requested capability structure within the
* device's PCI configuration space or 0 in case the device does not
* support it.
*
****************************************************************************/
int pci_enable_bus_master(FAR struct pci_dev_s *dev);
uint8_t pci_find_capability(FAR struct pci_device_s *dev, int cap);
/****************************************************************************
* Name: pci_disable_bus_master
* Name: pci_find_next_capability
*
* Description:
* Disable bus mastering for device
* To find the next capability.
*
* Input Parameters:
* dev - device
* dev - The PCI device to find capbilities
* pos - List node
* cap - Value of capabilities
*
* Return value:
* -EINVAL: error
* OK: OK
* Returned Value:
* Return the capability data
*
****************************************************************************/
int pci_disable_bus_master(FAR struct pci_dev_s *dev);
uint8_t pci_find_next_capability(FAR struct pci_device_s *dev, uint8_t pos,
int cap);
/****************************************************************************
* Name: pci_bar_valid
* Name: pci_register_driver
*
* Description:
* Determine in if the address in the BAR is valid
* To register a PCI driver
*
* Input Parameters:
* dev - device
* bar_id - bar number
* drv - PCI driver
*
* Return value:
* -EINVAL: error
* OK: OK
* Returned Value:
* Failed if return a negative value, otherwise success
*
****************************************************************************/
int pci_bar_valid(FAR struct pci_dev_s *dev, uint8_t bar_id);
int pci_register_driver(FAR struct pci_driver_s *drv);
/****************************************************************************
* Name: pci_bar_is_64
* Name: pci_unregister_driver
*
* Description:
* Determine in if the bar address is 64 bit. If it is the address includes
* the address in the next bar location.
* To unregister a PCI driver
*
* Input Parameters:
* dev - device
* bar_id - bar number
* drv - PCI driver
*
* Return value:
* true: 64bit address
* Returned Value:
* Failed if return a negative value, otherwise success
*
****************************************************************************/
bool pci_bar_is_64(FAR struct pci_dev_s *dev, uint8_t bar_id);
int pci_unregister_driver(FAR struct pci_driver_s *drv);
/****************************************************************************
* Name: pci_bar_size
* Name: pci_register_device
*
* Description:
* Determine the size of the address space required by the BAR
* To register a PCI device
*
* Input Parameters:
* dev - device
* bar_id - bar number
* dev - PCI device
*
* Return value:
* Size of address space
* Returned Value:
* Failed if return a negative value, otherwise success
*
****************************************************************************/
uint64_t pci_bar_size(FAR struct pci_dev_s *dev, uint8_t bar_id);
int pci_register_device(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_bar_addr
* Name: pci_unregister_device
*
* Description:
* Determine the size of the address space required by the BAR
* To unregister a PCI device
*
* Input Parameters:
* dev - device
* bar_id - bar number
* dev - PCI device
*
* Return value:
* full bar address
* Returned Value:
* Failed if return a negative value, otherwise success
*
****************************************************************************/
uint64_t pci_bar_addr(FAR struct pci_dev_s *dev, uint8_t bar_id);
int pci_unregister_device(FAR struct pci_device_s *dev);
/****************************************************************************
* Name: pci_dev_dump
* Name: pci_register_controller
*
* Description:
* Dump the configuration information for the device
* Start pci bridge enumeration process, and register pci device.
*
* Input Parameters:
* dev - device
* ctrl - PCI ctrl to register
*
****************************************************************************/
void pci_dev_dump(FAR struct pci_dev_s *dev);
int pci_register_controller(FAR struct pci_controller_s *ctrl);
/****************************************************************************
* Name: pci_bus_read_config_byte
*
* Description:
* Read data from specify position with byte size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_read_config_byte(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, FAR uint8_t *val);
/****************************************************************************
* Name: pci_bus_read_config_word
*
* Description:
* Read data from specify position with word size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_read_config_word(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, FAR uint16_t *val);
/****************************************************************************
* Name: pci_bus_read_config_dword
*
* Description:
* Read data from specify position with dword size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_read_config_dword(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, FAR uint32_t *val);
/****************************************************************************
* Name: pci_bus_write_config_byte
*
* Description:
* Write data to specify reg with byte size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_write_config_byte(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, uint8_t val);
/****************************************************************************
* Name: pci_bus_write_config_word
*
* Description:
* Write data to specify reg with word size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_write_config_word(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, uint16_t val);
/****************************************************************************
* Name: pci_bus_write_config_dword
*
* Description:
* Write data to specify reg with dword size
*
* Input Parameters:
* bus - PCI bus
* devfn - BDF
* where - Pos ID
* val - Value
*
* Return value
* Return 0 if success, otherwise Error values
*
****************************************************************************/
int pci_bus_write_config_dword(FAR struct pci_bus_s *bus, unsigned int devfn,
int where, uint32_t val);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif
#endif /* __INCLUDE_NUTTX_PCI_PCI_H */

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/****************************************************************************
* include/nuttx/pci/pci_ecam.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __INCLUDE_NUTTX_PCI_PCI_ECAM_H
#define __INCLUDE_NUTTX_PCI_PCI_ECAM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/pci/pci.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: pci_ecam_register
*
* Description:
* This function is used to register an ecam driver for pci.
*
* Input Parameters:
* cfg - Configuration space data
* io - I/O space data
* mem - No-prefetchable space data
* mem_pref - Prefetchable space data
*
* Returned Value:
* Return 0 if success, nageative if failed
*
****************************************************************************/
int pci_ecam_register(FAR const struct pci_resource_s *cfg,
FAR const struct pci_resource_s *io,
FAR const struct pci_resource_s *mem,
FAR const struct pci_resource_s *mem_pref);
#endif /* __INCLUDE_NUTTX_PCI_PCI_ECAM_H */

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