From 126bec4e5511a5e75b19300b5cc6bcb7c5b07844 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 7 Jan 2014 08:38:00 -0600 Subject: [PATCH] Add more nops after enabling MMU for Cortex-A8 --- ChangeLog | 3 +++ arch/arm/src/armv7-a/arm_head.S | 11 +++-------- arch/arm/src/armv7-a/arm_pghead.S | 13 ++++--------- 3 files changed, 10 insertions(+), 17 deletions(-) diff --git a/ChangeLog b/ChangeLog index 32e9073fde..cbf96864e2 100644 --- a/ChangeLog +++ b/ChangeLog @@ -6378,4 +6378,7 @@ problems for assembly language. How to prevent the integer over- flow warnings? (2014-1-6). * arch/arm/src/a1x/a1x_serial.c: Handle BUSY interrupt (2014-1-6). + * arch/arm/src/armv7-a/arm_head.S and arm_pghead.S: Add more nop's + after enabling the MMU. The cortex-a8 seems to need these + (2014-1-7). diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index b5bab00220..bce82d50b5 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -505,14 +505,9 @@ __start: /* Then write the configured control register */ mcr CP15_SCTLR(r0) /* Write control reg */ - - /* Read the Main ID register. This will be available in R1 after - * MMU trampoline (not currently used) - */ - - mrc CP15_MIDR(r1) /* Read main id reg */ - mov r1, r1 /* Null-avoiding nop */ - mov r1, r1 /* Null-avoiding nop */ + .rept 12 /* Cortex A8 wants lots of NOPs here */ + nop + .endr /* And "jump" to .Lvstart in the newly mapped virtual address space */ diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index a11570515c..36497e7552 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-a/arm_pghead.S * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -491,14 +491,9 @@ __start: /* Then write the configured control register */ mcr CP15_SCTLR(r0) /* Write control reg */ - - /* Read the Main ID register. This will be available in R1 after - * MMU trampoline (not currently used) - */ - - mrc CP15_MIDR(r1) /* Read main id reg */ - mov r1, r1 /* Null-avoiding nop */ - mov r1, r1 /* Null-avoiding nop */ + .rept 12 /* Cortex A8 wants lots of NOPs here */ + nop + .endr /* And "jump" to .Lvstart in the newly mapped virtual address space */