stm32f777zit6-meadow: Add audio support (CS4344)
This commit is contained in:
Alan Carvalho de Assis
Xiang Xiao
parent
d9148add03
commit
12849b66e6
113
boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig
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113
boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig
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@ -0,0 +1,113 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="stm32f777zit6-meadow"
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CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y
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CONFIG_ARCH_CHIP="stm32f7"
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CONFIG_ARCH_CHIP_STM32F777ZI=y
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CONFIG_ARCH_CHIP_STM32F7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_AUDIO=y
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CONFIG_AUDIO_CS4344=y
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CONFIG_AUDIO_EXCLUDE_TONE=y
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CONFIG_AUDIO_EXCLUDE_VOLUME=y
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CONFIG_AUDIO_I2S=y
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CONFIG_BCH=y
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CONFIG_BOARDCTL_ROMDISK=y
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CONFIG_BOARDCTL_USBDEVCTRL=y
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CONFIG_BOARD_LATE_INITIALIZE=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BUILTIN=y
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CONFIG_CDCACM=y
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CONFIG_CDCACM_CONSOLE=y
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CONFIG_CDCACM_PRODUCTID=0x0001
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CONFIG_CDCACM_PRODUCTSTR="Wilderness Labs"
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CONFIG_CDCACM_VENDORID=0x2E6A
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CONFIG_CDCACM_VENDORSTR="Meadow F7 Micro"
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CONFIG_CRYPTO=y
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CONFIG_CRYPTO_RANDOM_POOL=y
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CONFIG_DEBUG_AUDIO=y
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CONFIG_DEBUG_AUDIO_ERROR=y
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CONFIG_DEBUG_AUDIO_INFO=y
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CONFIG_DEBUG_AUDIO_WARN=y
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CONFIG_DEBUG_DMA=y
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CONFIG_DEBUG_DMA_ERROR=y
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CONFIG_DEBUG_DMA_INFO=y
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CONFIG_DEBUG_DMA_WARN=y
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CONFIG_DEBUG_FEATURES=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_I2S=y
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CONFIG_DEBUG_I2S_ERROR=y
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CONFIG_DEBUG_I2S_INFO=y
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CONFIG_DEBUG_I2S_WARN=y
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CONFIG_DEBUG_SCHED=y
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CONFIG_DEBUG_SCHED_ERROR=y
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CONFIG_DEBUG_SCHED_WARN=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEV_URANDOM=y
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CONFIG_DEV_URANDOM_RANDOM_POOL=y
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CONFIG_DRIVERS_AUDIO=y
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CONFIG_FS_PROCFS=y
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CONFIG_FS_TMPFS=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_I2S=y
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBC_MEMFD_ERROR=y
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CONFIG_MM_REGIONS=3
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CONFIG_MTD=y
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CONFIG_MTD_BYTE_WRITE=y
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CONFIG_MTD_PARTITION=y
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CONFIG_MTD_SECT512=y
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CONFIG_MTD_W25QXXXJV=y
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFCONFIG=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_DISABLE_PS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAMLOG=y
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CONFIG_RAMLOG_SYSLOG=y
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SPI=y
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CONFIG_START_DAY=14
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CONFIG_STM32F7_DMA1=y
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CONFIG_STM32F7_I2S2=y
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CONFIG_STM32F7_I2S2_MCK=y
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CONFIG_STM32F7_I2S2_TX=y
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CONFIG_STM32F7_OTGFS=y
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CONFIG_STM32F7_QSPI_POLLING=y
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CONFIG_STM32F7_QUADSPI=y
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CONFIG_STM32F7_USART1=y
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CONFIG_SYSLOG_DEFAULT=y
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CONFIG_SYSLOG_DEVPATH="/dev/ttyS1"
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CONFIG_SYSLOG_MAX_CHANNELS=2
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CONFIG_SYSTEM_FLASH_ERASEALL=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_NXPLAYER=y
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CONFIG_SYSTEM_ZMODEM=y
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CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024
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CONFIG_SYSTEM_ZMODEM_RCVBUFSIZE=1024
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CONFIG_SYSTEM_ZMODEM_SNDBUFSIZE=1024
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CONFIG_TASK_NAME_SIZE=64
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CONFIG_USBDEV=y
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CONFIG_W25QXXXJV_QSPI_FREQUENCY=64000000
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@ -152,6 +152,13 @@
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* SAIx input frequency = 25 / M * N / Q / P
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* 25000000 / 25 * 384 / 2 / 8
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*/
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#define STM32F7_SAI1_FREQUENCY (49142857)
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#define STM32F7_SAI2_FREQUENCY (49142857)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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@ -163,12 +170,13 @@
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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/* Configure factors for PLLI2S clock */
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#define CONFIG_STM32F7_PLLI2S 1
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(4)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(4)
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/* Configure Dedicated Clock Configuration Register 2 */
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@ -377,6 +385,10 @@
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/* DMA Channel/Stream Selections ********************************************/
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#define DMACHAN_SAI2_A DMAMAP_SAI2_A
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#define DMACHAN_SAI2_B DMAMAP_SAI2_B
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#define DMACHAN_SAI1_B DMAMAP_SAI1_B
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/* SDMMC */
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/* Stream selections are arbitrary for now but might become important in the
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@ -470,6 +482,25 @@
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#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz)
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#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz)
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/* Dumb definition to SPI2, just because it is needed by i2s driver */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_5
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3
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#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2
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#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2
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/* I2S2 - CS4344 configuration uses I2S2 */
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#define GPIO_I2S2_SD (GPIO_I2S2_SD_1) /* PB15 */
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#define GPIO_I2S2_CK (GPIO_I2S2_CK_3) /* PB13 */
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#define GPIO_I2S2_WS (GPIO_I2S2_WS_1) /* PB12 */
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#define GPIO_I2S2_MCK (GPIO_I2S2_MCK_0) /* PC6 */
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#define DMACHAN_I2S2_RX DMAMAP_SPI2_RX_2
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#define DMACHAN_I2S2_TX DMAMAP_SPI2_TX_2
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/* QSPI Mapping */
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#define GPIO_QSPI_CS (GPIO_QUADSPI_BK1_NCS_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
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@ -32,6 +32,15 @@
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#include <nuttx/fs/fs.h>
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#include <nuttx/i2c/i2c_master.h>
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#include <nuttx/board.h>
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#ifdef CONFIG_AUDIO_CS4344
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# include "stm32_cs4344.h"
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#endif
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#include "chip.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "stm32f777zit6-meadow.h"
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@ -139,6 +148,16 @@ int stm32_bringup(void)
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}
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#endif
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#ifdef CONFIG_AUDIO_CS4344
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/* Configure CS4344 audio as /dev/pcm0 on I2S2 */
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ret = board_cs4344_initialize(1, 2);
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if (ret != OK)
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{
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syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret);
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}
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#endif
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#ifdef CONFIG_BOARD_MEADOW_F7_CORE_COMPUTE
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/* Initialize all devices in the F7 Core Compute */
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