armv7-a: Fix comments on Cortex-A SGI
Summary: - I noticed that Cortex-A SGI can be masked - We thought the SGI is not maskable - Although I can not remember how I tested it before - It actually works as expected now - Also, fixed the number of remaining bugs in TODO Impact: - No impact Testing: - Tested with sabre-6quad:smp (QEMU and dev board) - Add the following code in up_idle() before calling asm("WFI"); + if (0 != up_cpu_index()) + { + up_irq_save(); + } - Run the hello app, you can see "Hello, World!!" - But nsh will freeze soon because arm_pause_handler is not called. Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
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TODO
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@ -1,4 +1,4 @@
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NuttX TODO List (Last updated October 20, 2020)
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NuttX TODO List (Last updated November 20, 2020)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This file summarizes known NuttX bugs, limitations, inconsistencies with
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@ -10,7 +10,7 @@ issues related to each board port.
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nuttx/:
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(16) Task/Scheduler (sched/)
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(5) SMP
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(3) SMP
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(1) Memory Management (mm/)
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(0) Power Management (drivers/pm)
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(5) Signals (sched/signal, arch/)
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@ -468,37 +468,6 @@ o SMP
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Priority: Medium for SMP system. Not critical to single CPU systems.
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NOTE: There are no known bugs from this potential problem.
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Title: CORTEX-A GIC SGI INTERRUPT MASKING
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Description: In the ARMv7-A GICv2 architecture, the inter-processor
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interrupts (SGIs) are non maskable and will occur even if
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interrupts are disabled. This adds a lot of complexity
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to the ARMV7-A critical section design.
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Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR
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register to control SGI interrupts. This register (much like
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the ARMv7-M BASEPRI register) can be used to mask interrupts
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by interrupt priority. Since SGIs may be assigned priorities
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the ICCMPR should be able to block execution of SGIs as well.
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Such an implementation would be very similar to the BASEPRI
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(vs PRIMASK) implementation for the ARMv7-M: (1) The
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up_irq_save() and up_irq_restore() registers would have to
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set/restore the ICCMPR register, (2) register setup logic in
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arch/arm/src/armv7-a for task start-up and signal dispatch
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would have to set the ICCMPR correctly, and (3) the 'xcp'
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structure would have to be extended to hold the ICCMPR
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register; logic would have to added be save/restore the
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ICCMPR register in the 'xcp' structure on each interrupt and
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context switch.
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This would also be an essential part of a high priority,
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nested interrupt implementation (unrelated).
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Status: Open
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Priority: Low. There are no known issues with the current non-maskable
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SGI implementation. This change would, however, lead to
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simplification in the design and permit commonality with
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other, non-GIC implementations.
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Title: ISSUES WITH ACCESSING CPU INDEX
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Description: The CPU number is accessed usually with the macro this_cpu().
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The returned CPU number is then used for various things,
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@ -60,12 +60,6 @@
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bool up_interrupt_context(void)
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{
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#ifdef CONFIG_SMP
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/* REVISIT: Currently up_irq_save() will not disable the Software
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* Generated Interrupts (SGIs) for the case of ARMv7-A architecture using
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* the GIC. So this will not be sufficient in that case, at least not
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* until we add support for the ICCMPR.
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*/
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irqstate_t flags = up_irq_save();
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#endif
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@ -353,10 +353,6 @@ try_again_in_irq:
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* and try again. Briefly re-enabling interrupts should
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* be sufficient to permit processing the pending pause
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* request.
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*
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* NOTE: This should never happen on architectures like
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* the Cortex-A; the inter-CPU interrupt (SGI) is not
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* maskable.
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*/
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up_irq_restore(ret);
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