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S32K additional style fixes

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This commit is contained in:
Jari van Ewijk 2020-06-30 14:28:43 +02:00 committed by Abdelatif Guettouche
parent 86c151edf1
commit 1306cbc16e
3 changed files with 21 additions and 13 deletions
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23
arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h
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@ -78,12 +78,14 @@
#define S32K1XX_CMU1_BASE 0x4003f000 /* Clock Monitor Unit 1 */
#define S32K1XX_LPTMR0_BASE 0x40040000 /* Low-power timer 0 */
#define S32K1XX_SIM_BASE 0x40048000 /* System integration module */
#define S32K1XX_PORT_BASE(n) (0x40049000 + ((n) << 12)) /* Port n multiplexing control */
# define S32K1XX_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define S32K1XX_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define S32K1XX_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define S32K1XX_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define S32K1XX_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define S32K1XX_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define S32K1XX_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define S32K1XX_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define S32K1XX_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define S32K1XX_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
#define S32K1XX_WDOG_BASE 0x40052000 /* Software watchdog */
#define S32K1XX_SAI0_BASE 0x40054000 /* Synchronous Audio Interface 0 */
#define S32K1XX_SAI1_BASE 0x40055000 /* Synchronous Audio Interface 1 */
@ -107,12 +109,13 @@
#define S32K1XX_PMC_BASE 0x4007d000 /* Power management controller */
#define S32K1XX_SMC_BASE 0x4007e000 /* System Mode controller */
#define S32K1XX_RCM_BASE 0x4007f000 /* Reset Control Module */
#define S32K1XX_GPIO_BASE(n) (0x400ff000 +((n) << 6)) /* GPIO controller */
# define S32K1XX_GPIOA_BASE 0x400ff000 /* GPIOA controller */
# define S32K1XX_GPIOB_BASE 0x400ff040 /* GPIOB controller */
# define S32K1XX_GPIOC_BASE 0x400ff080 /* GPIOC controller */
# define S32K1XX_GPIOD_BASE 0x400ff0c0 /* GPIOD controller */
# define S32K1XX_GPIOE_BASE 0x400ff100 /* GPIOE controller */
# define S32K1XX_GPIOA_BASE 0x400ff000 /* GPIOA controller */
# define S32K1XX_GPIOB_BASE 0x400ff040 /* GPIOB controller */
# define S32K1XX_GPIOC_BASE 0x400ff080 /* GPIOC controller */
# define S32K1XX_GPIOD_BASE 0x400ff0c0 /* GPIOD controller */
# define S32K1XX_GPIOE_BASE 0x400ff100 /* GPIOE controller */
#if defined(CONFIG_ARCH_CHIP_S32K14X)
# define S32K1XX_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell */

2
arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h
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@ -155,6 +155,7 @@
#define PCC_PCD_SHIFT (0) /* Bits 0-2: Peripheral Clock Divider Select */
#define PCC_PCD_MASK (7 << PCC_PCD_SHIFT)
# define PCC_PCD(n) ((uint32_t)((n) - 1) << PCC_PCD_SHIFT) /* n=1..8 */
#define PCC_FRAC (1 << 3) /* Bits 3: Peripheral Clock Divider Fraction */
#define PCC_PCS_SHIFT (24) /* Bits 24-26: Peripheral Clock Source Select */
#define PCC_PCS_MASK (7 << PCC_PCS_SHIFT)
@ -167,6 +168,7 @@
# define PCC_PCS_OPTION5 (5 << PCC_PCS_SHIFT) /* Clock option 5 */
# define PCC_PCS_OPTION6 (6 << PCC_PCS_SHIFT) /* Clock option 6 */
# define PCC_PCS_OPTION7 (7 << PCC_PCS_SHIFT) /* Clock option 7 */
#define PCC_CGC (1 << 30) /* Clock Gate Control */
#define PCC_PR (1 << 31) /* Present */

9
arch/arm/src/s32k1xx/s32k1xx_pin.c
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@ -174,7 +174,9 @@ int s32k1xx_pinconfig(uint32_t cfgset)
putreg32(regval, base + S32K1XX_GPIO_PIDR_OFFSET);
/* Additional configuration for the case of Alternative 1 (GPIO) modes */
/* Additional configuration for the case of Alternative 1 (GPIO)
* modes
*/
if (mode == PIN_MODE_GPIO)
{
@ -198,7 +200,8 @@ int s32k1xx_pinconfig(uint32_t cfgset)
/* Set the initial value of the GPIO output */
s32k1xx_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_ONE) != 0));
s32k1xx_gpiowrite(cfgset,
((cfgset & GPIO_OUTPUT_ONE) != 0));
}
}
}
@ -223,7 +226,7 @@ int s32k1xx_pinconfig(uint32_t cfgset)
* false: Digital Filters are clocked by the 1 kHz LPO clock
* width - Filter Length
*
*****************************************************************************/
****************************************************************************/
int s32k1xx_pinfilter(unsigned int port, bool lpo, unsigned int width)
{