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arch/arm/src/lpc54xx: Add configuration logic to the empty SPI driver. Still missing all data tranfer logic.

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This commit is contained in:
Gregory Nutt 2018-01-13 15:38:55 -06:00
parent fdf4e40b6a
commit 134bac3810
4 changed files with 647 additions and 149 deletions
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83
arch/arm/src/lpc54xx/chip/lpc54_spi.h
View File

@ -260,33 +260,104 @@
/* Register bit definitions *************************************************************************/ /* Register bit definitions *************************************************************************/
/* SPI Configuration register */ /* SPI Configuration register */
#define SPI_CFG_
#define SPI_CFG_ENABLE (1 << 0) /* Bit 0: SPI enable */
#define SPI_CFG_MASTER (1 << 2) /* Bit 2: Master mode select */
#define SPI_CFG_LSBF (1 << 3) /* Bit 3: LSB First mode enable */
#define SPI_CFG_CPHA (1 << 4) /* Bit 4: Clock Phase select */
#define SPI_CFG_CPOL (1 << 5) /* Bit 5: Clock Polarity select */
#define SPI_CFG_LOOP (1 << 7) /* Bit 7: Loopback mode enable */
#define SPI_CFG_SPOL0 (1 << 8) /* Bit 8: SSEL0 Polarity select */
#define SPI_CFG_SPOL1 (1 << 9) /* Bit 9: SSEL1 Polarity select */
#define SPI_CFG_SPOL2 (1 << 10) /* Bit 10: SSEL2 Polarity select */
#define SPI_CFG_SPOL3 (1 << 11) /* Bit 11: SSEL3 Polarity select */
/* SPI Delay register */ /* SPI Delay register */
#define SPI_DLY_
#define SPI_DLY_PRE_DELAY_SHIFT (0) /* Bits 0-3: Time between SSEL assertion and data transfer */
#define SPI_DLY_PRE_DELAY_MASK (15 << SPI_DLY_PRE_DELAY_SHIFT)
# define SPI_DLY_PRE_DELAY(n) ((uint32_t)(n) << SPI_DLY_PRE_DELAY_SHIFT)
#define SPI_DLY_POST_DELAY_SHIFT (4) /* Bits 4-7: Time between tdata transfer and SSEL deassertion */
#define SPI_DLY_POST_DELAY_MASK (15 << SPI_DLY_POST_DELAY_SHIFT)
# define SPI_DLY_POST_DELAY(n) ((uint32_t)(n) << SPI_DLY_POST_DELAY_SHIFT)
#define SPI_DLY_FRAME_DELAY_SHIFT (8) /* Bits 8-11: Minimum amount of time between frames */
#define SPI_DLY_FRAME_DELAY_MASK (15 << SPI_DLY_FRAME_DELAY_SHIFT)
# define SPI_DLY_FRAME_DELAY(n) ((uint32_t)(n) << SPI_DLY_FRAME_DELAY_SHIFT)
#define SPI_DLY_TRANSFER_DELAY_SHIFT (12) /* Bits 12-15: Time SSEL deasserted between transfers */
#define SPI_DLY_TRANSFER_DELAY_MASK (15 << SPI_DLY_TRANSFER_DELAY_SHIFT)
# define SPI_DLY_TRANSFER_DELAY(n) ((uint32_t)(n) << SPI_DLY_TRANSFER_DELAY_SHIFT)
/* SPI Status register */ /* SPI Status register */
#define SPI_STAT_ #define SPI_STAT_
/* SPI Interrupt Enable read and set */ /* SPI Interrupt Enable read and set */
#define SPI_INTENSET_ #define SPI_INTENSET_
/* SPI Interrupt Enable Clear */ /* SPI Interrupt Enable Clear */
#define SPI_INTENCLR_ #define SPI_INTENCLR_
/* SPI clock Divider */ /* SPI clock Divider */
#define SPI_DIV_
#define SPI_DIV_SHIFT (0) /* Bits 0-15: Rate divider value */
#define SPI_DIV_MASK (0xffff << SPI_DIV_SHIFT)
# define SPI_DIV(n) ((uint32_t)((n)-1) << SPI_DIV_SHIFT)
/* SPI Interrupt Status */ /* SPI Interrupt Status */
#define SPI_INTSTAT_ #define SPI_INTSTAT_
/* FIFO configuration and enable register */ /* FIFO configuration and enable register */
#define SPI_FIFOCFG_
#define SPI_FIFOCFG_ENABLETX (1 << 0) /* Bit 0: Enable the transmit FIFO) */
#define SPI_FIFOCFG_ENABLERX (1 << 1) /* Bit 1: Enable the receive FIFO) */
#define SPI_FIFOCFG_SIZE_SHIFT (4) /* Bits 4-5: FIFO size configuration (read-only) */
#define SPI_FIFOCFG_SIZE_MASK (3 << SPI_FIFOCFG_SIZE_SHIFT)
# define SPI_FIFOCFG_SIZE_8x16 (1 << SPI_FIFOCFG_SIZE_SHIFT) /* FIFO is configured as 8 entries of 16 bits */
#define SPI_FIFOCFG_DMATX (1 << 12) /* Bit 12: DMA configuration for transmit */
#define SPI_FIFOCFG_DMARX (1 << 13) /* Bit 13: DMA configuration for receive */
#define SPI_FIFOCFG_WAKETX (1 << 14) /* Bit 14: Wake-up for transmit FIFO level */
#define SPI_FIFOCFG_WAKERX (1 << 15) /* Bit 15: Wake-up for receive FIFO level */
#define SPI_FIFOCFG_EMPTYTX (1 << 16) /* Bit 16: Empty command for the transmit FIFO) */
#define SPI_FIFOCFG_EMPTYRX (1 << 17) /* Bit 17: Empty command for the receive FIFO) */
/* FIFO status register */ /* FIFO status register */
#define SPI_FIFOSTAT_ #define SPI_FIFOSTAT_
/* FIFO trigger level settings for interrupt and DMA request */ /* FIFO trigger level settings for interrupt and DMA request */
#define SPI_FIFOTRIG_
#define SPI_FIFOTRIG_TXLVLENA (1 << 0) /* Bit 0 Transmit FIFO level trigger enable */
#define SPI_FIFOTRIG_RXLVLENA (1 << 1) /* Bit 1 Receive FIFO level trigger enable */
#define SPI_FIFOTRIG_TXLVL_SHIFT (8) /* Bits 8-11: Transmit FIFO level trigger point */
#define SPI_FIFOTRIG_TXLVL_MASK (15 << SPI_FIFOTRIG_TXLVL_SHIFT)
# define SPI_FIFOTRIG_TXLVL(n) ((uint32_t)(n) << SPI_FIFOTRIG_TXLVL_SHIFT)
# define SPI_FIFOTRIG_TXLVL_EMPTY (0 << SPI_FIFOTRIG_TXLVL_SHIFT)
# define SPI_FIFOTRIG_TXLVL_NOTFULL (7 << SPI_FIFOTRIG_TXLVL_SHIFT)
#define SPI_FIFOTRIG_RXLVL_SHIFT (16) /* Bits 16-19: Receive FIFO level trigger point */
#define SPI_FIFOTRIG_RXLVL_MASK (15 << SPI_FIFOTRIG_RXLVL_SHIFT)
# define SPI_FIFOTRIG_RXLVL(n) ((uint32_t)((n)-1) << SPI_FIFOTRIG_RXLVL_SHIFT)
# define SPI_FIFOTRIG_RXLVL_NOTEMPTY (0 << SPI_FIFOTRIG_RXLVL_SHIFT)
# define SPI_FIFOTRIG_RXLVL_FULL (7 << SPI_FIFOTRIG_RXLVL_SHIFT)
/* FIFO interrupt enable set (enable) and read register */ /* FIFO interrupt enable set (enable) and read register */
#define SPI_FIFOINTENSET_ #define SPI_FIFOINTENSET_
/* FIFO interrupt enable clear (disable) and read register */ /* FIFO interrupt enable clear (disable) and read register */
#define SPI_FIFOINTENCLR_ #define SPI_FIFOINTENCLR_
/* FIFO interrupt status register */ /* FIFO interrupt status register */
#define SPI_FIFOINTSTAT_ #define SPI_FIFOINTSTAT_
/* FIFO write data */ /* FIFO write data */
#define SPI_FIFOWR_
#define SPI_FIFOWR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit data to the FIFO */
#define SPI_FIFOWR_TXDATA_MASK (0xffff << SPI_FIFOWR_TXDATA_SHIFT)
# define SPI_FIFOWR_TXDATA(n) ((uint32_t)(n) << SPI_FIFOWR_TXDATA_SHIFT)
#define SPI_FIFOWR_TXSSEL0_N (1 << 16) /* Bit 16: Transmit Slave Select */
#define SPI_FIFOWR_TXSSEL1_N (1 << 17) /* Bit 17: Transmit Slave Select */
#define SPI_FIFOWR_TXSSEL2_N (1 << 18) /* Bit 18: Transmit Slave Select */
#define SPI_FIFOWR_TXSSEL3_N (1 << 19) /* Bit 19: Transmit Slave Select */
#define SPI_FIFOWR_EOT (1 << 20) /* Bit 20: End of Transfer */
#define SPI_FIFOWR_EOF (1 << 21) /* Bit 21: End of Frame */
#define SPI_FIFOWR_RXIGNORE (1 << 22) /* Bit 22: Receive Ignore */
#define SPI_FIFOWR_LEN_SHIFT (24) /* Bits 24-27: Data Length */
#define SPI_FIFOWR_LEN_MASK (15 << SPI_FIFOWR_LEN_SHIFT)
# define SPI_FIFOWR_LEN(n) ((uint32_t)((n)-1) << SPI_FIFOWR_LEN_SHIFT)
/* FIFO read data */ /* FIFO read data */
#define SPI_FIFORD_ #define SPI_FIFORD_
/* FIFO data read with no FIFO pop */ /* FIFO data read with no FIFO pop */

554
arch/arm/src/lpc54xx/lpc54_spi_master.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/lpc54xx/lpc54_spi.c * arch/arm/src/lpc54xx/lpc54_spi.c
* *
* Copyright (C) 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -67,11 +67,13 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
#define SPI_DUMMYDATA 0xff
/**************************************************************************** /****************************************************************************
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
/* This structure descibes the state of the SSP driver */ /* This structure describes the state of the SSP driver */
struct lpc54_spidev_s struct lpc54_spidev_s
{ {
@ -95,8 +97,6 @@ static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv);
/* SPI methods */ /* SPI methods */
static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock); static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock);
static void lpc54_spi_select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev, static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency); uint32_t frequency);
static void lpc54_spi_setmode(FAR struct spi_dev_s *dev, static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
@ -122,19 +122,20 @@ static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev,
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
static const struct spi_ops_s g_spi_ops = #ifdef CONFIG_LPC54_SPI0_MASTER
static const struct spi_ops_s g_spi0_ops =
{ {
.lock = lpc54_spi_lock, .lock = lpc54_spi_lock,
.select = lpc54_spiselect, .select = lpc54_spi0_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency, .setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode, .setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits, .setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES #ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = 0, /* Not supported */ .hwfeatures = NULL, /* Not supported */
#endif #endif
.status = lpc54_spistatus, .status = lpc54_spi0_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spicmddata, .cmddata = lpc54_spi0_cmddata, /* Provided externally */
#endif #endif
.send = lpc54_spi_send, .send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE #ifdef CONFIG_SPI_EXCHANGE
@ -144,40 +145,300 @@ static const struct spi_ops_s g_spi_ops =
.recvblock = lpc54_spi_recvblock, .recvblock = lpc54_spi_recvblock,
#endif #endif
#ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spiregister, /* Provided externally */ .registercallback = lpc54_spi0_register, /* Provided externally */
#else #else
.registercallback = 0, /* Not implemented */ .registercallback = NULL, /* Not implemented */
#endif #endif
}; };
#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_spidev_s g_spi0_dev; static struct lpc54_spidev_s g_spi0_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C1_MASTER
#ifdef CONFIG_LPC54_SPI1_MASTER
static const struct spi_ops_s g_spi1_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi1_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi1_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi1_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi1_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi1_dev; static struct lpc54_spidev_s g_spi1_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C2_MASTER
#ifdef CONFIG_LPC54_SPI2_MASTER
static const struct spi_ops_s g_spi2_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi2_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi2_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi2_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi2_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi2_dev; static struct lpc54_spidev_s g_spi2_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C3_MASTER
#ifdef CONFIG_LPC54_SPI3_MASTER
static const struct spi_ops_s g_spi3_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi3_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi3_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi3_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi3_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi3_dev; static struct lpc54_spidev_s g_spi3_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C4_MASTER
#ifdef CONFIG_LPC54_SPI4_MASTER
static const struct spi_ops_s g_spi4_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi4_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi4_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi4_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi4_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi4_dev; static struct lpc54_spidev_s g_spi4_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C5_MASTER
#ifdef CONFIG_LPC54_SPI5_MASTER
static const struct spi_ops_s g_spi5_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi5_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi5_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi5_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi5_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi5_dev; static struct lpc54_spidev_s g_spi5_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C6_MASTER
#ifdef CONFIG_LPC54_SPI6_MASTER
static const struct spi_ops_s g_spi6_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi6_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi6_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi6_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi6_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi6_dev; static struct lpc54_spidev_s g_spi6_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C7_MASTER
#ifdef CONFIG_LPC54_SPI7_MASTER
static const struct spi_ops_s g_spi7_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi7_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi7_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi7_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi7_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi7_dev; static struct lpc54_spidev_s g_spi7_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C8_MASTER
#ifdef CONFIG_LPC54_SPI8_MASTER
static const struct spi_ops_s g_spi8_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi8_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi8_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi8_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi8_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi8_dev; static struct lpc54_spidev_s g_spi8_dev;
#endif #endif
#ifdef CONFIG_LPC54_I2C9_MASTER
#ifdef CONFIG_LPC54_SPI9_MASTER
static const struct spi_ops_s g_spi9_ops =
{
.lock = lpc54_spi_lock,
.select = lpc54_spi9_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = NULL, /* Not supported */
#endif
.status = lpc54_spi9_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
.cmddata = lpc54_spi9_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = lpc54_spi_exchange,
#else
.sndblock = lpc54_spi_sndblock,
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc54_spi9_register, /* Provided externally */
#else
.registercallback = NULL, /* Not implemented */
#endif
};
static struct lpc54_spidev_s g_spi9_dev; static struct lpc54_spidev_s g_spi9_dev;
#endif #endif
@ -196,18 +457,18 @@ static struct lpc54_spidev_s g_spi9_dev;
static inline void lpc54_spi_putreg(struct lpc54_spidev_s *priv, static inline void lpc54_spi_putreg(struct lpc54_spidev_s *priv,
unsigned int regoffset, uint32_t regval) unsigned int regoffset, uint32_t regval)
{ {
putreg32(value, priv->base + regoffset); putreg32(regval, priv->base + regoffset);
} }
/**************************************************************************** /****************************************************************************
* Name: lpc54_spi_gettreg * Name: lpc54_spi_getreg
* *
* Description: * Description:
* Read the content of a register at the offset from the Flexcomm base. * Read the content of a register at the offset from the Flexcomm base.
* *
****************************************************************************/ ****************************************************************************/
static inline void lpc54_spi_gettreg(struct lpc54_spidev_s *priv, static inline uint32_t lpc54_spi_getreg(struct lpc54_spidev_s *priv,
unsigned int regoffset) unsigned int regoffset)
{ {
return getreg32(priv->base + regoffset); return getreg32(priv->base + regoffset);
@ -237,8 +498,8 @@ static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv)
* Name: lpc54_spi_lock * Name: lpc54_spi_lock
* *
* Description: * Description:
* On SPI busses where there are multiple devices, it will be necessary to * On SPI buses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the busses for a sequence of * lock SPI to have exclusive access to the buses for a sequence of
* transfers. The bus should be locked before the chip is selected. After * transfers. The bus should be locked before the chip is selected. After
* locking the SPI bus, the caller should then also call the setfrequency, * locking the SPI bus, the caller should then also call the setfrequency,
* setbits, and setmode methods to make sure that the SPI is properly * setbits, and setmode methods to make sure that the SPI is properly
@ -303,11 +564,15 @@ static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency) uint32_t frequency)
{ {
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
uint32_t divider;
uint32_t actual; uint32_t actual;
uint32_t regval;
/* Check if the requested frequence is the same as the frequency selection */ /* Check if the requested frequency is the same as the current frequency
* selection.
*/
DEBUGASSERT(priv && frequency <= priv->fclock / 2); DEBUGASSERT(priv != NULL && frequency <= priv->fclock / 2);
if (priv->frequency == frequency) if (priv->frequency == frequency)
{ {
@ -317,7 +582,21 @@ static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
} }
/* Set the new SPI frequency */ /* Set the new SPI frequency */
#warning Missing logic
divider = priv->fclock / frequency;
if (divider > 0x10000)
{
divider = 0x10000;
}
regval = lpc54_spi_getreg(priv, LPC54_SPI_DIV_OFFSET);
regval &= ~SPI_DIV_MASK;
regval |= SPI_DIV(divider);
lpc54_spi_putreg(priv, LPC54_SPI_DIV_OFFSET, regval);
/* Calculate the actual frequency */
actual = priv->fclock / divider;
/* Save the frequency setting */ /* Save the frequency setting */
@ -354,24 +633,25 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
if (mode != priv->mode) if (mode != priv->mode)
{ {
/* Yes... Set the new mode */ /* Yes... Set the new mode */
#warning Missing logic
regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
regval &= ~(SPI_CFG_CPHA | SPI_CFG_CPOL);
switch (mode) switch (mode)
{ {
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
#warning Missing logic
break; break;
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
#warning Missing logic regval |= SPI_CFG_CPHA;
break; break;
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
#warning Missing logic regval |= SPI_CFG_CPOL;
break; break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
#warning Missing logic regval |= (SPI_CFG_CPHA | SPI_CFG_CPOL);
break; break;
default: default:
@ -379,9 +659,9 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
return; return;
} }
#warning Missing logic lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }
@ -405,18 +685,14 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits) static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{ {
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
uint32_t regval;
/* Has the number of bits changed? */ /* The valid range of bit selections is 4 through 16 */
DEBUGASSERT(priv && nbits > 7 && nbits < 17); DEBUGASSERT(priv != NULL && nbits >=4 && nbits <= 16);
if (nbits != priv->nbits) if (nbits >= 4 && nbits <= 16)
{ {
/* Yes... Set the number word width */ /* Save the selection. It will be applied when data is transferred. */
#warning Missing logic
/* Save the selection so the subsequence re-configurations will be faster */
priv->nbits = nbits; priv->nbits = nbits;
} }
@ -494,8 +770,8 @@ static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
{ {
/* 16-bit mode */ /* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer; FAR const uint16_t *src = (FAR const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *)rxbuffer; FAR uint16_t *dest = (FAR uint16_t *)rxbuffer;
uint16_t word; uint16_t word;
while (nwords-- > 0) while (nwords-- > 0)
@ -513,7 +789,7 @@ static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
/* Exchange one word */ /* Exchange one word */
word = spi_send(dev, word); word = lpc54_spi_send(dev, word);
/* Is there a buffer to receive the return value? */ /* Is there a buffer to receive the return value? */
@ -527,8 +803,8 @@ static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
{ {
/* 8-bit mode */ /* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer; FAR const uint8_t *src = (FAR const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *)rxbuffer; FAR uint8_t *dest = (FAR uint8_t *)rxbuffer;
uint8_t word; uint8_t word;
while (nwords-- > 0) while (nwords-- > 0)
@ -546,7 +822,7 @@ static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
/* Exchange one word */ /* Exchange one word */
word = (uint8_t)spi_send(dev, (uint16_t)word); word = (uint8_t)lpc54_spi_send(dev, (uint16_t)word);
/* Is there a buffer to receive the return value? */ /* Is there a buffer to receive the return value? */
@ -615,8 +891,8 @@ static void lpc54_spi_exchange(FAR struct spi_dev_s *dev,
static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev, static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
FAR const void *buffer, size_t nwords) FAR const void *buffer, size_t nwords)
{ {
spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); spiinfo("txbuffer=%p nwords=%d\n", buffer, nwords);
return lpc54_spi_exchange(dev, txbuffer, NULL, nwords); return lpc54_spi_exchange(dev, buffer, NULL, nwords);
} }
/**************************************************************************** /****************************************************************************
@ -642,8 +918,8 @@ static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords) size_t nwords)
{ {
spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); spiinfo("rxbuffer=%p nwords=%d\n", buffer, nwords);
return lpc54_spi_exchange(dev, NULL, rxbuffer, nwords); return lpc54_spi_exchange(dev, NULL, buffer, nwords);
} }
/**************************************************************************** /****************************************************************************
@ -672,6 +948,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
{ {
struct lpc54_spidev_s *priv; struct lpc54_spidev_s *priv;
irqstate_t flags; irqstate_t flags;
uint32_t regval;
flags = enter_critical_section(); flags = enter_critical_section();
@ -680,7 +957,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
* lpc54_lowputc.c. * lpc54_lowputc.c.
*/ */
#ifdef CONFIG_LPC54_I2C0_MASTER #ifdef CONFIG_LPC54_SPI0_MASTER
if (port == 0) if (port == 0)
{ {
/* Attach 12 MHz clock to FLEXCOMM0 */ /* Attach 12 MHz clock to FLEXCOMM0 */
@ -698,14 +975,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi0_dev; priv = &g_spi0_dev;
priv->base = LPC54_FLEXCOMM0_BASE; priv->base = LPC54_FLEXCOMM0_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM0; priv->irq = LPC54_IRQ_FLEXCOMM0;
priv->fclock = BOARD_FLEXCOMM0_FCLK; priv->fclock = BOARD_FLEXCOMM0_FCLK;
priv->dev.ops = &g_spi0_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C0_SCK); lpc54_gpio_config(GPIO_SPI0_SCK);
lpc54_gpio_config(GPIO_I2C0_MOSI); lpc54_gpio_config(GPIO_SPI0_MOSI);
lpc54_gpio_config(GPIO_I2C0_MISO); lpc54_gpio_config(GPIO_SPI0_MISO);
/* Set up the FLEXCOMM0 function clock */ /* Set up the FLEXCOMM0 function clock */
@ -713,7 +991,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C1_MASTER #ifdef CONFIG_LPC54_SPI1_MASTER
if (port == 1) if (port == 1)
{ {
/* Attach 12 MHz clock to FLEXCOMM1 */ /* Attach 12 MHz clock to FLEXCOMM1 */
@ -731,14 +1009,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi1_dev; priv = &g_spi1_dev;
priv->base = LPC54_FLEXCOMM1_BASE; priv->base = LPC54_FLEXCOMM1_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM1; priv->irq = LPC54_IRQ_FLEXCOMM1;
priv->fclock = BOARD_FLEXCOMM1_FCLK; priv->fclock = BOARD_FLEXCOMM1_FCLK;
priv->dev.ops = &g_spi1_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C1_SCK); lpc54_gpio_config(GPIO_SPI1_SCK);
lpc54_gpio_config(GPIO_I2C1_MOSI); lpc54_gpio_config(GPIO_SPI1_MOSI);
lpc54_gpio_config(GPIO_I2C1_MISO); lpc54_gpio_config(GPIO_SPI1_MISO);
/* Set up the FLEXCOMM1 function clock */ /* Set up the FLEXCOMM1 function clock */
@ -746,7 +1025,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C2_MASTER #ifdef CONFIG_LPC54_SPI2_MASTER
if (port == 2) if (port == 2)
{ {
/* Attach 12 MHz clock to FLEXCOMM2 */ /* Attach 12 MHz clock to FLEXCOMM2 */
@ -764,14 +1043,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi2_dev; priv = &g_spi2_dev;
priv->base = LPC54_FLEXCOMM2_BASE; priv->base = LPC54_FLEXCOMM2_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM2; priv->irq = LPC54_IRQ_FLEXCOMM2;
priv->fclock = BOARD_FLEXCOMM2_FCLK; priv->fclock = BOARD_FLEXCOMM2_FCLK;
priv->dev.ops = &g_spi2_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C2_SCK); lpc54_gpio_config(GPIO_SPI2_SCK);
lpc54_gpio_config(GPIO_I2C2_MOSI); lpc54_gpio_config(GPIO_SPI2_MOSI);
lpc54_gpio_config(GPIO_I2C2MISO); lpc54_gpio_config(GPIO_SPI2MISO);
/* Set up the FLEXCOMM2 function clock */ /* Set up the FLEXCOMM2 function clock */
@ -779,7 +1059,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C3_MASTER #ifdef CONFIG_LPC54_SPI3_MASTER
if (port == 3) if (port == 3)
{ {
/* Attach 12 MHz clock to FLEXCOMM3 */ /* Attach 12 MHz clock to FLEXCOMM3 */
@ -797,14 +1077,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi3_dev; priv = &g_spi3_dev;
priv->base = LPC54_FLEXCOMM3_BASE; priv->base = LPC54_FLEXCOMM3_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM3; priv->irq = LPC54_IRQ_FLEXCOMM3;
priv->fclock = BOARD_FLEXCOMM3_FCLK; priv->fclock = BOARD_FLEXCOMM3_FCLK;
priv->dev.ops = &g_spi3_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C3_SCK); lpc54_gpio_config(GPIO_SPI3_SCK);
lpc54_gpio_config(GPIO_I2C3_MOSI); lpc54_gpio_config(GPIO_SPI3_MOSI);
lpc54_gpio_config(GPIO_I2C3_MISO); lpc54_gpio_config(GPIO_SPI3_MISO);
/* Set up the FLEXCOMM3 function clock */ /* Set up the FLEXCOMM3 function clock */
@ -812,7 +1093,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C4_MASTER #ifdef CONFIG_LPC54_SPI4_MASTER
if (port == 4) if (port == 4)
{ {
/* Attach 12 MHz clock to FLEXCOMM4 */ /* Attach 12 MHz clock to FLEXCOMM4 */
@ -830,14 +1111,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi4_dev; priv = &g_spi4_dev;
priv->base = LPC54_FLEXCOMM4_BASE; priv->base = LPC54_FLEXCOMM4_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM4; priv->irq = LPC54_IRQ_FLEXCOMM4;
priv->fclock = BOARD_FLEXCOMM4_FCLK; priv->fclock = BOARD_FLEXCOMM4_FCLK;
priv->dev.ops = &g_spi4_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C4_SCK); lpc54_gpio_config(GPIO_SPI4_SCK);
lpc54_gpio_config(GPIO_I2C4_MOSI); lpc54_gpio_config(GPIO_SPI4_MOSI);
lpc54_gpio_config(GPIO_I2C4_MISO); lpc54_gpio_config(GPIO_SPI4_MISO);
/* Set up the FLEXCOMM4 function clock */ /* Set up the FLEXCOMM4 function clock */
@ -845,7 +1127,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C5_MASTER #ifdef CONFIG_LPC54_SPI5_MASTER
if (port == 5) if (port == 5)
{ {
/* Attach 12 MHz clock to FLEXCOMM5 */ /* Attach 12 MHz clock to FLEXCOMM5 */
@ -863,14 +1145,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi5_dev; priv = &g_spi5_dev;
priv->base = LPC54_FLEXCOMM5_BASE; priv->base = LPC54_FLEXCOMM5_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM5; priv->irq = LPC54_IRQ_FLEXCOMM5;
priv->fclock = BOARD_FLEXCOMM5_FCLK; priv->fclock = BOARD_FLEXCOMM5_FCLK;
priv->dev.ops = &g_spi5_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C5_SCK); lpc54_gpio_config(GPIO_SPI5_SCK);
lpc54_gpio_config(GPIO_I2C5_MOSI); lpc54_gpio_config(GPIO_SPI5_MOSI);
lpc54_gpio_config(GPIO_I2C5_MISO); lpc54_gpio_config(GPIO_SPI5_MISO);
/* Set up the FLEXCOMM5 function clock */ /* Set up the FLEXCOMM5 function clock */
@ -878,7 +1161,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C6_MASTER #ifdef CONFIG_LPC54_SPI6_MASTER
if (port == 6) if (port == 6)
{ {
/* Attach 12 MHz clock to FLEXCOMM6 */ /* Attach 12 MHz clock to FLEXCOMM6 */
@ -896,14 +1179,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi6_dev; priv = &g_spi6_dev;
priv->base = LPC54_FLEXCOMM6_BASE; priv->base = LPC54_FLEXCOMM6_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM6; priv->irq = LPC54_IRQ_FLEXCOMM6;
priv->fclock = BOARD_FLEXCOMM6_FCLK; priv->fclock = BOARD_FLEXCOMM6_FCLK;
priv->dev.ops = &g_spi6_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C6_SCK); lpc54_gpio_config(GPIO_SPI6_SCK);
lpc54_gpio_config(GPIO_I2C6_MOSI); lpc54_gpio_config(GPIO_SPI6_MOSI);
lpc54_gpio_config(GPIO_I2C6_MISO); lpc54_gpio_config(GPIO_SPI6_MISO);
/* Set up the FLEXCOMM6 function clock */ /* Set up the FLEXCOMM6 function clock */
@ -911,7 +1195,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C7_MASTER #ifdef CONFIG_LPC54_SPI7_MASTER
if (port == 7) if (port == 7)
{ {
/* Attach 12 MHz clock to FLEXCOMM7 */ /* Attach 12 MHz clock to FLEXCOMM7 */
@ -929,14 +1213,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi7_dev; priv = &g_spi7_dev;
priv->base = LPC54_FLEXCOMM7_BASE; priv->base = LPC54_FLEXCOMM7_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM7; priv->irq = LPC54_IRQ_FLEXCOMM7;
priv->fclock = BOARD_FLEXCOMM7_FCLK; priv->fclock = BOARD_FLEXCOMM7_FCLK;
priv->dev.ops = &g_spi7_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C7_SCK); lpc54_gpio_config(GPIO_SPI7_SCK);
lpc54_gpio_config(GPIO_I2C7_MOSI); lpc54_gpio_config(GPIO_SPI7_MOSI);
lpc54_gpio_config(GPIO_I2C7_MISO); lpc54_gpio_config(GPIO_SPI7_MISO);
/* Set up the FLEXCOMM7 function clock */ /* Set up the FLEXCOMM7 function clock */
@ -944,7 +1229,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C8_MASTER #ifdef CONFIG_LPC54_SPI8_MASTER
if (port == 8) if (port == 8)
{ {
/* Attach 12 MHz clock to FLEXCOMM8 */ /* Attach 12 MHz clock to FLEXCOMM8 */
@ -962,14 +1247,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi8_dev; priv = &g_spi8_dev;
priv->base = LPC54_FLEXCOMM8_BASE; priv->base = LPC54_FLEXCOMM8_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM8; priv->irq = LPC54_IRQ_FLEXCOMM8;
priv->fclock = BOARD_FLEXCOMM8_FCLK; priv->fclock = BOARD_FLEXCOMM8_FCLK;
priv->dev.ops = &g_spi8_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C8_SCK); lpc54_gpio_config(GPIO_SPI8_SCK);
lpc54_gpio_config(GPIO_I2C8_MOSI); lpc54_gpio_config(GPIO_SPI8_MOSI);
lpc54_gpio_config(GPIO_I2C8_MISO); lpc54_gpio_config(GPIO_SPI8_MISO);
/* Set up the FLEXCOMM8 function clock */ /* Set up the FLEXCOMM8 function clock */
@ -977,7 +1263,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
} }
else else
#endif #endif
#ifdef CONFIG_LPC54_I2C9_MASTER #ifdef CONFIG_LPC54_SPI9_MASTER
if (port == 9) if (port == 9)
{ {
/* Attach 12 MHz clock to FLEXCOMM9 */ /* Attach 12 MHz clock to FLEXCOMM9 */
@ -995,14 +1281,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi9_dev; priv = &g_spi9_dev;
priv->base = LPC54_FLEXCOMM9_BASE; priv->base = LPC54_FLEXCOMM9_BASE;
priv->irqid = LPC54_IRQ_FLEXCOMM9; priv->irq = LPC54_IRQ_FLEXCOMM9;
priv->fclock = BOARD_FLEXCOMM9_FCLK; priv->fclock = BOARD_FLEXCOMM9_FCLK;
priv->dev.ops = &g_spi9_ops;
/* Configure SPI pins (defined in board.h) */ /* Configure SPI pins (defined in board.h) */
lpc54_gpio_config(GPIO_I2C9_SCK); lpc54_gpio_config(GPIO_SPI9_SCK);
lpc54_gpio_config(GPIO_I2C9_MOSI); lpc54_gpio_config(GPIO_SPI9_MOSI);
lpc54_gpio_config(GPIO_I2C9_MISO); lpc54_gpio_config(GPIO_SPI9_MISO);
/* Set up the FLEXCOMM9 function clock */ /* Set up the FLEXCOMM9 function clock */
@ -1016,24 +1303,69 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
leave_critical_section(flags); leave_critical_section(flags);
/* Enable the SPI peripheral*/
/* Configure 8-bit SPI mode and master mode */
#warning Missing logic
/* Set the initial SPI configuration */ /* Set the initial SPI configuration */
priv->frequency = 0; priv->frequency = 0;
priv->nbits = 8; priv->nbits = 8;
priv->mode = SPIDEV_MODE0; priv->mode = SPIDEV_MODE0;
priv->dev.ops = &g_spi_ops;
/* Initialize the SPI semaphore that enforces mutually exclusive access */
nxsem_init(&priv->exclsem, 0, 1);
/* Configure master mode in mode 0:
*
* ENABLE - Disabled for now (0)
* MASTER - Master mode (1)
* LSBF - MSB first (0)
* CPHA/CPOL - Mode 0 (0,0)
* LOOP - Disable loopback mode (0)
* SPOLn - Active low (0,0,0)
*/
regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
regval &= ~(SPI_CFG_ENABLE | SPI_CFG_LSBF | SPI_CFG_CPHA | SPI_CFG_CPOL |
SPI_CFG_LOOP | SPI_CFG_SPOL0 | SPI_CFG_SPOL1 | SPI_CFG_SPOL2 |
SPI_CFG_SPOL3);
regval |= SPI_CFG_MASTER;
lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
/* Enable FIFOs */
regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
regval |= (SPI_FIFOCFG_EMPTYTX | SPI_FIFOCFG_EMPTYRX);
lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
regval |= (SPI_FIFOCFG_ENABLETX | SPI_FIFOCFG_ENABLERX);
lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
/* Set FIFO trigger levels: Empty for Tx FIFO; 1 word for RxFIFO */
regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
regval &= ~(SPI_FIFOTRIG_TXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK);
regval |= (SPI_FIFOTRIG_TXLVL_EMPTY | SPI_FIFOTRIG_RXLVL_NOTEMPTY);
/* Enable generation of interrupts for selected FIFO trigger levels */
regval |= (SPI_FIFOTRIG_TXLVLENA | SPI_FIFOTRIG_RXLVLENA);
lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
/* Set the delay configuration (not used) */
regval = (SPI_DLY_PRE_DELAY(0) | SPI_DLY_POST_DELAY(0) | SPI_DLY_FRAME_DELAY(0) |
SPI_DLY_TRANSFER_DELAY(0));
lpc54_spi_putreg(priv, LPC54_SPI_DLY_OFFSET, regval);
/* Select a default frequency of approx. 400KHz */ /* Select a default frequency of approx. 400KHz */
lpc54_spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); lpc54_spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
/* Initialize the SPI semaphore that enforces mutually exclusive access */ /* Enable the SPI peripheral */
regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
regval |= SPI_CFG_ENABLE;
lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->dev; return &priv->dev;
} }

145
arch/arm/src/lpc54xx/lpc54_spi_master.h
View File

@ -109,45 +109,111 @@ extern "C"
FAR struct spi_dev_s *lpc54_spibus_initialize(int port); FAR struct spi_dev_s *lpc54_spibus_initialize(int port);
/************************************************************************************ /************************************************************************************
* Name: lpc54_spiselect, lpc54_spistatus, and lpc54_spicmddata * Name: lpc54_spiN_select, lpc54_spiN_status, and lpc54_spiN_cmddata
* *
* Description: * Description:
* These functions must be provided in your board-specific logic. The * These functions must be provided in your board-specific logic. The
* lpc54_spiselect function will perform chip selection and the lpc54_spistatus * lpc54_spiN_select function will perform chip selection and the lpc54_spiN_status
* will perform status operations using GPIOs in the way your board is configured. * will perform status operations using GPIOs in the way your board is configured.
* *
* If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then * If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
* lpc54_spicmddata must also be provided. This functions performs cmd/data * lpc54_spiN_cmddata must also be provided. This functions performs cmd/data
* selection operations using GPIOs in the way your board is configured. * selection operations using GPIOs in the way your board is configured.
* *
************************************************************************************/ ************************************************************************************/
void lpc54_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); #ifdef CONFIG_LPC54_SPI0_MASTER
uint8_t lpc54_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); void lpc54_spi0_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi0_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_SPI_CMDDATA
int lpc54_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); int lpc54_spi0_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI1_MASTER
void lpc54_spi1_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi1_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi1_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI2_MASTER
void lpc54_spi2_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi2_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi2_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI3_MASTER
void lpc54_spi3_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi3_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi3_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI4_MASTER
void lpc54_spi4_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi4_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi4_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI5_MASTER
void lpc54_spi5_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi5_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi5_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI6_MASTER
void lpc54_spi6_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi6_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi6_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI7_MASTER
void lpc54_spi7_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi7_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi7_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI8_MASTER
void lpc54_spi8_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi8_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi8_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_LPC54_SPI9_MASTER
void lpc54_spi9_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
uint8_t lpc54_spi9_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int lpc54_spi9_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif #endif
/************************************************************************************ /************************************************************************************
* Name: spi_flush * Name: lpc54_spiN_register
*
* Description:
* Flush and discard any words left in the RX fifo. This can be called from
* spiselect after a device is deselected (if you worry about such things).
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* None
*
************************************************************************************/
void spi_flush(FAR struct spi_dev_s *dev);
/************************************************************************************
* Name: lpc54_spi/spiregister
* *
* Description: * Description:
* If the board supports a card detect callback to inform the SPI-based MMC/SD * If the board supports a card detect callback to inform the SPI-based MMC/SD
@ -167,7 +233,36 @@ void spi_flush(FAR struct spi_dev_s *dev);
************************************************************************************/ ************************************************************************************/
#ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_SPI_CALLBACK
int lpc54_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #ifdef CONFIG_LPC54_SPI0_MASTER
int lpc54_spi0_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI1_MASTER
int lpc54_spi1_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI2_MASTER
int lpc54_spi2_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI3_MASTER
int lpc54_spi3_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI4_MASTER
int lpc54_spi4_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI5_MASTER
int lpc54_spi5_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI6_MASTER
int lpc54_spi6_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI7_MASTER
int lpc54_spi7_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI8_MASTER
int lpc54_spi8_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_LPC54_SPI9_MASTER
int lpc54_spi9_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
#endif #endif
#undef EXTERN #undef EXTERN

4
sched/init/os_start.c
View File

@ -115,7 +115,7 @@ volatile dq_queue_t g_readytorun;
* and * and
* - Tasks/threads that have not been assigned to a CPU. * - Tasks/threads that have not been assigned to a CPU.
* *
* Otherwise, the TCB will be reatined in an assigned task list, * Otherwise, the TCB will be retained in an assigned task list,
* g_assignedtasks. As its name suggests, on 'g_assignedtasks queue for CPU * g_assignedtasks. As its name suggests, on 'g_assignedtasks queue for CPU
* 'n' would contain only tasks/threads that are assigned to CPU 'n'. Tasks/ * 'n' would contain only tasks/threads that are assigned to CPU 'n'. Tasks/
* threads would be assigned a particular CPU by one of two mechanisms: * threads would be assigned a particular CPU by one of two mechanisms:
@ -187,7 +187,7 @@ volatile dq_queue_t g_waitingforfill;
volatile dq_queue_t g_inactivetasks; volatile dq_queue_t g_inactivetasks;
/* These are lists of dayed memory deallocations that need to be handled /* These are lists of delayed memory deallocations that need to be handled
* within the IDLE loop or worker thread. These deallocations get queued * within the IDLE loop or worker thread. These deallocations get queued
* by sched_kufree and sched_kfree() if the OS needs to deallocate memory * by sched_kufree and sched_kfree() if the OS needs to deallocate memory
* while it is within an interrupt handler. * while it is within an interrupt handler.