diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5890c600a..c38f9cc04f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -109,6 +109,13 @@ config ARCH_CHIP_NUC1XX ---help--- NPX LPC43XX architectures (ARM Cortex-M4). +config ARCH_CHIP_SAMA5 + bool "Atmel AT91SAMA5" + select ARCH_CORTEXA5 + select ARCH_HAVE_FPU + ---help--- + Atmel AT91SAMA5 (ARM Cortex-A5) + config ARCH_CHIP_SAM34 bool "Atmel AT91SAM3/SAM4" select ARCH_HAVE_MPU @@ -192,6 +199,7 @@ config ARCH_CHIP default "lpc31xx" if ARCH_CHIP_LPC31XX default "lpc43xx" if ARCH_CHIP_LPC43XX default "nuc1xx" if ARCH_CHIP_NUC1XX + default "sama5" if ARCH_CHIP_SAMA5 default "sam34" if ARCH_CHIP_SAM34 default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X @@ -344,6 +352,9 @@ endif if ARCH_CHIP_NUC1XX source arch/arm/src/nuc1xx/Kconfig endif +if ARCH_CHIP_SAMA5 +source arch/arm/src/sama5/Kconfig +endif if ARCH_CHIP_SAM34 source arch/arm/src/sam34/Kconfig endif diff --git a/arch/arm/include/sama5/chip.h b/arch/arm/include/sama5/chip.h new file mode 100644 index 0000000000..8a727e0f4d --- /dev/null +++ b/arch/arm/include/sama5/chip.h @@ -0,0 +1,118 @@ +/************************************************************************************ + * arch/arm/include/samad5/chip.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_SAMAD5_CHIP_H +#define __ARCH_ARM_INCLUDE_SAMAD5_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* SAMA5D3 Family + * + * ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 + * ------------------------- ------------- ------------- ------------- ------------- + * Pin Count 324 324 324 324 + * Max. Operating Frequency 536 536 536 536 + * CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 + * Max I/O Pins 160 160 160 160 + * Ext Interrupts 160 160 160 160 + * USB Transceiver 3 3 3 3 + * USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed + * USB Interface Host, Device Host, Device Host, Device Host, Device + * SPI 6 6 6 6 + * TWI (I2C) 3 3 3 3 + * UART 7 5 5 7 + * CAN - - 2 2 + * LIN 4 4 4 4 + * SSC 2 2 2 2 + * Ethernet 1 1 1 2 + * SD / eMMC 3 2 3 3 + * Graphic LCD Yes Yes Yes - + * Camera Interface Yes Yes Yes Yes + * ADC channels 12 12 12 12 + * ADC Resolution (bits) 12 12 12 12 + * ADC Speed (ksps) 440 440 440 440 + * Resistive Touch Screen Yes Yes Yes Yes + * Crypto Engine AES/DES/ AES/DES/ AES/DES/ AES/DES/ + * SHA/TRNG SHA/TRNG SHA/TRNG SHA/TRNG + * SRAM (Kbytes) 128 128 128 128 + * External Bus Interface 1 1 1 1 + * DRAM Memory DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, + * SDRAM/LPSDR SDRAM/LPSDR DDR2/LPDDR, DDR2/LPDDR, + * NAND Interface Yes Yes Yes Yes + * Temp. Range (deg C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 + * I/O Supply Class 1.8/3.3 1.8/3.3 1.8/3.3 1.8/3.3 + * Operating Voltage (Vcc) 1.08 to 1.32 1.08 to 1.32 1.08 to 1.32 1.08 to 1.32 + * FPU Yes Yes Yes Yes + * MPU / MMU No/Yes No/Yes No/Yes No/Yes + * Timers 5 5 5 6 + * Output Compare channels 6 6 6 6 + * Input Capture Channels 6 6 6 6 + * PWM Channels 4 4 4 4 + * 32kHz RTC Yes Yes Yes Yes + * Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A + */ + +#if defined(CONFIG_ARCH_CHIP_ATSAMA5D31) +# define ATSAMA5D3 1 /* SAMA5D3 family */ +#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33) +# define ATSAMA5D3 1 /* SAMA5D3 family */ +#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34) +# define ATSAMA5D3 1 /* SAMA5D3 family */ +#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35) +# define ATSAMA5D3 1 /* SAMA5D3 family */ +#else +# error Unrecognized SAMAD5 chip +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_SAMAD5_CHIP_H */ diff --git a/arch/arm/include/sama5/irq.h b/arch/arm/include/sama5/irq.h new file mode 100644 index 0000000000..d8c113192a --- /dev/null +++ b/arch/arm/include/sama5/irq.h @@ -0,0 +1,90 @@ +/**************************************************************************************** + * arch/arm/include/sama5/irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAMA5_IRQ_H +#define __ARCH_ARM_INCLUDE_SAMA5_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include +#include + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* Chip-Specific External interrupts */ + +#if defined(ATSAMA5D3) +# include +#else +# error Unrecognized SAMA5 family +#endif + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAMA5_IRQ_H */ + diff --git a/arch/arm/include/sama5/sama5d3_irq.h b/arch/arm/include/sama5/sama5d3_irq.h new file mode 100644 index 0000000000..872a393e9e --- /dev/null +++ b/arch/arm/include/sama5/sama5d3_irq.h @@ -0,0 +1,396 @@ +/**************************************************************************************** + * arch/arm/include/sama5/sama5d3_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAMA5_SAMA5D3_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAMA5_SAMA5D3_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAMA5D3 Peripheral Identifiers */ + +#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */ +#define SAM_PID_SYS (1) /* System Controller Interrupt PMC */ +#define SAM_PID_DBGU (2) /* Debug Unit Interrupt */ +#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */ +#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */ +#define SAM_PID_HSMC (5) /* Multi-bit ECC Interrupt */ +#define SAM_PID_PIOA (6) /* Parallel I/O Controller A */ +#define SAM_PID_PIOB (7) /* Parallel I/O Controller B */ +#define SAM_PID_PIOC (8) /* Parallel I/O Controller C */ +#define SAM_PID_PIOD (9) /* Parallel I/O Controller D */ +#define SAM_PID_PIOE (10) /* Parallel I/O Controller E */ +#define SAM_PID_SMD (11) /* SMD Soft Modem */ +#define SAM_PID_USART0 (12) /* USART 0 */ +#define SAM_PID_USART1 (13) /* USART 1 */ +#define SAM_PID_USART2 (14) /* USART 2 */ +#define SAM_PID_USART3 (15) /* USART 3 */ +#define SAM_PID_UART0 (16) /* UART 0 */ +#define SAM_PID_UART1 (17) /* UART 1 */ +#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */ +#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */ +#define SAM_PID_TWI2 (20) /* Two-Wire Interface 2 */ +#define SAM_PID_HSMCI0 (21) /* High Speed Multimedia Card Interface 0 */ +#define SAM_PID_HSMCI1 (22) /* High Speed Multimedia Card Interface 1 */ +#define SAM_PID_HSMCI2 (23) /* High Speed Multimedia Card Interface 2 */ +#define SAM_PID_SPI0 (24) /* Serial Peripheral Interface 0 */ +#define SAM_PID_SPI1 (25) /* Serial Peripheral Interface 1 */ +#define SAM_PID_TC0 (26) /* Timer Counter 0 (ch. 0, 1, 2) */ +#define SAM_PID_TC1 (27) /* Timer Counter 1 (ch. 3, 4, 5) */ +#define SAM_PID_PWM (28) /* Pulse Width Modulation Controller */ +#define SAM_PID_ADC (29) /* Touch Screen ADC Controller */ +#define SAM_PID_DMAC0 (30) /* DMA Controller 0 */ +#define SAM_PID_DMAC1 (31) /* DMA Controller 1 */ +#define SAM_PID_UHPHS (32) /* USB Host High Speed */ +#define SAM_PID_UDPHS (33) /* USB Device High Speed */ +#define SAM_PID_GMAC (34) /* Gigabit Ethernet MAC */ +#define SAM_PID_EMAC (35) /* Ethernet MAC */ +#define SAM_PID_LCDC (36) /* LCD Controller */ +#define SAM_PID_ISI (37) /* Image Sensor Interface */ +#define SAM_PID_SSC0 (38) /* Synchronous Serial Controller 0 */ +#define SAM_PID_SSC1 (39) /* Synchronous Serial Controller 1 */ +#define SAM_PID_CAN0 (40) /* CAN controller 0 */ +#define SAM_PID_CAN1 (41) /* CAN controller 1 */ +#define SAM_PID_SHA (42) /* Secure Hash Algorithm */ +#define SAM_PID_AES (43) /* Advanced Encryption Standard */ +#define SAM_PID_TDES (44) /* Triple Data Encryption Standard */ +#define SAM_PID_TRNG (45) /* True Random Number Generator */ +#define SAM_PID_ARM (46) /* Performance Monitor Unit */ +#define SAM_PID_AIC (47) /* Advanced Interrupt Controller IRQ */ +#define SAM_PID_FUSE (48) /* Fuse Controller */ +#define SAM_PID_MPDDRC (49) /* MPDDR controller */ + /* 50-63 Reserved */ + +/* External interrupts vectors numbers (same as peripheral ID) */ + +#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */ +#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC */ +#define SAM_IRQ_DBGU SAM_PID_DBGU /* Debug Unit Interrupt */ +#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */ +#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */ +#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */ +#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */ +#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */ +#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */ +#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */ +#define SAM_IRQ_PIOE SAM_PID_PIOE /* Parallel I/O Controller E */ +#define SAM_IRQ_SMD SAM_PID_SMD /* SMD Soft Modem */ +#define SAM_IRQ_USART0 SAM_PID_USART0 /* USART 0 */ +#define SAM_IRQ_USART1 SAM_PID_USART1 /* USART 1 */ +#define SAM_IRQ_USART2 SAM_PID_USART2 /* USART 2 */ +#define SAM_IRQ_USART3 SAM_PID_USART3 /* USART 3 */ +#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */ +#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */ +#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */ +#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */ +#define SAM_IRQ_TWI2 SAM_PID_TWI2 /* Two-Wire Interface 2 */ +#define SAM_IRQ_HSMCI0 SAM_PID_HSMCI0 /* High Speed Multimedia Card Interface 0 */ +#define SAM_IRQ_HSMCI1 SAM_PID_HSMCI1 /* High Speed Multimedia Card Interface 1 */ +#define SAM_IRQ_HSMCI2 SAM_PID_HSMCI2 /* High Speed Multimedia Card Interface 2 */ +#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */ +#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */ +#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */ +#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */ +#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */ +#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */ +#define SAM_IRQ_DMAC0 SAM_PID_DMAC0 /* DMA Controller 0 */ +#define SAM_IRQ_DMAC1 SAM_PID_DMAC1 /* DMA Controller 1 */ +#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */ +#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */ +#define SAM_IRQ_GMAC SAM_PID_GMAC /* Gigabit Ethernet MAC */ +#define SAM_IRQ_EMAC SAM_PID_EMAC /* Ethernet MAC */ +#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */ +#define SAM_IRQ_ISI SAM_PID_ISI /* Image Sensor Interface */ +#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */ +#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */ +#define SAM_IRQ_CAN0 SAM_PID_CAN0 /* CAN controller 0 */ +#define SAM_IRQ_CAN1 SAM_PID_CAN1 /* CAN controller 1 */ +#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */ +#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */ +#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */ +#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */ +#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */ +#define SAM_IRQ_AIC SAM_PID_AIC /* Advanced Interrupt Controller IRQ */ +#define SAM_IRQ_FUSE SAM_PID_FUSE /* Fuse Controller */ +#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */ + +#define SAM_IRQ_NINT (SAM_PID_MPDDRC + 1) + +/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */ + +#ifdef CONFIG_SAMA5_PIOA_IRQ +# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT) +# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */ +# define SAM_NPIOAIRQS 32 +#else +# define SAM_NPIOAIRQS 0 +#endif + +#ifdef CONFIG_SAMA5_PIOB_IRQ +# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS) +# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */ +# define SAM_NPIOBIRQS 32 +#else +# define SAM_NPIOBIRQS 0 +#endif + +#ifdef CONFIG_SAMA5_PIOC_IRQ +# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS) +# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */ +# define SAM_NPIOCIRQS 32 +#else +# define SAM_NPIOCIRQS 0 +#endif + +#ifdef CONFIG_SAMA5_PIOD_IRQ +# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \ + SAM_NPIOCIRQS) +# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */ +# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */ +# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */ +# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */ +# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */ +# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */ +# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */ +# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */ +# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */ +# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */ +# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */ +# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */ +# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */ +# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */ +# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */ +# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */ +# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */ +# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */ +# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */ +# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */ +# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */ +# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */ +# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */ +# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */ +# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */ +# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */ +# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */ +# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */ +# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */ +# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */ +# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */ +# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */ +# define SAM_NPIODIRQS 32 +#else +# define SAM_NPIODIRQS 0 +#endif + +#ifdef CONFIG_SAMA5_PIOE_IRQ +# define SAM_IRQ_PIOE_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + \ + SAM_NPIOBIRQS + SAM_NPIOCIRQS + SAM_NPIODIRQS) +# define SAM_IRQ_PE0 (SAM_IRQ_PIOE_PINS+0) /* PIOE, PIN 0 */ +# define SAM_IRQ_PE1 (SAM_IRQ_PIOE_PINS+1) /* PIOE, PIN 1 */ +# define SAM_IRQ_PE2 (SAM_IRQ_PIOE_PINS+2) /* PIOE, PIN 2 */ +# define SAM_IRQ_PE3 (SAM_IRQ_PIOE_PINS+3) /* PIOE, PIN 3 */ +# define SAM_IRQ_PE4 (SAM_IRQ_PIOE_PINS+4) /* PIOE, PIN 4 */ +# define SAM_IRQ_PE5 (SAM_IRQ_PIOE_PINS+5) /* PIOE, PIN 5 */ +# define SAM_IRQ_PE6 (SAM_IRQ_PIOE_PINS+6) /* PIOE, PIN 6 */ +# define SAM_IRQ_PE7 (SAM_IRQ_PIOE_PINS+7) /* PIOE, PIN 7 */ +# define SAM_IRQ_PE8 (SAM_IRQ_PIOE_PINS+8) /* PIOE, PIN 8 */ +# define SAM_IRQ_PE9 (SAM_IRQ_PIOE_PINS+9) /* PIOE, PIN 9 */ +# define SAM_IRQ_PE10 (SAM_IRQ_PIOE_PINS+10) /* PIOE, PIN 10 */ +# define SAM_IRQ_PE11 (SAM_IRQ_PIOE_PINS+11) /* PIOE, PIN 11 */ +# define SAM_IRQ_PE12 (SAM_IRQ_PIOE_PINS+12) /* PIOE, PIN 12 */ +# define SAM_IRQ_PE13 (SAM_IRQ_PIOE_PINS+13) /* PIOE, PIN 13 */ +# define SAM_IRQ_PE14 (SAM_IRQ_PIOE_PINS+14) /* PIOE, PIN 14 */ +# define SAM_IRQ_PE15 (SAM_IRQ_PIOE_PINS+15) /* PIOE, PIN 15 */ +# define SAM_IRQ_PE16 (SAM_IRQ_PIOE_PINS+16) /* PIOE, PIN 16 */ +# define SAM_IRQ_PE17 (SAM_IRQ_PIOE_PINS+17) /* PIOE, PIN 17 */ +# define SAM_IRQ_PE18 (SAM_IRQ_PIOE_PINS+18) /* PIOE, PIN 18 */ +# define SAM_IRQ_PE19 (SAM_IRQ_PIOE_PINS+19) /* PIOE, PIN 19 */ +# define SAM_IRQ_PE20 (SAM_IRQ_PIOE_PINS+20) /* PIOE, PIN 20 */ +# define SAM_IRQ_PE21 (SAM_IRQ_PIOE_PINS+21) /* PIOE, PIN 21 */ +# define SAM_IRQ_PE22 (SAM_IRQ_PIOE_PINS+22) /* PIOE, PIN 22 */ +# define SAM_IRQ_PE23 (SAM_IRQ_PIOE_PINS+23) /* PIOE, PIN 23 */ +# define SAM_IRQ_PE24 (SAM_IRQ_PIOE_PINS+24) /* PIOE, PIN 24 */ +# define SAM_IRQ_PE25 (SAM_IRQ_PIOE_PINS+25) /* PIOE, PIN 25 */ +# define SAM_IRQ_PE26 (SAM_IRQ_PIOE_PINS+26) /* PIOE, PIN 26 */ +# define SAM_IRQ_PE27 (SAM_IRQ_PIOE_PINS+27) /* PIOE, PIN 27 */ +# define SAM_IRQ_PE28 (SAM_IRQ_PIOE_PINS+28) /* PIOE, PIN 28 */ +# define SAM_IRQ_PE29 (SAM_IRQ_PIOE_PINS+29) /* PIOE, PIN 29 */ +# define SAM_IRQ_PE30 (SAM_IRQ_PIOE_PINS+30) /* PIOE, PIN 30 */ +# define SAM_IRQ_PE31 (SAM_IRQ_PIOE_PINS+31) /* PIOE, PIN 31 */ +# define SAM_NPIOEIRQS 32 +#else +# define SAM_NPIOEIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_NINT + \ + SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \ + SAM_NPIODIRQS + SAM_NPIOEIRQS ) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAMA5_SAMA5D3_IRQ_H */ + diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig new file mode 100644 index 0000000000..f3cc87fa7b --- /dev/null +++ b/arch/arm/src/sama5/Kconfig @@ -0,0 +1,239 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_CHIP_SAMA5 + +comment "ATSAMA5 Configuration Options" + +choice + prompt "Atmel AT91SAMA5 Chip Selection" + default ARCH_CHIP_ATSAMA5D33 + +config ARCH_CHIP_ATSAMA5D31 + bool "Atmel ATSAMA5D31" + select ARCH_CHIP_SAMA5D3 + +config ARCH_CHIP_ATSAMA5D33 + bool "Atmel ATSAMA5D33" + select ARCH_CHIP_SAMA5D3 + +config ARCH_CHIP_ATSAMA5D34 + bool "Atmel ATSAMA5D34" + select ARCH_CHIP_SAMA5D3 + +config ARCH_CHIP_ATSAMA5D35 + bool "Atmel ATSAMA5D35" + select ARCH_CHIP_SAMA5D3 + +endchoice + +menu "ATSAMA5 Peripheral Support" + +config SAMA5_DBGU + bool "Debug Unit Interrupt (DBGU)" + default n + +config SAMA5_PIT + bool "Periodic Interval Timer Interrupt (PIT)" + default n + +config SAMA5_WDT + bool "Watchdog timer Interrupt (WDT)" + default n + +config SAMA5_HSMC + bool "Multi-bit ECC Interrupt (HSMC)" + default n + +config SAMA5_SMD + bool "SMD Soft Modem (SMD)" + default n + +config SAMA5_UART0 + bool "UART 0" + default y + select ARCH_HAVE_UART0 + +config SAMA5_UART1 + bool "UART 1" + default n + select ARCH_HAVE_UART1 + +config SAMA5_USART0 + bool "USART 0" + default n + select ARCH_HAVE_USART0 + +config SAMA5_USART1 + bool "USART 1" + default n + select ARCH_HAVE_USART1 + +config SAMA5_USART2 + bool "USART 2" + default n + select ARCH_HAVE_USART2 + +config SAMA5_USART3 + bool "USART 3" + default n + select ARCH_HAVE_USART3 + +config SAMA5_TWI0 + bool "Two-Wire Interface 0 (TWI0)" + default n + +config SAMA5_TWI1 + bool "Two-Wire Interface 1 (TWI1)" + default n + +config SAMA5_TWI2 + bool "Two-Wire Interface 2 (TWI2)" + default n + +config SAMA5_HSMCI0 + bool "High Speed Multimedia Card Interface 0 (HSMCI0)" + default n + +config SAMA5_HSMCI1 + bool "High Speed Multimedia Card Interface 1 (HSMCI1)" + default n + +config SAMA5_HSMCI2 + bool "High Speed Multimedia Card Interface 2 (HSMCI2)" + default n + +config SAMA5_SPI0 + bool "Serial Peripheral Interface 0 (SPI0)" + default n + +config SAMA5_SPI1 + bool "Serial Peripheral Interface 1 (SPI1)" + default n + +config SAMA5_TC0 + bool "Timer Counter 0 (ch. 0, 1, 2) (TC0)" + default n + +config SAMA5_TC1 + bool "Timer Counter 1 (ch. 3, 4, 5) (TC1)" + default n + +config SAMA5_PWM + bool "Pulse Width Modulation Controller (PWM)" + default n + +config SAMA5_ADC + bool "Touch Screen ADC Controller (ADC)" + default n + +config SAMA5_DMAC0 + bool "DMA Controller 0 (DMAC0)" + default n + +config SAMA5_DMAC1 + bool "DMA Controller 1 (DMAC1)" + default n + +config SAMA5_UHPHS + bool "USB Host High Speed (UHPHS)" + default n + +config SAMA5_UDPHS + bool "USB Device High Speed (UDPHS)" + default n + +config SAMA5_GMAC + bool "Gigabit Ethernet MAC (GMAC)" + default n + +config SAMA5_EMAC + bool "Ethernet MAC (EMAC)" + default n + +config SAMA5_LCDC + bool "LCD Controller (LCDC)" + default n + +config SAMA5_ISI + bool "Image Sensor Interface (ISI)" + default n + +config SAMA5_SSC0 + bool "Synchronous Serial Controller 0 (SSC0)" + default n + +config SAMA5_SSC1 + bool "Synchronous Serial Controller 1 (SSC1)" + default n + +config SAMA5_CAN0 + bool "CAN controller 0 (CAN0)" + default n + +config SAMA5_CAN1 + bool "CAN controller 1 (CAN1)" + default n + +config SAMA5_SHA + bool "Secure Hash Algorithm (SHA)" + default n + +config SAMA5_AES + bool "Advanced Encryption Standard (AES)" + default n + +config SAMA5_TDES + bool "Triple Data Encryption Standard (TDES)" + default n + +config SAMA5_TRNG + bool "True Random Number Generator (TRNG)" + default n + +config SAMA5_ARM + bool "Performance Monitor Unit (ARM)" + default n + +config SAMA5_FUSE + bool "Fuse Controller (FUSE)" + default n + +config SAMA5_MPDDRC + bool "MPDDR controller (MPDDRC)" + default n + +endmenu + +config PIO_IRQ + bool "PIO pin interrupts" + ---help--- + Enable support for interrupting PIO pins + +if PIO_IRQ + +config PIOA_IRQ + bool "PIOA interrupts" + default n + +config PIOB_IRQ + bool "PIOB interrupts" + default n + +config PIOC_IRQ + bool "PIOC interrupts" + default n + +config PIOD_IRQ + bool "PIOD interrupts" + default n + +config PIOE_IRQ + bool "PIOE interrupts" + default n + +endif + +endif diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs new file mode 100644 index 0000000000..7d6390a26f --- /dev/null +++ b/arch/arm/src/sama5/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# arch/arm/samad5/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name Gregory Nutt nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = arm_head.S + +CMN_ASRCS = arm_vectors.S arm_vectortab.S arm_fullcontextrestore.S +CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S + +CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c +CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c +CMN_CSRCS += up_mdelay.c up_udelay.c +CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c + +CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copystate.c arm_dataabort.c +CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_prefetchabort.c +CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c +CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c +CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c + +ifeq ($(CONFIG_PAGING),y) +CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c +CMN_CSRCS += arm_va2pte.c +endif + +ifeq ($(CONFIG_ELF),y) +CMN_CSRCS += arm_elf.c +endif + +CHIP_ASRCS = + +CHIP_CSRCS =