Add configuration support for SAMD21
This commit is contained in:
Gregory Nutt
parent
046e849459
commit
138830d53f
@ -291,6 +291,7 @@
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMDL_NTRNG 0 /* No True random number generator */
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# define SAMDL_NSERCOM 4 /* 4 SERCOM */
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# define SAMDL_NI2S 0 /* No I2S */
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# define SAMDL_NADC 10 /* 10 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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@ -314,6 +315,7 @@
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMDL_NTRNG 0 /* No True random number generator */
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# define SAMDL_NSERCOM 6 /* 6 SERCOM */
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# define SAMDL_NI2S 0 /* No I2S */
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# define SAMDL_NADC 15 /* 14 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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@ -337,6 +339,7 @@
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMDL_NTRNG 0 /* No True random number generator */
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# define SAMDL_NSERCOM 6 /* 6 SERCOM */
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# define SAMDL_NI2S 0 /* No I2S */
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# define SAMDL_NADC 20 /* 20 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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@ -350,8 +353,293 @@
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# define SAMDL_WDT 1 /* Have watchdog timer */
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#endif
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/* SAML21 Family ********************************************************************/
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/* SAMD21 Family ********************************************************************/
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/* FEATURE SAM D21J SAM D21G SAM D21E
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* ------------------- ------------------ ------------------ --------
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* No. of pins 64 48 32
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* Flash 256/128/64/32/16KB 256/128/64/32KB 256/128/64/32KB
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* SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4KB
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* Max. Freq. 48MHz 48MHz 48MHz
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* Event channels 12 12 12
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* Timer/counters 5 3 3
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* TC output channels 2 2 2
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* T/C Control 3 3 3
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* TCC output channels 2 2 2
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* TCC waveform output 8/4/2 8/4/2 6/4/2
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* DMA channels 12 12 12
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* USB interface 1 1 1
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* SERCOM 6 6 4
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* I2S 1 1 1
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* ADC channels 20 14 10
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* Comparators 2 2 2
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* DAC channels 1 1 1
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* RTC Yes Yes Yes
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* RTC alarms 1 1 1
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* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
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* External interrupts 16 16 16
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* PTC X an Y 16x16 12x10 10x6
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* Packages QFN/TQFP QFN/TQFP/WLCSP QFN/TQFP/UFBGA
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* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC8M, DFLL48M, and FDPLL96M
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* SW Debug interface Yes Yes Yes
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* Watchdog timer Yes Yes Yes
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*/
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#if defined(CONFIG_ARCH_CHIP_SAMD21E15A) || defined(CONFIG_ARCH_CHIP_SAMD21E15B)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E16A) || defined(CONFIG_ARCH_CHIP_SAMD21E16B)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E17A)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E18A)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G15A) || defined(CONFIG_ARCH_CHIP_SAMD21G15B)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# define SAMD21G 1 /* SAMD21G */
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G16A) || defined(CONFIG_ARCH_CHIP_SAMD21G16B)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# define SAMD21G 1 /* SAMD21G */
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G17A)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# define SAMD21G 1 /* SAMD21G */
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21G18A)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# define SAMD21G 1 /* SAMD21G */
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# undef SAMD21J
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J15A) || defined(CONFIG_ARCH_CHIP_SAMD21J15B)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# undef SAMD21G
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# define SAMD21J 1 /* SAMD21J */
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J16A) || defined(CONFIG_ARCH_CHIP_SAMD21J16B)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# undef SAMD21G
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# define SAMD21J 1 /* SAMD21J */
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J17A)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# undef SAMD21G
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# define SAMD21J 1 /* SAMD21J */
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD21J18A)
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# define SAMD21 1 /* SAMD21 family */
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# undef SAMD21E
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# undef SAMD21G
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# define SAMD21J 1 /* SAMD21J */
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (0*1024) /* None - except on B device variant */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#else
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# undef SAMD21 /* Not SAMD21 family */
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# undef SAMD21E
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# undef SAMD21G
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# undef SAMD21J
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#endif
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#if defined(SAMD21E)
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# define SAMDL_NEVENTS 12 /* 12 event channels */
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# define SAMDL_NTC 3 /* 3 Timer/counters */
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
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# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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# define SAMDL_NTRNG 1 /* 1 True random number generator */
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# define SAMDL_NSERCOM 4 /* 4 SERCOM */
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# define SAMDL_NI2S 1 /* 1 I2S */
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# define SAMDL_NADC 10 /* 10 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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# define SAMCL_NOPAMP 3 /* 3 OpAmps */
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# define SAMDL_RTC 1 /* Have RTC */
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# define SAMDL_NALARMS 1 /* 1 RTC alarm */
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# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMDL_NEXTINT 16 /* 16 External interrupts */
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# define SAMDL_NPTCX 10 /* 10x6 */
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# define SAMDL_NPTCY 6 /* 10x6*/
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# define SAMDL_WDT 1 /* Have watchdog timer */
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#elif defined(SAMD21G)
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# define SAMDL_NEVENTS 12 /* 12 event channels */
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# define SAMDL_NTC 3 /* 3 Timer/counters */
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
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# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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# define SAMDL_NTRNG 1 /* 1 True random number generator */
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# define SAMDL_NSERCOM 6 /* 6 SERCOM */
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# define SAMDL_NI2S 1 /* 1 I2S */
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# define SAMDL_NADC 14 /* 14 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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# define SAMCL_NOPAMP 3 /* 3 OpAmps */
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# define SAMDL_RTC 1 /* Have RTC */
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# define SAMDL_NALARMS 1 /* 1 RTC alarm */
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# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMDL_NEXTINT 16 /* 16 External interrupts */
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# define SAMDL_NPTCX 12 /* 12x10 */
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# define SAMDL_NPTCY 10 /* 12x10 */
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# define SAMDL_WDT 1 /* Have watchdog timer */
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#elif defined(SAMD21J)
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# define SAMDL_NEVENTS 12 /* 12 event channels */
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# define SAMDL_NTC 5 /* 5 Timer/counters */
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
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# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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# define SAMDL_NTRNG 1 /* 1 True random number generator */
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# define SAMDL_NSERCOM 6 /* 6 SERCOM */
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# define SAMDL_NI2S 1 /* 1 I2S */
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# define SAMDL_NADC 20 /* 20 ADC channels */
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# define SAMDL_NCMP 2 /* 2 Comparators */
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# define SAMDL_NDAC 1 /* 1 DAC channel */
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# define SAMCL_NOPAMP 3 /* 3 OpAmps */
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# define SAMDL_RTC 1 /* Have RTC */
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# define SAMDL_NALARMS 1 /* 1 RTC alarm */
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# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMDL_NEXTINT 16 /* 16 External interrupts */
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# define SAMDL_NPTCX 16 /* 16x16 */
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# define SAMDL_NPTCY 16 /* 16x16*/
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# define SAMDL_WDT 1 /* Have watchdog timer */
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#endif
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/* SAML21 Family ********************************************************************/
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/* FEATURE SAM L21J SAM L21G SAM L21E
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* ------------------- ------------------ ------------------ --------
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* No. of pins 64 48 32
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* Flash 256/128/64KB 256/128/64KB 256/128/64/32KB
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@ -402,7 +690,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21E16)
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@ -420,7 +708,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21E17)
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@ -438,7 +726,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21E18)
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@ -456,7 +744,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 6 /* 6 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 6 /* 6 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21G16)
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@ -474,7 +762,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21G17)
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@ -492,7 +780,7 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21G18)
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@ -510,14 +798,14 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21J16)
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# define SAML21 1 /* SAML21 family */
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# undef SAML21E
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# undef SAML21G
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# define SAML21J /* SAML21J */
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# define SAML21J 1 /* SAML21J */
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/* Internal memory */
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@ -528,14 +816,14 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21J17)
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# define SAML21 1 /* SAML21 family */
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# undef SAML21E
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# undef SAML21G
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# define SAML21J /* SAML21J */
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# define SAML21J 1 /* SAML21J */
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/* Internal memory */
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@ -546,14 +834,14 @@
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/* TCC waveform outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC wavefor outputs */
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# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
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#elif defined(CONFIG_ARCH_CHIP_SAML21J18)
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# define SAML21 1 /* SAML21 family */
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# undef SAML21E
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# undef SAML21G
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# define SAML21J /* SAML21J */
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# define SAML21J 1 /* SAML21J */
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/* Internal memory */
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@ -564,7 +852,7 @@
|
||||
|
||||
/* TCC waveform outputs */
|
||||
|
||||
# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC wavefor outputs */
|
||||
# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
|
||||
|
||||
#else
|
||||
|
||||
@ -587,6 +875,7 @@
|
||||
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
|
||||
# define SAMDL_NTRNG 1 /* 1 True random number generator */
|
||||
# define SAMDL_NSERCOM 4 /* 4 SERCOM */
|
||||
# define SAMDL_NI2S 0 /* No I2S */
|
||||
# define SAMDL_NADC 10 /* 10 ADC channels */
|
||||
# define SAMDL_NCMP 2 /* 2 Comparators */
|
||||
# define SAMDL_NDAC 2 /* 2 DAC channels */
|
||||
@ -610,6 +899,7 @@
|
||||
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
|
||||
# define SAMDL_NTRNG 1 /* 1 True random number generator */
|
||||
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
|
||||
# define SAMDL_NI2S 0 /* No I2S */
|
||||
# define SAMDL_NADC 14 /* 14 ADC channels */
|
||||
# define SAMDL_NCMP 2 /* 2 Comparators */
|
||||
# define SAMDL_NDAC 2 /* 2 DAC channels */
|
||||
@ -633,6 +923,7 @@
|
||||
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
|
||||
# define SAMDL_NTRNG 1 /* 1 True random number generator */
|
||||
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
|
||||
# define SAMDL_NI2S 0 /* No I2S */
|
||||
# define SAMDL_NADC 20 /* 20 ADC channels */
|
||||
# define SAMDL_NCMP 2 /* 2 Comparators */
|
||||
# define SAMDL_NDAC 2 /* 2 DAC channels */
|
||||
|
||||
@ -131,6 +131,150 @@ config ARCH_CHIP_SAMD20J18
|
||||
---help---
|
||||
Flash 256KB SRAM 32KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E15A
|
||||
bool "SAMD21E15A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E15B
|
||||
bool "SAMD21E15B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E16A
|
||||
bool "SAMD21E16A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E16B
|
||||
bool "SAMD21E16B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E17A
|
||||
bool "SAMD21E17A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 128KB SRAM 16KB
|
||||
|
||||
config ARCH_CHIP_SAMD21E18A
|
||||
bool "SAMD21E18A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 256KB SRAM 32KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G15A
|
||||
bool "SAMD21G15A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21G
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G15B
|
||||
bool "SAMD21G15B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21G
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G16A
|
||||
bool "SAMD21G16A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21G
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G16B
|
||||
bool "SAMD21G16B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G17A
|
||||
bool "SAMD21G17A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21G
|
||||
---help---
|
||||
Flash 128KB SRAM 16KB
|
||||
|
||||
config ARCH_CHIP_SAMD21G18A
|
||||
bool "SAMD21G18A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21G
|
||||
---help---
|
||||
Flash 256KB SRAM 32KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J15A
|
||||
bool "SAMD21J15A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21J
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J15B
|
||||
bool "SAMD21J15B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21J
|
||||
---help---
|
||||
Flash 32KB SRAM 4KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J16A
|
||||
bool "SAMD21J16A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21J
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J16B
|
||||
bool "SAMD21J16B"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21J
|
||||
---help---
|
||||
Flash 64KB SRAM 8KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J17A
|
||||
bool "SAMD21J17A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21E
|
||||
---help---
|
||||
Flash 128KB SRAM 16KB
|
||||
|
||||
config ARCH_CHIP_SAMD21J18A
|
||||
bool "SAMD21J18A"
|
||||
depends on ARCH_CHIP_SAMD
|
||||
select ARCH_FAMILY_SAMD21
|
||||
select ARCH_FAMILY_SAMD21J
|
||||
---help---
|
||||
Flash 256KB SRAM 32KB
|
||||
|
||||
config ARCH_CHIP_SAML21E15
|
||||
bool "SAML21E15"
|
||||
depends on ARCH_CHIP_SAML
|
||||
@ -238,6 +382,30 @@ config ARCH_FAMILY_SAMD20J
|
||||
select SAMDL_HAVE_TC6
|
||||
select SAMDL_HAVE_TC7
|
||||
|
||||
config ARCH_FAMILY_SAMD21
|
||||
bool
|
||||
default n
|
||||
select SAMDL_HAVE_DMAC
|
||||
|
||||
config ARCH_FAMILY_SAMD21E
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_FAMILY_SAMD21G
|
||||
bool
|
||||
default n
|
||||
select SAMDL_HAVE_SERCOM4
|
||||
select SAMDL_HAVE_SERCOM5
|
||||
|
||||
config ARCH_FAMILY_SAMD21J
|
||||
bool
|
||||
default n
|
||||
select SAMDL_HAVE_SERCOM4
|
||||
select SAMDL_HAVE_SERCOM5
|
||||
select SAMDL_HAVE_TC2
|
||||
select SAMDL_HAVE_TC3
|
||||
select SAMDL_HAVE_TC5
|
||||
|
||||
config ARCH_FAMILY_SAML21
|
||||
bool
|
||||
default n
|
||||
|
||||
Loading…
Reference in New Issue
Block a user