diff --git a/Documentation/README.html b/Documentation/README.html index 65a1bbe0d8..4291196ed3 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -180,6 +180,8 @@ | | | `- README.txt | | |- pic32mx7mmb/ | | | `- README.txt + | | |- pic32mz-starterkit/ + | | | `- README.txt | | |- pirelli_dpl10/ | | | `- README.txt | | |- qemu-i486/ diff --git a/README.txt b/README.txt index 3db22193ab..b9dee33eef 100644 --- a/README.txt +++ b/README.txt @@ -1237,6 +1237,8 @@ nuttx | | `- README.txt | |- pic32mx7mmb/ | | `- README.txt + | |- pic32mz-starterkit/ + | | `- README.txt | |- pirelli_dpl10/ | | `- README.txt | |- qemu-i486/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1a6bf9537b..d6f87d1195 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -16,7 +16,17 @@ config ARCH_CHIP_PIC32MX select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_SERIAL_TERMIOS ---help--- - Microchip PIC32MX320F032H (MIPS32) + Microchip PIC32MX (MIPS32) + +config ARCH_CHIP_PIC32MZ + bool "PIC32MZ" + select ARCH_MIPS32 + select ARCH_HAVE_IRQPRIO + select ARCH_VECNOTIRQ + select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_SERIAL_TERMIOS + ---help--- + Microchip PIC32MZ (MIPS32) endchoice @@ -32,9 +42,11 @@ config ARCH_FAMILY config ARCH_CHIP string default "pic32mx" if ARCH_CHIP_PIC32MX + default "pic32mz" if ARCH_CHIP_PIC32MZ source arch/mips/src/common/Kconfig source arch/mips/src/mips32/Kconfig source arch/mips/src/pic32mx/Kconfig +source arch/mips/src/pic32mz/Kconfig endif diff --git a/arch/mips/include/pic32mz/chip.h b/arch/mips/include/pic32mz/chip.h new file mode 100644 index 0000000000..eaf661eee5 --- /dev/null +++ b/arch/mips/include/pic32mz/chip.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/chip.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_CHIP_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +config ARCH_CHIP_PIC32MZ2048ECH + bool "PIC32MZ2048ECH" + select ARCH_CHIP_PIC32MZEC + ---help--- + Microchip PIC32MZ2048ECH (MIPS32) + ARCH_CHIP_PIC32MZ1 + +config ARCH_CHIP_PIC32MZ2048ECM + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 144 pin package (PIC32MZ2048ECH144) and should be reviewed for + * other parts. + */ + +#if defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECH) +# define CHIP_PIC32MZEC 1 +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NCRTYPO 0 /* No crtypo support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 144 pin package (PIC32MZ2048ECM144) and should be reviewed for + * other parts. + */ + +#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECM) +# define CHIP_PIC32MZEC 1 +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NCRTYPO 1 /* Has crtypo support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +#else +# error "Unrecognized PIC32MZ device +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_CHIP_H */ diff --git a/arch/mips/include/pic32mz/cp0.h b/arch/mips/include/pic32mz/cp0.h new file mode 100644 index 0000000000..bcb8512332 --- /dev/null +++ b/arch/mips/include/pic32mz/cp0.h @@ -0,0 +1,397 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/cp0.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* CP0 Register Addresses ***************************************************/ + +#ifdef __ASSEMBLY__ +# define PIC32MZ_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */ +# define PIC32MZ_CP0_BADVADDR $8,0 /* Address of most recent exception */ +# define PIC32MZ_CP0_COUNT $9,0 /* Processor cycle count */ +# define PIC32MZ_CP0_COMPARE $11,0 /* Timer interrupt control */ +# define PIC32MZ_CP0_STATUS $12,0 /* Processor status and control */ +# define PIC32MZ_CP0_INTCTL $12,1 /* Interrupt system status and control */ +# define PIC32MZ_CP0_SRSCTL $12,2 /* Shadow register set status and control */ +# define PIC32MZ_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */ +# define PIC32MZ_CP0_CAUSE $13,0 /* Cause of last general exception */ +# define PIC32MZ_CP0_EPC $14,0 /* Program counter at last exception */ +# define PIC32MZ_CP0_PRID $15,0 /* Processor identification and revision */ +# define PIC32MZ_CP0_EBASE $15,1 /* Exception vector base register */ +# define PIC32MZ_CP0_CONFIG $16,0 /* Configuration register */ +# define PIC32MZ_CP0_CONFIG1 $16,1 /* Configuration register 1 */ +# define PIC32MZ_CP0_CONFIG2 $16,2 /* Configuration register 3 */ +# define PIC32MZ_CP0_CONFIG3 $16,3 /* Configuration register 3 */ +# define PIC32MZ_CP0_DEBUG $23,3 /* Debug control and exception status */ +# define PIC32MZ_CP0_DEPC $24,3 /* Program counter at last debug exception */ +# define PIC32MZ_CP0_ERREPC $30,3 /* Program counter at last error */ +# define PIC32MZ_CP0_DESAVE $31,3 /* Debug handler scratchpad register */ +#endif + +/* CP0 Registers ************************************************************/ + +/* Register Number: 0-6: Reserved + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + */ + +/* Register Number: 7 Sel: 0 Name: HWREna + * Function: Enables access via the RDHWR instruction to selected hardware + * registers in non-privileged mode. + * Compliance Level: (Reserved for future extensions) + */ + +#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */ +#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT) + +/* Register Number: 8 Sel: 0 Name: BadVAddr + * Function: Reports the address for the most recent address-related + * exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 9 Sel: 0 Name: Count + * Function: Processor cycle count + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 10 Reserved. + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * + * Register Number: 11 Sel: 0 Name: Compare + * Function: Timer interrupt control + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 12 Sel: 0 Name: Status + * Function: Processor status and control + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * NOTES: + * 1. The following are reserved bits in the PIC32: + * CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32) + * CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32) + * CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32) + * CP0_STATUS_IMPL Bits 16-17: Implementation dependent + * CP0_STATUS_TS Bit 21: TLB detected match on multiple entries + * CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32) + * CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32) + */ + +#undef CP0_STATUS_UX +#undef CP0_STATUS_SX +#undef CP0_STATUS_KX +#undef CP0_STATUS_IMPL +#undef CP0_STATUS_IMPL_SHIFT +#undef CP0_STATUS_IMPL_MASK +#undef CP0_STATUS_TS +#undef CP0_STATUS_PX +#undef CP0_STATUS_MX + +/* 2. The following field is of a different width. Apparently, it + * excludes the software interrupt bits. + * + * CP0_STATUS_IM Bits 8-15: Interrupt Mask + * Vs. + * CP0_STATUS_IPL Bits 10-15: Interrupt priority level + * Bitss 8-9 reserved + */ + +#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */ +#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT) + +/* 3. Supervisor mode not supported + * CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode) + */ + +#undef CP0_STATUS_KSU_SHIFT +#undef CP0_STATUS_KSU_MASK +#undef CP0_STATUS_KSU_KERNEL +#undef CP0_STATUS_KSU_SUPER +#undef CP0_STATUS_KSU_USER + +/* Register Number: 12 Sel: 1 Name: IntCtl */ + +#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */ +#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT) + +/* Register Number: 12 Sel: 2 Name: SRSCtl */ + +#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */ +#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT) +#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */ +#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT) +#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */ +#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT) +#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */ +#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT) +#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */ +#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT) +# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */ +# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */ +# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */ + +/* Register Number: 12 Sel: 3 Name: SRSMap */ + +#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */ +#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT) +#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */ +#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT) +#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */ +#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT) +#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */ +#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT) +#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */ +#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT) +#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */ +#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT) +#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */ +#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT) +#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */ +#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT) + +/* Register Number: 13 Sel: 0 Name: Cause + * Function: Cause of last general exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * NOTES: The following bits are added in the PIC32: + */ + +#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */ +#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */ +#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *. + +/* Register Number: 14 Sel: 0 Name: EPC + * Function: Program counter at last exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 15 Sel: 0 Name: PRId + * Function: Processor identification and revision + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * NOTE: Slightly different bit interpretations of some fields: + */ + +#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */ +#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT) +#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */ +#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT) +#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */ +#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT) + +#undef CP0_PRID_OPTIONS_SHIFT +#undef CP0_PRID_OPTIONS_MASK + +/* Register Number: 15 Sel: 1 Name: EBASE */ + +#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */ +#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT) +#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */ +#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT) + +/* Register Number: 16 Sel: 0 Name: Config + * Function: Configuration register + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * 1. PIC32MZ is always little-endian. + * 2. Implementation specific bits defined. + */ + +#undef CP0_CONFIG_IMPL_SHIFT +#undef CP0_CONFIG_IMPL_MASK + +#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */ +#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT) +#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */ +#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT) +#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */ +#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */ +#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */ +#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */ + +/* Register Number: 16 Sel: 1 Name: Config1 + * Function: Configuration register 1 + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 16 Sel: 2 Name: Config2 + * Function: Configuration register 2 + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +#undef CP0_CONFIG2_TBS_SHIFT +#undef CP0_CONFIG2_TBS_MASK + +/* Register Number: 16 Sel: 3 Name: Config3 + * Function: Configuration register 3 + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */ +#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */ +#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */ + +/* Register Number: 17-22 Reserved + * Compliance Level: Optional. + */ + +/* Register Number: 23 Sel: 0 Name: Debug + * Function: EJTAG Debug register + * Compliance Level: Optional. + */ + +#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */ +#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */ +#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */ +#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */ +#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */ +#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */ +#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */ +#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */ +#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */ +#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT) +#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */ +#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT) +#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */ +#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */ +#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */ +#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */ +#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */ +#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */ +#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */ +#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */ +#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */ +#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */ +#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */ +#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */ +#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */ +#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */ + +/* Register Number: 23 Sel: ? Name: Debug2 + * Is this documented anywhere? + */ + +/* Register Number: 24 Sel: 0 Name: DEPC + * Function: Program counter at last EJTAG debug exception + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 25-29 Reserved + * Compliance Level: Recommended/Optional. + * + * Register Number: 30 Sel: 0 Name: ErrorEPC + * Function: Program counter at last error + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 31 Sel: 0 Name: DeSAVE + * Function: EJTAG debug exception save register + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H */ diff --git a/arch/mips/include/pic32mz/irq.h b/arch/mips/include/pic32mz/irq.h new file mode 100644 index 0000000000..b7f14c756f --- /dev/null +++ b/arch/mips/include/pic32mz/irq.h @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/irq.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2) +# include +#else +# error "Unknown PIC32MZ family +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cp0_getintctl + * + * Description: + * Get the CP0 IntCtl register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t cp0_getintctl(void) +{ + register uint32_t intctl; + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t mfc0 %0, $12, 1\n" /* Get CP0 IntCtl register */ + "\t.set pop\n" + : "=r" (intctl) + : + : "memory" + ); + + return intctl; +} + +/**************************************************************************** + * Name: cp0_putintctl + * + * Description: + * Write the CP0 IntCtl register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp0_putintctl(uint32_t intctl) +{ + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t.set noreorder\n" + "\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */ + "\t.set pop\n" + : + : "r" (intctl) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp0_getebase + * + * Description: + * Get the CP0 EBASE register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t cp0_getebase(void) +{ + register uint32_t ebase; + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t mfc0 %0, $15, 1\n" /* Get CP0 EBASE register */ + "\t.set pop\n" + : "=r" (ebase) + : + : "memory" + ); + + return ebase; +} + +/**************************************************************************** + * Name: cp0_putebase + * + * Description: + * Write the CP0 EBASE register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp0_putebase(uint32_t ebase) +{ + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t.set noreorder\n" + "\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */ + "\t.set pop\n" + : + : "r" (ebase) + : "memory" + ); +} + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_H */ + diff --git a/arch/mips/include/pic32mz/irq_pic32mzxxxec.h b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h new file mode 100644 index 0000000000..31127b31e8 --- /dev/null +++ b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h @@ -0,0 +1,283 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/irq_pic32mzxxxec.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEC_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt vector numbers. These should be used to attach to interrupts + * and to change interrupt priorities. + */ + +#define PIC32MZ_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */ +#define PIC32MZ_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */ +#define PIC32MZ_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */ +#define PIC32MZ_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */ +#define PIC32MZ_IRQ_T1 4 /* Vector: 4, Timer 1 */ +#define PIC32MZ_IRQ_ICE1 5 /* Vector: 5, Input Capture 1 Error */ +#define PIC32MZ_IRQ_IC1 6 /* Vector: 6, Input Capture 1 */ +#define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */ +#define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */ +#define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */ +#define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */ +#define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */ +#define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */ +#define PIC32MZ_IRQ_INT2 13 /* Vector: 13, External Interrupt 2 */ +#define PIC32MZ_IRQ_T3 14 /* Vector: 14, Timer 3 */ +#define PIC32MZ_IRQ_ICE3 15 /* Vector: 15, Input Capture 3 Error */ +#define PIC32MZ_IRQ_IC3 16 /* Vector: 16, Input Capture 3 */ +#define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */ +#define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */ +#define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */ +#define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */ +#define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */ +#define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */ +#define PIC32MZ_IRQ_INT4 23 /* Vector: 23, External Interrupt 4 */ +#define PIC32MZ_IRQ_T5 24 /* Vector: 24, Timer 5 */ +#define PIC32MZ_IRQ_ICE5 25 /* Vector: 25, Input Capture 5 Error */ +#define PIC32MZ_IRQ_IC5 26 /* Vector: 26, Input Capture 5 */ +#define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */ +#define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */ +#define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */ +#define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */ +#define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */ +#define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */ +#define PIC32MZ_IRQ_ICE7 33 /* Vector: 33, Input Capture 7 Error */ +#define PIC32MZ_IRQ_IC7 34 /* Vector: 34, Input Capture 7 */ +#define PIC32MZ_IRQ_OC7 35 /* Vector: 35, Output Compare 7 */ +#define PIC32MZ_IRQ_T8 36 /* Vector: 36, Timer 8 */ +#define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */ +#define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */ +#define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */ +#define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */ +#define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */ +#define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */ +#define PIC32MZ_IRQ_OC9 43 /* Vector: 43, Output Compare 9 */ +#define PIC32MZ_IRQ_AD1 44 /* Vector: 44, ADC1 Global Interrupt */ + /* Vector: 45, Reserved */ +#define PIC32MZ_IRQ_AD1CMP1 46 /* Vector: 46, ADC1 Digital Comparator 1 */ +#define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */ +#define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */ +#define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */ +#define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */ +#define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */ +#define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */ +#define PIC32MZ_IRQ_AD1FLT2 53 /* Vector: 53, ADC1 Digital Filter 2 */ +#define PIC32MZ_IRQ_AD1FLT3 54 /* Vector: 54, ADC1 Digital Filter 3 */ +#define PIC32MZ_IRQ_AD1FLT4 55 /* Vector: 55, ADC1 Digital Filter 4 */ +#define PIC32MZ_IRQ_AD1FLT5 56 /* Vector: 56, ADC1 Digital Filter 5 */ +#define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */ + /* Vector: 58, Reserved */ +#define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */ +#define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */ +#define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */ +#define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */ +#define PIC32MZ_IRQ_AD1DAT4 63 /* Vector: 63, ADC1 Data 4 */ +#define PIC32MZ_IRQ_AD1DAT5 64 /* Vector: 64, ADC1 Data 5 */ +#define PIC32MZ_IRQ_AD1DAT6 65 /* Vector: 65, ADC1 Data 6 */ +#define PIC32MZ_IRQ_AD1DAT7 66 /* Vector: 66, ADC1 Data 7 */ +#define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */ +#define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */ +#define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */ +#define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */ +#define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */ +#define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */ +#define PIC32MZ_IRQ_AD1DAT14 73 /* Vector: 73, ADC1 Data 14 */ +#define PIC32MZ_IRQ_AD1DAT15 74 /* Vector: 74, ADC1 Data 15 */ +#define PIC32MZ_IRQ_AD1DAT16 75 /* Vector: 75, ADC1 Data 16 */ +#define PIC32MZ_IRQ_AD1DAT17 76 /* Vector: 76, ADC1 Data 17 */ +#define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */ +#define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */ +#define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */ +#define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */ +#define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */ +#define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */ +#define PIC32MZ_IRQ_AD1DAT24 83 /* Vector: 83, ADC1 Data 24 */ +#define PIC32MZ_IRQ_AD1DAT25 84 /* Vector: 84, ADC1 Data 25 */ +#define PIC32MZ_IRQ_AD1DAT26 85 /* Vector: 85, ADC1 Data 26 */ +#define PIC32MZ_IRQ_AD1DAT27 86 /* Vector: 86, ADC1 Data 27 */ +#define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */ +#define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */ +#define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */ +#define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */ +#define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */ +#define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */ +#define PIC32MZ_IRQ_AD1DAT34 93 /* Vector: 93, ADC1 Data 34 */ +#define PIC32MZ_IRQ_AD1DAT35 94 /* Vector: 94, ADC1 Data 35 */ +#define PIC32MZ_IRQ_AD1DAT36 95 /* Vector: 95, ADC1 Data 36 */ +#define PIC32MZ_IRQ_AD1DAT37 96 /* Vector: 96, ADC1 Data 37 */ +#define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */ +#define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */ +#define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */ +#define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */ +#define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */ +#define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */ +#define PIC32MZ_IRQ_AD1DAT44 103 /* Vector: 103, ADC1 Data 44 */ +#define PIC32MZ_IRQ_COREPERF 104 /* Vector: 104, Core Performance Counter Interrupt */ +#define PIC32MZ_IRQ_COREFDBG 105 /* Vector: 105, Core Fast Debug Channel Interrupt */ +#define PIC32MZ_IRQ_BUSPROT 106 /* Vector: 106, System Bus Protection Violation */ +#define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */ + /* Vector: 108, Reserved */ +#define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */ +#define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */ +#define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */ +#define PIC32MZ_IRQ_UART1F 112 /* Vector: 112, UART1 Fault */ +#define PIC32MZ_IRQ_UART1RX 113 /* Vector: 113, UART1 Receive Done */ +#define PIC32MZ_IRQ_UART1TX 114 /* Vector: 114, UART1 Transfer Done */ +#define PIC32MZ_IRQ_I2C1COL 115 /* Vector: 115, I2C1 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C1S 116 /* Vector: 116, I2C1 Slave Event */ +#define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */ +#define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTF 123 /* Vector: 123, PORTF Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTG 124 /* Vector: 124, PORTG Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTH 125 /* Vector: 125, PORTH Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTJ 126 /* Vector: 126, PORTJ Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */ +#define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */ +#define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */ +#define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */ +#define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */ +#define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */ +#define PIC32MZ_IRQ_USBDMA 133 /* Vector: 133, USB DMA Event */ +#define PIC32MZ_IRQ_DMA0 134 /* Vector: 134, DMA Channel 0 */ +#define PIC32MZ_IRQ_DMA1 135 /* Vector: 135, DMA Channel 1 */ +#define PIC32MZ_IRQ_DMA2 136 /* Vector: 136, DMA Channel 2 */ +#define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */ +#define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */ +#define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */ +#define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */ +#define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */ +#define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */ +#define PIC32MZ_IRQ_SPI2RX 143 /* Vector: 143, SPI2 Receive Done */ +#define PIC32MZ_IRQ_SPI2TX 144 /* Vector: 144, SPI2 Transfer Done */ +#define PIC32MZ_IRQ_UART2F 145 /* Vector: 145, UART2 Fault */ +#define PIC32MZ_IRQ_UART2RX 146 /* Vector: 146, UART2 Receive Done */ +#define PIC32MZ_IRQ_UART2TX 147 /* Vector: 147, UART2 Transfer Done */ +#define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */ +#define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */ +#define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */ +#define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */ +#define PIC32MZ_IRQ_ETH 153 /* Vector: 153, Ethernet interrupt */ +#define PIC32MZ_IRQ_SPI3F 154 /* Vector: 154, SPI3 Fault */ +#define PIC32MZ_IRQ_SPI3RX 155 /* Vector: 155, SPI3 Receive Done */ +#define PIC32MZ_IRQ_SPI3TX 156 /* Vector: 156, SPI3 Transfer Done */ +#define PIC32MZ_IRQ_UART3F 157 /* Vector: 157, UART3 Fault */ +#define PIC32MZ_IRQ_UART3RX 158 /* Vector: 158, UART3 Receive Done */ +#define PIC32MZ_IRQ_UART3TX 159 /* Vector: 159, UART3 Transfer Done */ +#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */ +#define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */ +#define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */ +#define PIC32MZ_IRQ_SPI4RX 164 /* Vector: 164, SPI4 Receive Done */ +#define PIC32MZ_IRQ_SPI4TX 165 /* Vector: 165, SPI4 Transfer Done */ +#define PIC32MZ_IRQ_RTCC 166 /* Vector: 166, Real-Time Clock and Calendar */ +#define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */ +#define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */ +#define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */ +#define PIC32MZ_IRQ_UART4F 170 /* Vector: 170, UART4 Fault */ +#define PIC32MZ_IRQ_UART4RX 171 /* Vector: 171, UART4 Receive Done */ +#define PIC32MZ_IRQ_UART4TX 172 /* Vector: 172, UART4 Transfer Done */ +#define PIC32MZ_IRQ_I2C4COL 173 /* Vector: 173, I2C4 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C4S 174 /* Vector: 174, I2C4 Slave Event */ +#define PIC32MZ_IRQ_I2C4M 175 /* Vector: 175, I2C4 Master Event */ +#define PIC32MZ_IRQ_SPI5F 176 /* Vector: 176, SPI5 Fault */ +#define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */ +#define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */ +#define PIC32MZ_IRQ_UART5F 179 /* Vector: 179, UART5 Fault */ +#define PIC32MZ_IRQ_UART5RX 180 /* Vector: 180, UART5 Receive Done */ +#define PIC32MZ_IRQ_UART5TX 181 /* Vector: 181, UART5 Transfer Done */ +#define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C5S 183 /* Vector: 183, I2C5 Slave Event */ +#define PIC32MZ_IRQ_I2C5M 184 /* Vector: 184, I2C5 Master Event */ +#define PIC32MZ_IRQ_SPI6F 185 /* Vector: 185, SPI6 Fault */ +#define PIC32MZ_IRQ_SPI6RX 186 /* Vector: 186, SPI6 Receive Done */ +#define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */ +#define PIC32MZ_IRQ_UART6F 188 /* Vector: 188, UART6 Fault */ +#define PIC32MZ_IRQ_UART6RX 189 /* Vector: 189, UART6 Receive Done */ +#define PIC32MZ_IRQ_UART6TX 190 /* Vector: 190, UART6 Transfer Done */ + +#define PIC32MZ_IRQ_BAD 191 /* Not a real IRQ number */ +#define NR_IRQS 191 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEC_H */ + diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig new file mode 100644 index 0000000000..a89bb71cb1 --- /dev/null +++ b/arch/mips/src/pic32mz/Kconfig @@ -0,0 +1,740 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_CHIP_PIC32MZ +comment "PIC32MZ Configuration Options" + +choice + prompt "PIC32MZ chip selection" + default ARCH_CHIP_PIC32MZ460F512L + +config ARCH_CHIP_PIC32MZ2048ECH + bool "PIC32MZ2048ECH" + select ARCH_CHIP_PIC32MZEC + ---help--- + Microchip PIC32MZ2048ECH (MIPS32) + ARCH_CHIP_PIC32MZ1 + +config ARCH_CHIP_PIC32MZ2048ECM + bool "PIC32MZ2048ECH" + select ARCH_CHIP_PIC32MZEC + ---help--- + Microchip PIC32MZ2048ECH (MIPS32) + +endchoice + +config ARCH_CHIP_PIC32MZEC + bool + default n + +config PIC32MZ_MVEC + bool + default n + +config PIC32MZ_T1 + bool + default y + +menu "PIC32MZ Peripheral Support" + +config PIC32MZ_WDT + bool "Watchdog timer (WDT)" + default n + +config PIC32MZ_T2 + bool "Timer 2 (T2)" + default n + +config PIC32MZ_T3 + bool "Timer 3 (T3)" + default n + +config PIC32MZ_T4 + bool "Timer 4 (T4)" + default n + +config PIC32MZ_T5 + bool "Timer 5 (T5)" + default n + +config PIC32MZ_IC1 + bool "Input Capture 1 (IC1)" + default n + +config PIC32MZ_IC2 + bool "Input Capture 2 (IC2)" + default n + +config PIC32MZ_IC3 + bool "Input Capture 3 (IC3)" + default n + +config PIC32MZ_IC4 + bool "Input Capture 4 (IC4)" + default n + +config PIC32MZ_IC5 + bool "Input Capture 5 (IC5)" + default n + +config PIC32MZ_OC1 + bool "Output Compare 1 (OC1)" + default n + +config PIC32MZ_OC2 + bool "Output Compare 2 (OC2)" + default n + +config PIC32MZ_OC3 + bool "Output Compare 3 (OC3)" + default n + +config PIC32MZ_OC4 + bool "Output Compare 4 (OC4)" + default n + +config PIC32MZ_OC5 + bool "Output Compare 5 (OC5)" + default n + +config PIC32MZ_I2C1 + bool "I2C1" + default n + +config PIC32MZ_I2C2 + bool "I2C2" + default n + +config PIC32MZ_I2C3 + bool "I2C3" + default n + +config PIC32MZ_I2C4 + bool "I2C4" + default n + +config PIC32MZ_I2C5 + bool "I2C5" + default n + +config PIC32MZ_SPI1 + bool "SPI1" + default n + +config PIC32MZ_SPI2 + bool "SPI2" + default n + +config PIC32MZ_SPI3 + bool "SPI3" + default n + +config PIC32MZ_SPI4 + bool "SPI4" + default n + +config PIC32MZ_UART1 + bool "UART1" + default n + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_UART2 + bool "UART2" + default n + select ARCH_HAVE_UART2 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_UART3 + bool "UART3" + default n + select ARCH_HAVE_UART3 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_UART4 + bool "UART4" + default n + select ARCH_HAVE_UART4 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_UART5 + bool "UART5" + default n + select ARCH_HAVE_UART5 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_UART6 + bool "UART6" + default n + select ARCH_HAVE_UART6 + select ARCH_HAVE_SERIAL_TERMIOS + +config PIC32MZ_ADC + bool "ADC1" + default n + +config PIC32MZ_PMP + bool "Parallel Master Port (PMP)" + default n + +config PIC32MZ_CM1 + bool "Comparator 1 (CM1)" + default n + +config PIC32MZ_CM2 + bool "Comparator 2 (CM2)" + default n + +config PIC32MZ_CM3 + bool "Comparator 3 (CM3)" + default n + +config PIC32MZ_RTCC + bool "Real-Time Clock and Calendar (RTCC)" + default n + +config PIC32MZ_DMA + bool "DMA" + default n + select ARCH_DMA + +config PIC32MZ_FLASH + bool "FLASH" + default n + +config PIC32MZ_USBDEV + bool "USB device" + default n + +config PIC32MZ_USBHOST + bool "USB host" + default n + +config PIC32MZ_CAN1 + bool "Controller area network 1 (CAN1)" + default n + +config PIC32MZ_CAN2 + bool "Controller area network 2 (CAN2)" + default n + +config PIC32MZ_ETHERNET + bool "Ethernet" + default n + select NETDEVICES + select ARCH_HAVE_PHY + +config PIC32MZ_CTMU + bool "Charge Time Measurement Unit (CMTU)" + default n + +endmenu + +menu "PIC32MZ Peripheral Interrupt Priorities" + +config PIC32MZ_CTPRIO + int "Core Timer Interrupt (CT)" + default 16 + ---help--- + Core Timer Interrupt. Range 4-31, Default 16. + +config PIC32MZ_CS0PRIO + int "Core Software Interrupt 0 (CS0)" + default 16 + ---help--- + Core Software Interrupt 0. Range 4-31, Default 16. + +config PIC32MZ_CS1PRIO + int "Core Software Interrupt 1 (CS1)" + default 16 + ---help--- + Core Software Interrupt 1. Range 4-31, Default 16. + +config PIC32MZ_INT0PRIO + int "External Interrupt 0 (INT0)" + default 16 + ---help--- + External Interrupt 0. Range 4-31, Default 16. + +config PIC32MZ_INT1PRIO + int "External Interrupt 1 (INT1)" + default 16 + ---help--- + External Interrupt 1. Range 4-31, Default 16. + +config PIC32MZ_INT2PRIO + int "External Interrupt 2 (INT2)" + default 16 + ---help--- + External Interrupt 2. Range 4-31, Default 16. + +config PIC32MZ_INT3PRIO + int "External Interrupt 3 (INT3)" + default 16 + ---help--- + External Interrupt 3. Range 4-31, Default 16. + +config PIC32MZ_INT4PRIO + int "External Interrupt 4 (INT4)" + default 16 + ---help--- + External Interrupt 4. Range 4-31, Default 16. + +config PIC32MZ_FSCMPRIO + int "Fail-Safe Clock Monitor (FSCM)" + default 16 + depends on PIC32MZ_ + ---help--- + Fail-Safe Clock Monitor. Range 4-31, Default 16. + +config PIC32MZ_T1PRIO + int "Timer 1 (T1)" + default 16 + ---help--- + Timer 1 (System timer) priority. Range 4-31, Default 16. + +config PIC32MZ_T2PRIO + int "Timer 2 (T2)" + default 16 + depends on PIC32MZ_T2 + ---help--- + Timer 2 priority. Range 4-31, Default 16. + +config PIC32MZ_T3PRIO + int "Timer 3 (T3)" + default 16 + depends on PIC32MZ_T3 + ---help--- + Timer 3 priority. Range 4-31, Default 16. + +config PIC32MZ_T4PRIO + int "Timer 4 (T4)" + default 16 + depends on PIC32MZ_T4 + ---help--- + Timer 4 priority. Range 4-31, Default 16. + +config PIC32MZ_T5PRIO + int "Timer 5 (T5)" + default 16 + depends on PIC32MZ_ + ---help--- + Timer 5 priority. Range 4-31, Default 16. + +config PIC32MZ_IC1PRIO + int "Input Capture 1 (IC1)" + default 16 + depends on PIC32MZ_IC1 + ---help--- + Input Capture 1. Range 4-31, Default 16. + +config PIC32MZ_IC2PRIO + int "Input Capture 2 (IC2)" + default 16 + depends on PIC32MZ_IC2 + ---help--- + Input Capture 2. Range 4-31, Default 16. + +config PIC32MZ_IC3PRIO + int "Input Capture 3 (IC3)" + default 16 + depends on PIC32MZ_IC3 + ---help--- + Input Capture 3. Range 4-31, Default 16. + +config PIC32MZ_IC4PRIO + int "Input Capture 4 (IC4)" + default 16 + depends on PIC32MZ_IC4 + ---help--- + Input Capture 4. Range 4-31, Default 16. + +config PIC32MZ_IC5PRIO + int "Input Capture 5 (IC5)" + default 16 + depends on PIC32MZ_IC5 + ---help--- + Input Capture 5. Range 4-31, Default 16. + +config PIC32MZ_OC1PRIO + int "Output Compare 1 (OC1)" + default 16 + depends on PIC32MZ_OC1 + ---help--- + Output Compare 1. Range 4-31, Default 16. + +config PIC32MZ_OC2PRIO + int "Output Compare 2 (OC2)" + default 16 + depends on PIC32MZ_OC2 + ---help--- + Output Compare 2. Range 4-31, Default 16. + +config PIC32MZ_OC3PRIO + int "Output Compare 3 (OC3)" + default 16 + depends on PIC32MZ_OC3 + ---help--- + Output Compare 3. Range 4-31, Default 16. + +config PIC32MZ_OC4PRIO + int "Output Compare 4 (OC4)" + default 16 + depends on PIC32MZ_OC4 + ---help--- + Output Compare 4. Range 4-31, Default 16. + +config PIC32MZ_OC5PRIO + int "Output Compare 5 (OC5)" + default 16 + depends on PIC32MZ_OC5 + ---help--- + Output Compare 5. Range 4-31, Default 16. + +config PIC32MZ_I2C1PRIO + int "I2C1" + default 16 + depends on PIC32MZ_I2C1 + ---help--- + I2C 1. Range 4-31, Default 16. + +config PIC32MZ_I2C2PRIO + int "I2C2" + default 16 + depends on PIC32MZ_I2C3 + ---help--- + I2C 2. Range 4-31, Default 16. + +config PIC32MZ_I2C3PRIO + int "I2C3" + default 16 + depends on PIC32MZ_I2C3 + ---help--- + I2C 3. Range 4-31, Default 16. + +config PIC32MZ_I2C4PRIO + int "I2C4" + default 16 + depends on PIC32MZ_I2C4 + ---help--- + I2C 4. Range 4-31, Default 16. + +config PIC32MZ_I2C5PRIO + int "I2C5" + default 16 + depends on PIC32MZ_I2C5 + ---help--- + I2C 5. Range 4-31, Default 16. + +config PIC32MZ_SPI1PRIO + int "SPI1" + default 16 + depends on PIC32MZ_SPI1 + ---help--- + SPI 2 + +config PIC32MZ_SPI2PRIO + int "SPI2" + default 16 + depends on PIC32MZ_SPI2 + ---help--- + SPI 2 + +config PIC32MZ_UART1PRIO + int "UART1" + default 16 + depends on PIC32MZ_UART1 + ---help--- + UART 1. Range 4-31, Default 16. + +config PIC32MZ_UART2PRIO + int "UART2" + default 16 + depends on PIC32MZ_UART2 + ---help--- + UART 2. Range 4-31, Default 16. + +config PIC32MZ_CNPRIO + int "CN" + default 16 + depends on PIC32MZ_CN + ---help--- + Input Change Interrupt. Range 4-31, Default 16. + +config PIC32MZ_ADCPRIO + int "ADC1" + default 16 + depends on PIC32MZ_ADC1 + ---help--- + ADC1 Convert Done. Range 4-31, Default 16. + +config PIC32MZ_PMPPRIO + int "Parallel Master Port (PMP)" + default 16 + depends on PIC32MZ_PMP + ---help--- + Parallel Master Port. Range 4-31, Default 16. + +config PIC32MZ_CM1PRIO + int "Comparator 1 (CM1)" + default 16 + depends on PIC32MZ_CM1 + ---help--- + Comparator 1. Range 4-31, Default 16. + +config PIC32MZ_CM2PRIO + int "Comparator 2 (CM2)" + default 16 + depends on PIC32MZ_CM2 + ---help--- + Comparator 2. Range 4-31, Default 16. + +config PIC32MZ_RTCCPRIO + int "Real-Time Clock and Calendar (RTCC)" + default 16 + depends on PIC32MZ_RTCC + ---help--- + Real-Time Clock and Calendar. Range 4-31, Default 16. + +config PIC32MZ_DMA0PRIO + int "DMA0" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 0. Range 4-31, Default 16. + +config PIC32MZ_DMA1PRIO + int "DMA1" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 1. Range 4-31, Default 16. + +config PIC32MZ_DMA2PRIO + int "DMA2" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 2. Range 4-31, Default 16. + +config PIC32MZ_DMA3PRIO + int "DMA3" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 3. Range 4-31, Default 16. + +config PIC32MZ_DMA4PRIO + int "DMA4" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 4. Range 4-31, Default 16. + +config PIC32MZ_DMA5PRIO + int "DMA5" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 5. Range 4-31, Default 16. + +config PIC32MZ_DMA6PRIO + int "DMA6" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 6. Range 4-31, Default 16. + +config PIC32MZ_DMA7PRIO + int "DMA7" + default 16 + depends on PIC32MZ_DMA + ---help--- + DMA Channel 7. Range 4-31, Default 16. + +config PIC32MZ_FCEPRIO + int "FCE" + default 16 + depends on PIC32MZ_FLASH + ---help--- + Flash Control Event. Range 4-31, Default 16. + +config PIC32MZ_USBPRIO + int "USB" + default 16 + depends on PIC32MZ_USBDEV || PIC32MZ_USBHOST + ---help--- + USB. Range 4-31, Default 16. + +endmenu + +menu "PIC32MZ PHY/Ethernet device driver settings" + depends on PIC32MZ_ETHERNET + +config PHY_AUTONEG + bool "Auto-negotion" + default y + depends on PIC32MZ_ETHERNET + ---help--- + Enable auto-negotion + +config PHY_SPEED100 + bool "100Mbps spped" + default n + depends on PIC32MZ_ETHERNET && !PHY_AUTONEG + ---help--- + Select 100Mbit vs. 10Mbit speed. + +config PHY_FDUPLEX + bool "Full duplex" + default n + depends on PIC32MZ_ETHERNET && !PHY_AUTONEG + ---help--- + Select full (vs. half) duplex + +config NET_NTXDESC + int "Number Tx descriptors" + default 2 + depends on PIC32MZ_ETHERNET + ---help--- + Configured number of Tx descriptors. Default: 2 + +config NET_NRXDESC + int "Number Rx descriptors" + default 4 + depends on PIC32MZ_ETHERNET + ---help--- + Configured number of Rx descriptors. Default: 4 + +config NET_PRIORITY + int "" + default 28 + depends on PIC32MZ_ETHERNET + ---help--- + Ethernet interrupt priority. The is default is the higest priority. + +config NET_WOL + bool "Wake-up on LAN" + default n + depends on PIC32MZ_ETHERNET + ---help--- + Enable Wake-up on LAN (not fully implemented). + +config NET_REGDEBUG + bool "Register level debug" + default n + depends on PIC32MZ_ETHERNET && DEBUG + ---help--- + Enabled low level register debug. Also needs DEBUG. + +config NET_HASH + bool "Hash" + default n + depends on PIC32MZ_ETHERNET + ---help--- + Enable receipt of near-perfect match frames. + +config NET_MULTICAST + bool "Multicast" + default y if NET_IGMP + depends on PIC32MZ_ETHERNET + ---help--- + Enable receipt of multicast (and unicast) frames. Automatically set if + NET_IGMP is selected. + +endmenu + +menu "Device Configuration 0 (DEVCFG0)" + +config PIC32MZ_DEBUGGER + int "Debugger" + default 3 + ---help--- + Background Debugger Enable. Default 3 (disabled). The value 2 enables. + +config PIC32MZ_ICESEL + int "ICE channel" + default 1 + ---help--- + In-Circuit Emulator/Debugger Communication Channel Select. Default 1 (PG2) + +config PIC32MZ_PROGFLASHWP + hex "Program FLASH write protect" + default 0x3ff if ARCH_CHIP_PIC32MZ1 || ARCH_CHIP_PIC32MZ2 + default 0xff if !ARCH_CHIP_PIC32MZ1 && !ARCH_CHIP_PIC32MZ2 + ---help--- + Program FLASH write protect. Default 0xff (disabled) + +config PIC32MZ_BOOTFLASHWP + int "Boot FLASH write protect" + default 1 + ---help--- + Default 1 (disabled) + +config PIC32MZ_CODEWP + int "Code write protect" + default 1 + ---help--- + Default 1 (disabled) + +endmenu + +menu "Device Configuration 1 (DEVCFG1)" + +config PIC32MZ_OSCOUT + int "USB ID" + default 0 + depends on ARCH_CHIP_PIC32MZ1 || ARCH_CHIP_PIC32MZ2 + ---help--- + USB USBID Selection. Default 1 if USB enabled (USBID pin is controlled by the USB + module), but 0 (GPIO) otherwise. + +endmenu + +menu "Device Configuration 3 (DEVCFG3)" + +config PIC32MZ_USBIDO + int "USB ID" + default 1 if PIC32MZ_USB + default 0 if !PIC32MZ_USB + ---help--- + USB USBID Selection. Default 1 if USB enabled (USBID pin is controlled by the USB + module), but 0 (GPIO) otherwise. + +config PIC32MZ_VBUSIO + int "USB VBUSON" + default 1 if PIC32MZ_USB + default 0 if !PIC32MZ_USB + ---help--- + USB VBUSON Selection (Default 1 if USB enabled (VBUSON pin is controlled by the USB + module, but 0 (GPIO) otherwise. + +config PIC32MZ_WDENABLE + bool "Watchdog enable" + default 0 + ---help--- + Enabled watchdog on power up. Default 0 (watchdog can be enabled later by software). + +config PIC32MZ_FETHIO + int "Ethernet I/O pins" + default 1 + ---help--- + Ethernet I/O Pin Selection bit: + + 1 = Default Ethernet I/O Pins + 0 = Alternate Ethernet I/O Pins + +config PIC32MZ_FMIIEN + int "Ethernet MII" + default 1 + ---help--- + Ethernet MII Enable bit + + 1 = MII enabled + 0 = RMII enabled + +endmenu + +endif diff --git a/configs/Kconfig b/configs/Kconfig index fa45a76ce4..542949257c 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -553,7 +553,7 @@ config ARCH_BOARD_PCDUINO_A10 but the others may be compatible. config ARCH_BOARD_PIC32MX_STARTERKIT - bool "Microchip PIC32 Ethernet Starter Kit (DM320004)" + bool "Microchip PIC32MX Ethernet Starter Kit (DM320004)" depends on ARCH_CHIP_PIC32MX795F512L select ARCH_HAVE_LEDS ---help--- @@ -569,6 +569,22 @@ config ARCH_BOARD_PIC32MX7MMB This is the port NuttX to the Mikroelektronika PIC32MX7 Multimedia Board (MMB). See http://www.mikroe.com/ for further information. +config ARCH_BOARD_PIC32MZ_STARTERKIT + bool "Microchip PIC32MZ Ethernet Starter Kit ((DM320006)" + depends on ARCH_CHIP_PIC32MZ2048ECH || ARCH_CHIP_PIC32MZ2048ECM + select ARCH_HAVE_LEDS + ---help--- + This is the port of NuttX to the Microchip PIC32MZ Embedded + Connectivity (EC) Starter Kit. There are two configurations of the + starter kit: + + 1) The PIC32MZ Embedded Connectivity Starter Kit based on the + PIC32MZ2048ECH144-I/PH chip (DM320006), and + 2) The PIC32MZ Embedded Connectivity Starter Kit based on the + PIC32MZ2048ECM144-I/PH w/Crypto Engine (DM320006-C) + + See www.microchip.com for further information. + config ARCH_BOARD_PIRELLI_DPL10 bool "Pirelli DPL10 phone" depends on ARCH_CHIP_CALYPSO @@ -1111,6 +1127,7 @@ config ARCH_BOARD default "pcduino-a10" if ARCH_BOARD_PCDUINO_A10 default "pic32mx-starterkit" if ARCH_BOARD_PIC32MX_STARTERKIT default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB + default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT default "pirelli_dpl10" if ARCH_BOARD_PIRELLI_DPL10 default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE default "qemu-i486" if ARCH_BOARD_QEMU_I486 @@ -1379,6 +1396,9 @@ endif if ARCH_BOARD_PIC32MX7MMB source "configs/pic32mx7mmb/Kconfig" endif +if ARCH_BOARD_PIC32MZ_STARTERKIT +source "configs/pic32mz-starterkit/Kconfig" +endif if ARCH_BOARD_PIRELLI_DPL10 source "configs/pirelli_dpl10/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index f43a6b8105..a7f8069fc4 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -463,6 +463,18 @@ configs/pic32mx7mmb http://www.mikroe.com/ for further information. configs/pirelli_dpl10 +configs/pic32mz-starterkit + This directory contains the port of NuttX to the Microchip PIC32MZ + Embedded Connectivity (EC) Starter Kit. There are two configurations of + the starter kit: + + 1) The PIC32MZ Embedded Connectivity Starter Kit based on the + PIC32MZ2048ECH144-I/PH chip (DM320006), and + 2) The PIC32MZ Embedded Connectivity Starter Kit based on the + PIC32MZ2048ECM144-I/PH w/Crypto Engine (DM320006-C) + + See www.microchip.com for further information. + This directory contains the board support for Pirelli "Discus" DP-L10 phones. It is a variant of the compal_e88 config with the small changes for the differences in the board. diff --git a/configs/pic32mz-starterkit/README.txt b/configs/pic32mz-starterkit/README.txt index cafec5b830..6682dea643 100644 --- a/configs/pic32mz-starterkit/README.txt +++ b/configs/pic32mz-starterkit/README.txt @@ -182,6 +182,9 @@ Where is one of the following: 2. Serial Output The OS test produces all of its test output on the serial console. - This configuration has UART1 enabled as a serial console. I have - been unable to get this UART work on the MEB. But on the Expansion - I/O board, this maps to RX = J11 pin 41 and TX = J11 pin 43 + This configuration has UART1 enabled as a serial console. + + 3. Toolchain + + By default, the Pinguino MIPs tool chain is used. This toolchain + selection can easily be changed with 'make menuconfig'. diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 16920c833d..0ea714f2c4 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -70,6 +70,7 @@ CONFIG_ARCH_MIPS=y CONFIG_ARCH="mips" CONFIG_ARCH_FAMILY="mips32" CONFIG_ARCH_CHIP="pic32mz" +# CONFIG_ARCH_CHIP_PIC32MX is not set CONFIG_ARCH_CHIP_PIC32MZ=y CONFIG_ARCH_MIPS32=y @@ -78,162 +79,89 @@ CONFIG_ARCH_MIPS32=y # # CONFIG_MIPS32_TOOLCHAIN_GNU_ELF is not set # CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW is not set -CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE=y -# CONFIG_MIPS32_TOOLCHAIN_PINGUINOW is not set +# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE is not set +CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y # CONFIG_MIPS32_FRAMEPOINTER is not set # -# PIC32MX Configuration Options +# PIC32MZ Configuration Options # -# CONFIG_ARCH_CHIP_PIC32MX110F016B is not set -# CONFIG_ARCH_CHIP_PIC32MX110F016C is not set -# CONFIG_ARCH_CHIP_PIC32MX110F016D is not set -# CONFIG_ARCH_CHIP_PIC32MX120F032B is not set -# CONFIG_ARCH_CHIP_PIC32MX120F032C is not set -# CONFIG_ARCH_CHIP_PIC32MX120F032D is not set -# CONFIG_ARCH_CHIP_PIC32MX130F064B is not set -# CONFIG_ARCH_CHIP_PIC32MX130F064C is not set -# CONFIG_ARCH_CHIP_PIC32MX130F064D is not set -# CONFIG_ARCH_CHIP_PIC32MX150F128B is not set -# CONFIG_ARCH_CHIP_PIC32MX150F128C is not set -# CONFIG_ARCH_CHIP_PIC32MX150F128D is not set -# CONFIG_ARCH_CHIP_PIC32MX210F016B is not set -# CONFIG_ARCH_CHIP_PIC32MX210F016C is not set -# CONFIG_ARCH_CHIP_PIC32MX210F016D is not set -# CONFIG_ARCH_CHIP_PIC32MX220F032B is not set -# CONFIG_ARCH_CHIP_PIC32MX220F032C is not set -# CONFIG_ARCH_CHIP_PIC32MX220F032D is not set -# CONFIG_ARCH_CHIP_PIC32MX230F064B is not set -# CONFIG_ARCH_CHIP_PIC32MX230F064C is not set -# CONFIG_ARCH_CHIP_PIC32MX230F064D is not set -# CONFIG_ARCH_CHIP_PIC32MX250F128B is not set -# CONFIG_ARCH_CHIP_PIC32MX250F128C is not set -# CONFIG_ARCH_CHIP_PIC32MX250F128D is not set -# CONFIG_ARCH_CHIP_PIC32MX320F032H is not set -# CONFIG_ARCH_CHIP_PIC32MX320F064H is not set -# CONFIG_ARCH_CHIP_PIC32MX320F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX320F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX340F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX340F256H is not set -# CONFIG_ARCH_CHIP_PIC32MX340F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX340F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX360F256L is not set -# CONFIG_ARCH_CHIP_PIC32MX360F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX420F032H is not set -# CONFIG_ARCH_CHIP_PIC32MX440F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX440F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX440F256H is not set -# CONFIG_ARCH_CHIP_PIC32MX440F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX460F256L is not set -# CONFIG_ARCH_CHIP_PIC32MX460F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX534F064H is not set -# CONFIG_ARCH_CHIP_PIC32MX534F064L is not set -# CONFIG_ARCH_CHIP_PIC32MX564F064H is not set -# CONFIG_ARCH_CHIP_PIC32MX564F064L is not set -# CONFIG_ARCH_CHIP_PIC32MX564F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX564F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX575F256H is not set -# CONFIG_ARCH_CHIP_PIC32MX575F256L is not set -# CONFIG_ARCH_CHIP_PIC32MX575F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX575F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX664F064H is not set -# CONFIG_ARCH_CHIP_PIC32MX664F064L is not set -# CONFIG_ARCH_CHIP_PIC32MX664F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX664F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX675F256H is not set -# CONFIG_ARCH_CHIP_PIC32MX675F256L is not set -# CONFIG_ARCH_CHIP_PIC32MX675F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX675F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX695F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX695F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX764F128H is not set -# CONFIG_ARCH_CHIP_PIC32MX764F128L is not set -# CONFIG_ARCH_CHIP_PIC32MX775F256H is not set -# CONFIG_ARCH_CHIP_PIC32MX775F256L is not set -# CONFIG_ARCH_CHIP_PIC32MX775F512H is not set -# CONFIG_ARCH_CHIP_PIC32MX775F512L is not set -# CONFIG_ARCH_CHIP_PIC32MX795F512H is not set -CONFIG_ARCH_CHIP_PIC32MX795F512L=y -# CONFIG_ARCH_CHIP_PIC32MX1 is not set -# CONFIG_ARCH_CHIP_PIC32MX2 is not set -# CONFIG_ARCH_CHIP_PIC32MX3 is not set -# CONFIG_ARCH_CHIP_PIC32MX4 is not set -# CONFIG_ARCH_CHIP_PIC32MX5 is not set -# CONFIG_ARCH_CHIP_PIC32MX6 is not set -CONFIG_ARCH_CHIP_PIC32MX7=y -# CONFIG_PIC32MX_MVEC is not set -CONFIG_PIC32MX_T1=y +# CONFIG_ARCH_CHIP_PIC32MZ2048ECH is not set +CONFIG_ARCH_CHIP_PIC32MZ2048ECM=y +CONFIG_ARCH_CHIP_PIC32MZEC=y +# CONFIG_PIC32MZ_MVEC is not set +CONFIG_PIC32MZ_T1=y # -# PIC32MX Peripheral Support +# PIC32MZ Peripheral Support # -# CONFIG_PIC32MX_WDT is not set -# CONFIG_PIC32MX_T2 is not set -# CONFIG_PIC32MX_T3 is not set -# CONFIG_PIC32MX_T4 is not set -# CONFIG_PIC32MX_T5 is not set -# CONFIG_PIC32MX_IC1 is not set -# CONFIG_PIC32MX_IC2 is not set -# CONFIG_PIC32MX_IC3 is not set -# CONFIG_PIC32MX_IC4 is not set -# CONFIG_PIC32MX_IC5 is not set -# CONFIG_PIC32MX_OC1 is not set -# CONFIG_PIC32MX_OC2 is not set -# CONFIG_PIC32MX_OC3 is not set -# CONFIG_PIC32MX_OC4 is not set -# CONFIG_PIC32MX_OC5 is not set -# CONFIG_PIC32MX_I2C1 is not set -# CONFIG_PIC32MX_I2C2 is not set -# CONFIG_PIC32MX_I2C3 is not set -# CONFIG_PIC32MX_I2C4 is not set -# CONFIG_PIC32MX_I2C5 is not set -# CONFIG_PIC32MX_SPI1 is not set -# CONFIG_PIC32MX_SPI2 is not set -# CONFIG_PIC32MX_SPI3 is not set -# CONFIG_PIC32MX_SPI4 is not set -CONFIG_PIC32MX_UART1=y -# CONFIG_PIC32MX_UART2 is not set -# CONFIG_PIC32MX_UART3 is not set -# CONFIG_PIC32MX_UART4 is not set -# CONFIG_PIC32MX_UART5 is not set -# CONFIG_PIC32MX_UART6 is not set -# CONFIG_PIC32MX_ADC is not set -# CONFIG_PIC32MX_PMP is not set -# CONFIG_PIC32MX_CM1 is not set -# CONFIG_PIC32MX_CM2 is not set -# CONFIG_PIC32MX_CM3 is not set -# CONFIG_PIC32MX_RTCC is not set -# CONFIG_PIC32MX_DMA is not set -# CONFIG_PIC32MX_FLASH is not set -# CONFIG_PIC32MX_USBDEV is not set -# CONFIG_PIC32MX_USBHOST is not set -# CONFIG_PIC32MX_CAN1 is not set -# CONFIG_PIC32MX_CAN2 is not set -# CONFIG_PIC32MX_ETHERNET is not set -# CONFIG_PIC32MX_CTMU is not set +# CONFIG_PIC32MZ_WDT is not set +# CONFIG_PIC32MZ_T2 is not set +# CONFIG_PIC32MZ_T3 is not set +# CONFIG_PIC32MZ_T4 is not set +# CONFIG_PIC32MZ_T5 is not set +# CONFIG_PIC32MZ_IC1 is not set +# CONFIG_PIC32MZ_IC2 is not set +# CONFIG_PIC32MZ_IC3 is not set +# CONFIG_PIC32MZ_IC4 is not set +# CONFIG_PIC32MZ_IC5 is not set +# CONFIG_PIC32MZ_OC1 is not set +# CONFIG_PIC32MZ_OC2 is not set +# CONFIG_PIC32MZ_OC3 is not set +# CONFIG_PIC32MZ_OC4 is not set +# CONFIG_PIC32MZ_OC5 is not set +# CONFIG_PIC32MZ_I2C1 is not set +# CONFIG_PIC32MZ_I2C2 is not set +# CONFIG_PIC32MZ_I2C3 is not set +# CONFIG_PIC32MZ_I2C4 is not set +# CONFIG_PIC32MZ_I2C5 is not set +# CONFIG_PIC32MZ_SPI1 is not set +# CONFIG_PIC32MZ_SPI2 is not set +# CONFIG_PIC32MZ_SPI3 is not set +# CONFIG_PIC32MZ_SPI4 is not set +CONFIG_PIC32MZ_UART1=y +# CONFIG_PIC32MZ_UART2 is not set +# CONFIG_PIC32MZ_UART3 is not set +# CONFIG_PIC32MZ_UART4 is not set +# CONFIG_PIC32MZ_UART5 is not set +# CONFIG_PIC32MZ_UART6 is not set +# CONFIG_PIC32MZ_ADC is not set +# CONFIG_PIC32MZ_PMP is not set +# CONFIG_PIC32MZ_CM1 is not set +# CONFIG_PIC32MZ_CM2 is not set +# CONFIG_PIC32MZ_CM3 is not set +# CONFIG_PIC32MZ_RTCC is not set +# CONFIG_PIC32MZ_DMA is not set +# CONFIG_PIC32MZ_FLASH is not set +# CONFIG_PIC32MZ_USBDEV is not set +# CONFIG_PIC32MZ_USBHOST is not set +# CONFIG_PIC32MZ_CAN1 is not set +# CONFIG_PIC32MZ_CAN2 is not set +# CONFIG_PIC32MZ_ETHERNET is not set +# CONFIG_PIC32MZ_CTMU is not set # -# PIC32MX Peripheral Interrupt Priorities +# PIC32MZ Peripheral Interrupt Priorities # -CONFIG_PIC32MX_CTPRIO=16 -CONFIG_PIC32MX_CS0PRIO=16 -CONFIG_PIC32MX_CS1PRIO=16 -CONFIG_PIC32MX_INT0PRIO=16 -CONFIG_PIC32MX_INT1PRIO=16 -CONFIG_PIC32MX_INT2PRIO=16 -CONFIG_PIC32MX_INT3PRIO=16 -CONFIG_PIC32MX_INT4PRIO=16 -CONFIG_PIC32MX_T1PRIO=16 -CONFIG_PIC32MX_UART1PRIO=16 +CONFIG_PIC32MZ_CTPRIO=16 +CONFIG_PIC32MZ_CS0PRIO=16 +CONFIG_PIC32MZ_CS1PRIO=16 +CONFIG_PIC32MZ_INT0PRIO=16 +CONFIG_PIC32MZ_INT1PRIO=16 +CONFIG_PIC32MZ_INT2PRIO=16 +CONFIG_PIC32MZ_INT3PRIO=16 +CONFIG_PIC32MZ_INT4PRIO=16 +CONFIG_PIC32MZ_T1PRIO=16 +CONFIG_PIC32MZ_UART1PRIO=16 # # Device Configuration 0 (DEVCFG0) # -CONFIG_PIC32MX_DEBUGGER=2 -CONFIG_PIC32MX_ICESEL=1 -CONFIG_PIC32MX_PROGFLASHWP=0xff -CONFIG_PIC32MX_BOOTFLASHWP=1 -CONFIG_PIC32MX_CODEWP=1 +CONFIG_PIC32MZ_DEBUGGER=2 +CONFIG_PIC32MZ_ICESEL=1 +CONFIG_PIC32MZ_PROGFLASHWP=0xff +CONFIG_PIC32MZ_BOOTFLASHWP=1 +CONFIG_PIC32MZ_CODEWP=1 # # Device Configuration 1 (DEVCFG1) @@ -242,11 +170,11 @@ CONFIG_PIC32MX_CODEWP=1 # # Device Configuration 3 (DEVCFG3) # -CONFIG_PIC32MX_USBIDO=0 -CONFIG_PIC32MX_VBUSIO=0 -# CONFIG_PIC32MX_WDENABLE is not set -CONFIG_PIC32MX_FETHIO=0 -CONFIG_PIC32MX_FMIIEN=0 +CONFIG_PIC32MZ_USBIDO=0 +CONFIG_PIC32MZ_VBUSIO=0 +# CONFIG_PIC32MZ_WDENABLE is not set +CONFIG_PIC32MZ_FETHIO=0 +CONFIG_PIC32MZ_FMIIEN=0 # # Architecture Options @@ -305,7 +233,6 @@ CONFIG_RAM_SIZE=131072 # Board Selection # CONFIG_ARCH_BOARD_PIC32MZ_STARTERKIT=y -# CONFIG_ARCH_BOARD_PIC32MX7MMB is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="pic32mz-starterkit"