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Add a hello world configuration to help with the SAMA5 bringup

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This commit is contained in:
Gregory Nutt 2013-07-26 15:28:01 -06:00
parent 2f772c84fd
commit 14093ef76a
7 changed files with 52 additions and 13 deletions
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7
arch/arm/src/armv7-a/arm_head.S
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@ -382,8 +382,13 @@ __start:
mcr CP15_TTBR0(r4)
mcr CP15_TTBR1(r4)
/* Clear the TTB control register (TTBCR) to indicate that we are using
/* Set the TTB control register (TTBCR) to indicate that we are using
* TTBR0. r0 still holds the value of zero.
*
* N : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
* PD0 : 0=Perform translation table walks using TTBR0
* PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
* EAE : 0=Use 32-bit translation system
*/
mcr CP15_TTBCR(r0)

1
arch/arm/src/armv7-a/arm_saveusercontext.S
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@ -139,3 +139,4 @@ up_saveusercontext:
mov r0, #0 /* Return value == 0 */
mov pc, lr /* Return */
.size up_saveusercontext, . - up_saveusercontext
.end

8
arch/arm/src/armv7-a/arm_vectors.S
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@ -43,12 +43,14 @@
#include "arm.h"
#include "cp15.h"
.file "arm_vectors.S"
/************************************************************************************
* Definitions
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Global Data
* Private Data
************************************************************************************/
.data
@ -76,8 +78,6 @@ g_aborttmp:
* Public Functions
************************************************************************************/
.text
/************************************************************************************
* Name: arm_vectorirq
*

10
arch/arm/src/armv7-a/arm_vectortab.S
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@ -39,14 +39,19 @@
#include <nuttx/config.h>
.file "arm_vectortab.S"
/****************************************************************************
* Definitions
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Global Data
* Global Symbols
****************************************************************************/
.globl _vector_start
.globl _vector_end
/****************************************************************************
* Assembly Macros
****************************************************************************/
@ -101,4 +106,5 @@ _vector_start:
.globl _vector_end
_vector_end:
.size _vector_start, . - _vector_start
.end

2
arch/arm/src/armv7-a/mmu.h
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@ -401,7 +401,7 @@
/* Bit 2: Bufferable bit */
/* Bit 3: Cacheable bit */
/* Bits 4-5: Access Permissions bits AP[0:1] */
#define PTE_SMALL_AP_MASK (0xfffff000) /* Bits 12-31: Small page base address, PA[31:12] */
#define PTE_SMALL_PADDR_MASK (0xfffff000) /* Bits 12-31: Small page base address, PA[31:12] */
/* Level 2 Translation Table Access Permissions:
*

20
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
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@ -264,6 +264,12 @@
#ifndef CONFIG_ARCH_ROMPGTABLE
/* Notice that these mappings are a simple 1-to-1 mapping *unless*
* CONFIG_ARCH_LOWVECTORS is not defined. In the high vector case, the
* register system controls register area is moved out 0f 0xffff:000 where
* the high vectors must reside.
*/
#define SAM_INTMEM_VSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
# define SAM_BOOTMEM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
# define SAM_ROM_VSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
@ -284,12 +290,24 @@
#define SAM_EBICS3_VSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 2 */
#define SAM_NFCCR_VSECTION 0x70000000 /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0x80000000-0xefffffff: Undefined */
/* If CONFIG_ARCH_LOWVECTORS is not defined, then move the system control
* registers out of the way.
*/
#ifdef CONFIG_ARCH_LOWVECTORS
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
# define SAM_SYSC_VSECTION 0xfff00000 /* 0xfff00000-0xffffffff: System Controller */
# define SAM_SYSC_VADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
#else
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf1000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHB_VSECTION 0xf2000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
# define SAM_SYSC_VSECTION 0xf300000 /* 0xfff00000-0xffffffff: System Controller */
# define SAM_SYSC_VADDR 0xf30fc000 /* 0xffffc000-0xffffffff: System Controller */
#endif
#endif
/* Peripheral virtual base addresses */

17
arch/arm/src/sama5/sam_boot.c
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@ -38,7 +38,9 @@
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
@ -304,9 +306,14 @@ static void sam_vectorpermissions(uint32_t mmuflags)
#ifdef NEED_VECTORMAP
static void sam_vectormapping(void)
{
uint32_t vector_paddr = SAM_VECTOR_PADDR;
uint32_t vector_vaddr = SAM_VECTOR_VADDR;
uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE;
uint32_t vector_paddr = SAM_VECTOR_PADDR & PTE_SMALL_PADDR_MASK;
uint32_t vector_vaddr = SAM_VECTOR_VADDR & PTE_SMALL_PADDR_MASK;
uint32_t vector_size = (uint32_t)&_vector_end - (uint32_t)&_vector_start;
uint32_t end_paddr = SAM_VECTOR_PADDR + vector_size;
/* REVISIT: Cannot really assert in this context */
DEBUGASSERT (vector_size <= VECTOR_TABLE_SIZE);
/* We want to keep our interrupt vectors and interrupt-related logic in
* zero-wait state internal SRAM (ISRAM). The SAMA5 has 128Kb of ISRAM
@ -324,7 +331,9 @@ static void sam_vectormapping(void)
/* Now set the level 1 descriptor to refer to the level 2 page table. */
sam_setl1entry(VECTOR_L2_PBASE, SAM_VECTOR_VADDR, MMU_L1_VECTORFLAGS);
sam_setl1entry(VECTOR_L2_PBASE & PMD_PTE_PADDR_MASK,
SAM_VECTOR_VADDR & PMD_PTE_PADDR_MASK,
MMU_L1_VECTORFLAGS);
}
#else
/* No vector remap */