Fixes a few typos in comments
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@ -96,7 +96,7 @@
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* PMC_MCKR_CSS_SLOW Slow Clock
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* PMC_MCKR_CSS_MAIN Main Clock
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* PMC_MCKR_CSS_PLLA PLLA Clock
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* MC_MCKR_CSS_UPLL Divided UPLL Clock
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* PMC_MCKR_CSS_UPLL Divided UPLL Clock
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*
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* BOARD_PMC_MCKR_PRES - Source clock pre-scaler. May be one of:
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*
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@ -105,7 +105,7 @@
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* PMC_MCKR_PRES_DIV4 Selected clock divided by 4
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* PMC_MCKR_PRES_DIV8 Selected clock divided by 8
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* PMC_MCKR_PRES_DIV16 Selected clock divided by 16
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* MC_MCKR_PRES_DIV32 Selected clock divided by 32
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* PMC_MCKR_PRES_DIV32 Selected clock divided by 32
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* PMC_MCKR_PRES_DIV64 Selected clock divided by 64
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* PMC_MCKR_PRES_DIV3 Selected clock divided by 3
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*
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@ -115,7 +115,7 @@
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*
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* BOARD_PMC_MCKR_MDIV - MCK divider. May be one of:
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*
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* PMC_MCKR_MDIV_DIV1 Master Clock is Prescaler Output Clock / 1
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* PMC_MCKR_MDIV_DIV1 Master Clock = Prescaler Output Clock / 1
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* PMC_MCKR_MDIV_DIV2 Master Clock = Prescaler Output Clock / 2
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* PMC_MCKR_MDIV_DIV4 Master Clock = Prescaler Output Clock / 4
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* PMC_MCKR_MDIV_DIV3 Master Clock = Prescaler Output Clock / 3
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