sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix nxstyle warning

Browse Source 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2020-07-05 15:10:40 +08:00 committed by David Sidrane
parent bf7399a982
commit 1475309c5b
18 changed files with 75 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/src/efm32/efm32_start.c
View File

@ -98,7 +98,7 @@ static inline void efm32_fpuconfig(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_nx_start(void *pv, unsigned int nbytes)
__attribute__ ((naked,no_instrument_function,noreturn));
__attribute__ ((naked, no_instrument_function, noreturn));
#endif
/****************************************************************************
@ -141,7 +141,7 @@ static void go_nx_start(void *pv, unsigned int nbytes)
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -175,7 +175,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -205,7 +205,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}

2
arch/arm/src/efm32/efm32_start.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
/****************************************************************************

3
arch/arm/src/imxrt/imxrt_start.c
View File

@ -305,7 +305,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_BOOT_RUNFROMISRAM

14
arch/arm/src/kinetis/kinetis_start.c
View File

@ -75,8 +75,8 @@ static void go_nx_start(void *pv, unsigned int nbytes)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/*
/* Memory Map ***************************************************************
* 0x0000:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH).
@ -116,7 +116,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Functions
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
@ -139,7 +138,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -173,7 +172,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -203,7 +202,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -276,7 +275,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Disable the watchdog timer */

9
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
View File

@ -121,7 +121,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -155,7 +155,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -185,7 +185,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -225,7 +225,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Configure the uart so that we can get debug output as soon as possible */

8
arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
View File

@ -50,10 +50,10 @@
* Name: lpc17_40_boardinitialize
*
* Description:
* All LPC17xx/LPC40xx architectures must provide the following entry point. This entry
* point is called early in the initialization -- after clocking and memory have
* been configured but before caches have been enabled and before any devices have
* been initialized.
* All LPC17xx/LPC40xx architectures must provide the following entry point. This
* entry point is called early in the initialization -- after clocking and memory
* have been configured but before caches have been enabled and before any devices
* have been initialized.
*
************************************************************************************/

9
arch/arm/src/sam34/sam_start.c
View File

@ -138,7 +138,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -172,7 +172,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -202,7 +202,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -280,7 +280,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

9
arch/arm/src/samd5e5/sam_start.c
View File

@ -139,7 +139,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -173,7 +173,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -203,7 +203,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -276,7 +276,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

14
arch/arm/src/samv7/sam_start.c
View File

@ -61,8 +61,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
/* Memory Map ***************************************************************
* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM and start of .data (_sdata)
@ -132,7 +133,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -166,7 +167,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -196,7 +197,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -316,7 +317,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

9
arch/arm/src/stm32/stm32_start.c
View File

@ -140,7 +140,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -174,7 +174,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -204,7 +204,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -275,7 +275,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Configure the UART so that we can get debug output as soon as possible */

13
arch/arm/src/stm32f7/stm32_start.c
View File

@ -62,8 +62,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
/*
* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
/* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM and start of .data (_sdata)
@ -133,7 +133,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -167,7 +167,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -197,7 +197,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -318,7 +318,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

13
arch/arm/src/stm32h7/stm32_start.c
View File

@ -62,8 +62,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
/*
* TODO: Fix this
/* TODO: Fix this
* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
@ -148,7 +148,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -182,7 +182,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -212,7 +212,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -333,7 +333,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

13
arch/arm/src/stm32l4/stm32l4_start.c
View File

@ -60,8 +60,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
/*
* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x1000:0000 - Start of internal SRAM2
@ -148,7 +148,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@ -182,7 +182,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -212,7 +212,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@ -283,7 +283,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32L4_SRAM2_INIT

2
arch/arm/src/tiva/tiva_start.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
/****************************************************************************

2
arch/hc/src/m9s12/m9s12_initialstate.c
View File

@ -111,7 +111,7 @@ void up_initial_state(struct tcb_s *tcb)
# ifdef CONFIG_SUPPRESS_INTERRUPTS
/* Disable STOP, Mask I- and Z- interrupts */
xcp->regs[REG_CCR] = HCS12_CCR_S|HCS12_CCR_X|HCS12_CCR_I;
xcp->regs[REG_CCR] = HCS12_CCR_S | HCS12_CCR_X | HCS12_CCR_I;
# else
/* Disable STOP, Enable I- and Z-interrupts */

1
arch/renesas/src/m16c/chip.h
View File

@ -62,6 +62,7 @@
/* Bits 8-11: Reserved */
#define M16C_FLG_IPLMASK 0x7000 /* Bits 12:14: Processor interrupt priority level */
/* Bit 15: Reserved */
/* Memory Map */
/* Memory-mapped special function registers begin at address 0x00000 */

6
arch/renesas/src/m16c/m16c_initialstate.c
View File

@ -82,7 +82,9 @@ void up_initial_state(FAR struct tcb_s *tcb)
memset(xcp, 0, sizeof(struct xcptcontext));
/* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an interrupt */
/* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an
* interrupt
*/
*regs++ = ((M16C_DEFAULT_IPL << 4) | ((uint32_t)tcb->start >> 16));
@ -101,7 +103,7 @@ void up_initial_state(FAR struct tcb_s *tcb)
/* Offset 18-20: User stack pointer */
regs = &xcp->regs[REG_SP];
regs = &xcp->regs[REG_SP];
*regs++ = (uint32_t)tcb->adj_stack_ptr >> 8; /* Bits 8-15 of SP */
*regs = (uint32_t)tcb->adj_stack_ptr; /* Bits 0-7 of SP */
}

2
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
View File

@ -364,7 +364,7 @@ int stm32_bbsram_int(void)
state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1;
syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x "
"state:%d\n", (unsigned int)desc.fileno, (unsigned int) desc.len,
"state:%d\n", (unsigned int)desc.fileno, (unsigned int)desc.len,
(unsigned int)desc.flags, state);
if (state == OK)