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arch/arm/src/tiva: Fix several compile problems with trim logic. Still many missing TI driverlib functions.

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This commit is contained in:
Gregory Nutt 2019-01-16 09:04:49 -06:00
parent a7fb5d4445
commit 14b4b6abf1
8 changed files with 84 additions and 78 deletions
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21
arch/arm/src/tiva/cc13xx/cc13x0_trim.c
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
* arch/arm/src/tiva/cc13xx/cc13x0_trim.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -45,13 +45,14 @@
#include <nuttx/config.h>
#include "tiva_chipinfo.h"
#include "hardware/tiva_adi2_refsys.h"
#include "hardware/tiva_adi3_refsys.h"
#include "hardware/tiva_aon_ioc.h"
#include "hardware/tiva_ccfg.h"
#include "hardware/tiva_fcfg1.h"
#include "hardware/tiva_flash.h"
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
#include "hardware/tiva_ddi0_osc.h"
#include "hardware/tiva_adi2_refsys.h"
#include "hardware/tiva_adi3_refsys.h"
/******************************************************************************
* Private Functions
@ -93,6 +94,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
uint32_t ccfg_modeconf;
uint32_t mp1rev;
uing32_t regval;
/* Force AUX on and enable clocks No need to save the current status of the
* power/clock registers. At this point both AUX and AON should have been
@ -125,14 +127,15 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
putreg8((uint8_t)regval,
TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
}
/* Enable for JTAG to be powered down(will still be powered on if debugger
* is connected)
*/
AONWUCJtagPowerOff();
AONWUCJtagPowerOff();
/* read the MODE_CONF register in CCFG */
@ -172,6 +175,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
uint32_t ldoTrimReg = getreg32(TIVA_FCFG1_BAT_RC_LDO_TRIM);
uint32_t vtrim_bod;
uint32_t vtrim_udig;
uint8_t regval8;
/* bit[27:24] unsigned */
@ -202,7 +206,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
regval8 = (vtrim_udig << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT) |
(vtrim_bod << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT);
putreg8(regval, TIVA_ADI2_SOCLDOCTL0);
putreg8(regval, TIVA_ADI2_REFSYS_SOCLDOCTL0);
}
/* Third part of trim done after cold reset and wakeup from shutdown:
@ -268,6 +272,7 @@ void cc13xx_trim_device(void)
{
uint32_t fcfg1_revision;
uint32_t aon_sysresetctrl;
uint32_t regval;
/* Get layout revision of the factory configuration area (Handle undefined
* revision as revision = 0)
@ -303,7 +308,7 @@ void cc13xx_trim_device(void)
*/
regval = getreg32(TIVA_PRCM_WARMRESET);
regval |= PRCM_WARMRESET_WR_TO_PINRESET;
regval |= PRCM_WARMRESET_WRTO_PINRESET;
putreg32(regval, TIVA_PRCM_WARMRESET)
/* Select correct CACHE mode and set correct CACHE configuration */

65
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
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@ -1,5 +1,5 @@
/******************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
* arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -45,16 +45,17 @@
#include <nuttx/config.h>
#include "tiva_chipinfo.h"
#include "hardware/tiva_ccfg.h"
#include "hardware/tiva_flash.h"
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
#include "hardware/tiva_ddi0_osc.h"
#include "hardware/tiva_aon_pmctl.h"
#include "hardware/tiva_aon_rtc.h"
#include "hardware/tiva_adi2_refsys.h"
#include "hardware/tiva_adi3_refsys.h"
#include "hardware/tiva_adi4_aux.h"
#include "hardware/tiva_aon_ioc.h"
#include "hardware/tiva_aon_pmctl.h"
#include "hardware/tiva_aon_rtc.h"
#include "hardware/tiva_ccfg.h"
#include "hardware/tiva_ddi0_osc.h"
#include "hardware/tiva_flash.h"
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
/******************************************************************************
* Pre-processor Definitions
@ -135,7 +136,7 @@ static void Step_RCOSCHF_CTRIM(uint32_t toCode)
}
/******************************************************************************
* Name: Step_VBG
* Name: step_vbg
*
* Description:
* Special shadow register trim propagation on first batch of devices.
@ -145,22 +146,26 @@ static void Step_RCOSCHF_CTRIM(uint32_t toCode)
*
******************************************************************************/
static void Step_VBG(int32_t target_signed)
static void step_vbg(int32_t target_signed)
{
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI3_REFSYS:REFSYSCTL3.TRIM_VBG) */
int32_t current_signed;
uint8_t ref_sysctl;
do
{
uint8_t ref_sysctl;
int lshift;
int rshift;
ref_sysctl = getreg8(TIVA_ADI3_REFSYS_REFSYSCTL3);
current_signed =
(((int32_t)
(ref_sysctl <<
(32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_W -
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT))) >>
(32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_W));
/* Isolate and sign extend the TRIM VDBG field */
lshift = (32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_WIDTH -
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT);
rshift = (32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_WIDTH);
current_signed = (((int32_t)ref_sysctl << lshift) >> rshift);
/* Wait for next edge on SCLK_LF (positive or negative) */
@ -209,6 +214,7 @@ static void Step_VBG(int32_t target_signed)
static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
uint32_t ccfg_modeconf;
uint32_t regval;
/* Check in CCFG for alternative DCDC setting */
@ -236,13 +242,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
* OSCHfSourceSwitch().
*/
regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL |
(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL >> 16);
putreg32(regval, TIVA_DDI0_OSC_MASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
/* Dummy read to ensure that the write has propagated */
(void)getreg16(TIVA_AUX_DDI0_OSCCTL0);
(void)getreg16(TIVA_DDI0_OSC_CTL0);
/* read the MODE_CONF register in CCFG */
@ -273,6 +279,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
uint32_t org_resetctl;
uint16_t regval16;
uint8_t regval8;
int lshift;
int rshift;
/* Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register
* OSC_BIAS_LDO_TRIM
@ -389,13 +397,14 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_SHIFT);
}
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI3_REFSYS:REFSYSCTL3.TRIM_VBG) */
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI3_REFSYS:REFSYSCTL3.TRIM_VBG)
* Provide isolated and sign extended SHDW_ANA_TRIM_TRIMTEMP
*/
Step_VBG(((int32_t)
(fusedata <<
(32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W -
FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT))) >>
(32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W));
lshift = (32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_WIDTH -
FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT);
rshift = (32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_WIDTH);
step_vbg(((int32_t)fusedata << lshift) >> rshift);
/* Wait two more LF edges before restoring xxx_LOSS_EN settings */
@ -420,7 +429,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
uint16_t regval16;
uint8_t regval8;
/*Propagate the LPM_BIAS trim */
/* Propagate the LPM_BIAS trim */
trimreg = getreg32(TIVA_FCFG1_DAC_BIAS_CNF);
trimvalue = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_MASK) >>

31
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
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@ -1,5 +1,5 @@
/******************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
* arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -45,13 +45,15 @@
#include <nuttx/config.h>
#include "tiva_chipinfo.h"
#include "hardware/tiva_ccfg.h"
#include "hardware/tiva_flash.h"
#include "hardware/tiva_vims.h"
#include "hardware/tiva_ddi0_osc.h"
#include "hardware/tiva_aon_pmctl.h"
#include "hardware/tiva_adi3_refsys.h"
#include "hardware/tiva_adi4_aux.h"
#include "hardware/tiva_aon_ioc.h"
#include "hardware/tiva_aon_pmctl.h"
#include "hardware/tiva_ccfg.h"
#include "hardware/tiva_ddi0_osc.h"
#include "hardware/tiva_flash.h"
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
/******************************************************************************
* Private Functions
@ -120,13 +122,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
* OSCHfSourceSwitch().
*/
regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL |
(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL >> 16);
putreg32(regval, TIVA_DDI0_OSC_MASK16B + (TIVA_DDI0_OSC_CTL0_OFFSET << 1) + 4);
/* Dummy read to ensure that the write has propagated */
(void)getret16(TIVA_AUX_DDI0_OSCCTL0);
(void)getreg16(TIVA_DDI0_OSC_CTL0);
/* read the MODE_CONF register in CCFG */
@ -183,9 +185,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
uint32_t trimwidth;
uint16_t regval16;
uint32_t trimwidth =
((trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_MASK) >>
FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_SHIFT);
trimwidth = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_MASK) >>
FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_SHIFT);
/* Set LPM_BIAS_WIDTH_TRIM = 3
* Set mask (bits to be written) in [15:8]
@ -221,7 +222,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
}
/******************************************************************************
* Name:
* Name: trim_coldreset
*
* Description:
* Trims to be applied when coming from PIN_RESET.
@ -379,7 +380,7 @@ void cc13xx_trim_device(void)
* but need to be sure)
*/
while ((getreg32(TIVA_VIMS_STAT0 & VIMS_STAT_MODE_CHANGING) != 0)
while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0)
{
/* Do nothing - wait for an eventual ongoing mode change to complete. */
}

10
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h
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@ -63,11 +63,11 @@
/* AON IOC Register Addresses ***************************************************************************************/
#define TIVA_AON_IOC_IOSTRMIN (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
#define TIVA_AON_IOC_IOSTRMAX (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMAX_OFFSET)
#define TIVA_AON_IOC_IOCLATCH (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
#define TIVA_AON_IOC_CLK32KCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
#define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
#define TIVA_AON_IOC_IOSTRMAX (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMAX_OFFSET)
#define TIVA_AON_IOC_IOCLATCH (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
#define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
/* AON IOC Bitfield Definitions *************************************************************************************/

1
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
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@ -186,6 +186,7 @@
/* TIVA_ADI3_REFSYS_REFSYSCTL3 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT (0) /* Bits 0-5 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_WIDTH (6) /* (Needed to sign extend) */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK (0x3f << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
# define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
#define ADI3_REFSYS_REFSYSCTL3_VTEMP_EN (1 << 6) /* Bit 6 */

21
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h
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@ -65,10 +65,7 @@
#define TIVA_ADI4_AUX_ADC1_OFFSET 0x0009 /* ADC Control 1 */
#define TIVA_ADI4_AUX_ADCREF0_OFFSET 0x000a /* ADC Reference 0 */
#define TIVA_ADI4_AUX_ADCREF1_OFFSET 0x000b /* ADC Reference 1 */
#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
# define TIVA_ADI4_AUX_LPMBIAS_OFFSET 0x000e
#endif
#define TIVA_ADI4_AUX_LPMBIAS_OFFSET 0x000e
/* ADI3 AUX Register Addresses **************************************************************************************/
@ -83,10 +80,7 @@
#define TIVA_ADI4_AUX_ADC1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADC1_OFFSET)
#define TIVA_ADI4_AUX_ADCREF0 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF0_OFFSET)
#define TIVA_ADI4_AUX_ADCREF1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF1_OFFSET)
#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
# define TIVA_ADI4_AUX_LPMBIAS (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_LPMBIAS_OFFSET)
#endif
#define TIVA_ADI4_AUX_LPMBIAS (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_LPMBIAS_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
@ -180,13 +174,9 @@
#define ADI4_AUX_COMP_COMPA_EN (1 << 1) /* Bit 1: COMPA enable */
#define ADI4_AUX_COMP_COMPB_EN (1 << 2) /* Bit 2: COMPB enable */
#ifdef CONFIG_ARCH_CHIP_CC13XX_V2
# define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT (3) /* Bits 3-5 */
# define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK (7 << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
# define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM(n) ((uint32_t)(n) << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
#endif
#define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT (3) /* Bits 3-5 */
#define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK (7 << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
# define ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM(n) ((uint32_t)(n) << ADI4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT)
#define ADI4_AUX_COMP_COMPA_REF_CURR_EN (1 << 6) /* Bit 6: Enables 2uA IPTAT current from ISRC to COMPA reference */
#define ADI4_AUX_COMP_COMPA_REF_RES_EN (1 << 7) /* Bit 7: Enables 400kohm resistance from COMPA reference */
@ -245,7 +235,6 @@
#define ADI4_AUX_ADCREF0_IOMUX (1 << 5) /* Bit 5 */
#define ADI4_AUX_ADCREF0_REF_ON_IDLE (1 << 6) /* Bit 6: Enable ADCREF in IDLE state */
/* TIVA_ADI4_AUX_ADCREF1 */
#define ADI4_AUX_ADCREF1_VTRIM_SHIFT (0) /* Bits 0-5: Trim output voltage of ADC fixed

12
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h
View File

@ -63,12 +63,12 @@
/* AON IOC Register Addresses ***************************************************************************************/
#define TIVA_AON_IOC_IOSTRMIN (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
#define TIVA_AON_IOC_IOSTRMAX (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMAX_OFFSET)
#define TIVA_AON_IOC_IOCLATCH (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
#define TIVA_AON_IOC_CLK32KCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
#define TIVA_AON_IOC_TCKCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_TCKCTL_OFFSET)
#define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
#define TIVA_AON_IOC_IOSTRMAX (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMAX_OFFSET)
#define TIVA_AON_IOC_IOCLATCH (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
#define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
#define TIVA_AON_IOC_TCKCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_TCKCTL_OFFSET)
/* AON IOC Bitfield Definitions *************************************************************************************/

1
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h
View File

@ -1186,6 +1186,7 @@ degrees C */
/* TIVA_FCFG1_SHDW_ANA_TRIM */
#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT (0) /* Bits 0-5 */
#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_WIDTH (6) /* (For sign extension) */
#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_MASK (0x3f << FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT)
# define FCFG1_SHDW_ANA_TRIM_TRIMTEMP(n) ((uint32_t)(n) << FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT)
#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_SHIFT (6) /* Bits 6-10 */