Add memory map for the TM4C129X
This commit is contained in:
Gregory Nutt
parent
aa724ea75b
commit
14b987dbfa
@ -89,6 +89,30 @@
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# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
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/* -0xe003ffff: Reserved */
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# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
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# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
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/* -0xffffffff: Reserved */
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#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_FLASH_BASE 0x00000000 /* -0x000fffff: On-chip FLASH */
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/* -0x01ffffff: Reserved */
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# define TIVA_ROM_BASE 0x02000000 /* -0x02ffffff: On-chip ROM (16 MB) */
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/* -0x1fffgfff: Reserved */
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# define TIVA_SRAM_BASE 0x20000000 /* -0x2006ffff: Bit-banded on-chip SRAM */
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/* -0x21ffffff: Reserved */
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# define TIVA_ASRAM_BASE 0x22000000 /* -0x2234ffff: Bit-band alias of 20000000- */
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/* -0x3fffffff: Reserved */
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# define TIVA_PERIPH1_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
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/* -0x41ffffff: Peripherals */
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# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000-400fffff */
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# define TIVA_PERIPH2_BASE 0x44000000 /* -0x4001ffff: More Peripherals */
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/* -0x5fffffff: Reserved */
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# define TIVA_EPIRAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */
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# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
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# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
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# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
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/* -0xe000dfff: Reserved */
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# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
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/* -0xe003ffff: Reserved */
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# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
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# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
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/* -0xffffffff: Reserved */
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#else
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@ -99,6 +123,8 @@
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
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/* Peripheral Base Addresses */
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# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
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# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
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/* -0x03fff: Reserved */
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@ -119,8 +145,6 @@
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# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
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# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
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/* -0x1ffff: Reserved */
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/* Peripheral Base Addresses */
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# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
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# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
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# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
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@ -185,6 +209,8 @@
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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/* Peripheral Base Addresses */
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# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
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# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
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/* -0x03fff: Reserved */
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@ -205,8 +231,6 @@
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# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
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# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
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/* -0x1ffff: Reserved */
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/* Peripheral Base Addresses */
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# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
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# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
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# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
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@ -253,8 +277,11 @@
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# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
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# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
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# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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/* Peripheral Base Addresses */
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# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
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# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
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/* -0x03fff: Reserved */
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@ -275,8 +302,6 @@
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# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
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# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
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/* -0x1ffff: Reserved */
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/* Peripheral Base Addresses */
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# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
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# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
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# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
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@ -323,6 +348,118 @@
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# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
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# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
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# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
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#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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/* Peripheral region 1 */
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# define TIVA_WDOG0_BASE (TIVA_PERIPH1_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
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# define TIVA_WDOG1_BASE (TIVA_PERIPH1_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
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/* -0x03fff: Reserved */
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# define TIVA_GPIOA_BASE (TIVA_PERIPH1_BASE + 0x04000) /* -0x04fff: GPIO Port A */
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# define TIVA_GPIOB_BASE (TIVA_PERIPH1_BASE + 0x05000) /* -0x05fff: GPIO Port B */
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# define TIVA_GPIOC_BASE (TIVA_PERIPH1_BASE + 0x06000) /* -0x06fff: GPIO Port C */
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# define TIVA_GPIOD_BASE (TIVA_PERIPH1_BASE + 0x07000) /* -0x07fff: GPIO Port D */
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# define TIVA_SSI0_BASE (TIVA_PERIPH1_BASE + 0x08000) /* -0x08fff: SSI0 */
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# define TIVA_SSI1_BASE (TIVA_PERIPH1_BASE + 0x09000) /* -0x09fff: SSI1 */
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# define TIVA_SSI2_BASE (TIVA_PERIPH1_BASE + 0x0a000) /* -0x0afff: SSI2 */
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# define TIVA_SSI3_BASE (TIVA_PERIPH1_BASE + 0x0b000) /* -0x0bfff: SSI3 */
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# define TIVA_UART0_BASE (TIVA_PERIPH1_BASE + 0x0c000) /* -0x0cfff: UART0 */
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# define TIVA_UART1_BASE (TIVA_PERIPH1_BASE + 0x0d000) /* -0x0dfff: UART1 */
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# define TIVA_UART2_BASE (TIVA_PERIPH1_BASE + 0x0e000) /* -0x0efff: UART2 */
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# define TIVA_UART3_BASE (TIVA_PERIPH1_BASE + 0x0f000) /* -0x0ffff: UART3 */
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# define TIVA_UART4_BASE (TIVA_PERIPH1_BASE + 0x10000) /* -0x10fff: UART4 */
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# define TIVA_UART5_BASE (TIVA_PERIPH1_BASE + 0x11000) /* -0x11fff: UART5 */
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# define TIVA_UART6_BASE (TIVA_PERIPH1_BASE + 0x12000) /* -0x12fff: UART6 */
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# define TIVA_UART7_BASE (TIVA_PERIPH1_BASE + 0x13000) /* -0x13fff: UART7 */
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/* -0x1ffff: Reserved */
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# define TIVA_I2C0_BASE (TIVA_PERIPH1_BASE + 0x20000) /* -0x20fff: I2C0 */
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# define TIVA_I2C1_BASE (TIVA_PERIPH1_BASE + 0x21000) /* -0x21fff: I2C1 */
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# define TIVA_I2C2_BASE (TIVA_PERIPH1_BASE + 0x22000) /* -0x22fff: I2C2 */
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# define TIVA_I2C3_BASE (TIVA_PERIPH1_BASE + 0x23000) /* -0x23fff: I2C3 */
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# define TIVA_GPIOE_BASE (TIVA_PERIPH1_BASE + 0x24000) /* -0x24fff: GPIO Port E */
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# define TIVA_GPIOF_BASE (TIVA_PERIPH1_BASE + 0x25000) /* -0x25fff: GPIO Port F */
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# define TIVA_GPIOG_BASE (TIVA_PERIPH1_BASE + 0x26000) /* -0x26fff: GPIO Port G */
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# define TIVA_GPIOH_BASE (TIVA_PERIPH1_BASE + 0x27000) /* -0x27fff: GPIO Port H */
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# define TIVA_PWM0_BASE (TIVA_PERIPH1_BASE + 0x28000) /* -0x28fff: PWM 0 */
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/* -0x2bfff: Reserved */
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# define TIVA_QEI0_BASE (TIVA_PERIPH1_BASE + 0x2c000) /* -0x2cfff: QEI 0 */
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/* -0x2ffff: Reserved */
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# define TIVA_TIMER0_BASE (TIVA_PERIPH1_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
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# define TIVA_TIMER1_BASE (TIVA_PERIPH1_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
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# define TIVA_TIMER2_BASE (TIVA_PERIPH1_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
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# define TIVA_TIMER3_BASE (TIVA_PERIPH1_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
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# define TIVA_TIMER4_BASE (TIVA_PERIPH1_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
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# define TIVA_TIMER5_BASE (TIVA_PERIPH1_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
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/* -0x37fff: Reserved */
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# define TIVA_ADC0_BASE (TIVA_PERIPH1_BASE + 0x38000) /* -0x38fff: ADC 0 */
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# define TIVA_ADC1_BASE (TIVA_PERIPH1_BASE + 0x39000) /* -0x39fff: ADC 1 */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH1_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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# define TIVA_GPIOJ_BASE (TIVA_PERIPH1_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
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/* -0x3ffff: Reserved */
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# define TIVA_CAN0_BASE (TIVA_PERIPH1_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
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# define TIVA_CAN1_BASE (TIVA_PERIPH1_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
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/* -0x4ffff: Reserved */
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# define TIVA_USB_BASE (TIVA_PERIPH1_BASE + 0x50000) /* -0x50fff: USB */
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/* -0x57fff: Reserved */
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# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH1_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
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# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH1_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
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# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH1_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
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# define TIVA_GPIODAHB_BASE (TIVA_PERIPH1_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
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# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH1_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
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# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH1_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
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# define TIVA_GPIOGAHB_BASE (TIVA_PERIPH1_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
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# define TIVA_GPIOHAHB_BASE (TIVA_PERIPH1_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
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# define TIVA_GPIOJAHB_BASE (TIVA_PERIPH1_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
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# define TIVA_GPIOKAHB_BASE (TIVA_PERIPH1_BASE + 0x61000) /* -0x61fff: GPIO Port K (AHB aperture) */
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# define TIVA_GPIOLAHB_BASE (TIVA_PERIPH1_BASE + 0x62000) /* -0x62fff: GPIO Port L (AHB aperture) */
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# define TIVA_GPIOMAHB_BASE (TIVA_PERIPH1_BASE + 0x63000) /* -0x63fff: GPIO Port M (AHB aperture) */
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# define TIVA_GPIONAHB_BASE (TIVA_PERIPH1_BASE + 0x64000) /* -0x64fff: GPIO Port N (AHB aperture) */
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# define TIVA_GPIOPAHB_BASE (TIVA_PERIPH1_BASE + 0x65000) /* -0x65fff: GPIO Port P (AHB aperture) */
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# define TIVA_GPIOQAHB_BASE (TIVA_PERIPH1_BASE + 0x66000) /* -0x66fff: GPIO Port Q (AHB aperture) */
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# define TIVA_GPIORRHB_BASE (TIVA_PERIPH1_BASE + 0x67000) /* -0x67fff: GPIO Port R (AHB aperture) */
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# define TIVA_GPIOFSHB_BASE (TIVA_PERIPH1_BASE + 0x68000) /* -0x68fff: GPIO Port S (AHB aperture) */
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# define TIVA_GPIOFTHB_BASE (TIVA_PERIPH1_BASE + 0x69000) /* -0x69fff: GPIO Port T (AHB aperture) */
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/* -0xaefff: Reserved */
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# define TIVA_EEPROM_BASE (TIVA_PERIPH1_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
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/* -0xb5fff: Reserved */
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# define TIVA_1WIRE_BASE (TIVA_PERIPH1_BASE + 0xb6000) /* -0xb6fff: EEPROM and Key Locker */
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/* -0xb7fff: Reserved */
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# define TIVA_I2C8_BASE (TIVA_PERIPH1_BASE + 0xb8000) /* -0xb8fff: I2C8 */
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# define TIVA_I2C9_BASE (TIVA_PERIPH1_BASE + 0xb9000) /* -0xb9fff: I2C9 */
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/* -0xbffff: Reserved */
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# define TIVA_I2C4_BASE (TIVA_PERIPH1_BASE + 0xc0000) /* -0xc0fff: I2C4 */
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# define TIVA_I2C5_BASE (TIVA_PERIPH1_BASE + 0xc1000) /* -0xc1fff: I2C5 */
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# define TIVA_I2C6_BASE (TIVA_PERIPH1_BASE + 0xc2000) /* -0xc2fff: I2C6 */
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# define TIVA_I2C7_BASE (TIVA_PERIPH1_BASE + 0xc3000) /* -0xc3fff: I2C7 */
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/* -0xcffff: Reserved */
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# define TIVA_EPI0_BASE (TIVA_PERIPH1_BASE + 0xd0000) /* -0xd0fff: EPI0 */
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/* -0xdffff: Reserved */
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# define TIVA_TIMER6_BASE (TIVA_PERIPH1_BASE + 0xe0000) /* -0xe0fff: 16/32 Timer 6 */
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# define TIVA_TIMER7_BASE (TIVA_PERIPH1_BASE + 0xe1000) /* -0xe1fff: 16/32 Timer 7 */
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/* -0xebfff: Reserved */
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# define TIVA_ETHCON_BASE (TIVA_PERIPH1_BASE + 0xec000) /* -0xecfff: Ethernet Controller */
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/* -0xf8fff: Reserved */
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# define TIVA_SYSEXC_BASE (TIVA_PERIPH1_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
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/* -0xfbfff: Reserved */
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# define TIVA_HIBERNATE_BASE (TIVA_PERIPH1_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
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# define TIVA_FLASHCON_BASE (TIVA_PERIPH1_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
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# define TIVA_SYSCON_BASE (TIVA_PERIPH1_BASE + 0xfe000) /* -0xfefff: System Control */
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# define TIVA_UDMA_BASE (TIVA_PERIPH1_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
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/* Peripheral region 2 */
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/* -0x2ffff: Reserved */
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# define TIVA_CRC_BASE (TIVA_PERIPH3_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */
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/* -0x33fff: Reserved */
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# define TIVA_SHAMD5_BASE (TIVA_PERIPH3_BASE + 0x34000) /* -0x35fff: SHA/MD5 */
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# define TIVA_AES_BASE (TIVA_PERIPH3_BASE + 0x36000) /* -0x37fff: AES */
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# define TIVA_DES_BASE (TIVA_PERIPH3_BASE + 0x38000) /* -0x39fff: DES */
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/* -0x4ffff: Reserved */
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# define TIVA_LCD_BASE (TIVA_PERIPH3_BASE + 0x50000) /* -0x50fff: LCD */
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/* -0x53fff: Reserved */
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# define TIVA_EPHY_BASE (TIVA_PERIPH3_BASE + 0x54000) /* -0x54fff: EPHY */
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/* -0xfffff: Reserved */
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#else
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# error "Peripheral base addresses not specified for this Stellaris chip"
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#endif
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@ -524,7 +524,7 @@ UNUSED(TIVA_RESERVED_123) /* Vector 123: Reserved */
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UNUSED(TIVA_RESERVED_124) /* Vector 124: Reserved */
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VECTOR(tiva_i2c8, TIVA_IRQ_I2C8) /* Vector 125: I2C 8 */
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VECTOR(tiva_i2c9, TIVA_IRQ_I2C9) /* Vector 126: I2C 9 */
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VECTOR(tiva_gpiot, TIVA_IRQ_GPIOT) /* Vector 127: GPIO Port S */
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VECTOR(tiva_gpiot, TIVA_IRQ_GPIOT) /* Vector 127: GPIO Port T */
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UNUSED(TIVA_RESERVED_128) /* Vector 128: Reserved */
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UNUSED(TIVA_RESERVED_129) /* Vector 129: Reserved */
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