diff --git a/arch/arm/src/efm32/chip/efm32_dma.h b/arch/arm/src/efm32/chip/efm32_dma.h
index 38db920b82..7f83ef36d7 100644
--- a/arch/arm/src/efm32/chip/efm32_dma.h
+++ b/arch/arm/src/efm32/chip/efm32_dma.h
@@ -2277,6 +2277,6 @@ struct dma_descriptor_s
   volatile void * volatile dstend; /* DMA destination address end */
   volatile uint32_t        ctrl;   /* DMA control register */
   volatile uint32_t        user;   /* DMA padding register, available for user */
-};      
+};
 
 #endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DMA_H */
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index 9b91efcee1..dc1f64ec05 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -646,7 +646,7 @@ void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
 
       /* Enable buffer-full requests for the channel */
 
-      putreg32(bit, EFM_DMA_CHREQMASKC);      
+      putreg32(bit, EFM_DMA_CHREQMASKC);
     }
   else
     {
@@ -656,12 +656,12 @@ void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
 
       /* Disable buffer-full requests for the channel */
 
-      putreg32(bit, EFM_DMA_CHREQMASKS);      
+      putreg32(bit, EFM_DMA_CHREQMASKS);
     }
 
   /* Use the primary data structure for channel 0 */
 
-  putreg32(bit, EFM_DMA_CHALTC);      
+  putreg32(bit, EFM_DMA_CHALTC);
 
   /* Enable the channel */
 
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index 98c973efae..ba3af1b267 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -1721,7 +1721,7 @@ static inline int sam_multiple(struct sam_xdmach_s *xdmach)
     {
       regval |= XDMACH_CNDC_NDSUP;
     }
-    
+
   /* Update the destination address if this is a *-to-memory transfer.
    *
    *   TYPE = 0 -> memory-to-memory
@@ -1887,7 +1887,7 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
           gpending &= !bit;
         }
     }
- 
+
   return OK;
 }