arch/nrf53: add more registers definitions
This commit is contained in:
raiden00pl
Alan Carvalho de Assis
parent
e3f2443fc3
commit
15a932f8e1
120
arch/arm/src/nrf53/hardware/nrf53_clock.h
Normal file
120
arch/arm/src/nrf53/hardware/nrf53_clock.h
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@ -0,0 +1,120 @@
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/****************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_clock.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_CLOCK_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_CLOCK_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "nrf53_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define NRF53_CLOCK_TASKS_HFCLKSTART_OFFSET 0x0000 /* Start HFCLK crystal oscillator */
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#define NRF53_CLOCK_TASKS_HFCLKSTOP_OFFSET 0x0004 /* Stop HFCLK crystal oscillator */
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#define NRF53_CLOCK_TASKS_LFCLKSTART_OFFSET 0x0008 /* Start LFCLK source */
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#define NRF53_CLOCK_TASKS_LFCLKSTOP_OFFSET 0x000c /* Stop LFCLK source */
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#define NRF53_CLOCK_TASKS_CAL_OFFSET 0x0010 /* Start calibration of LFRC oscillator */
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/* TODO: */
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#define NRF53_CLOCK_EVENTS_HFCLKSTARTED_OFFSET 0x0100 /* HFCLK oscillator started */
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#define NRF53_CLOCK_EVENTS_LFCLKSTARTED_OFFSET 0x0104 /* LFCLK started */
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#define NRF53_CLOCK_EVENTS_DONE_OFFSET 0x011c /* Calibration of LFCLK RC oscillator complete event */
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/* TODO: */
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#define NRF53_CLOCK_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF53_CLOCK_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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/* TODO: */
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#define NRF53_CLOCK_HFCLKRUN_OFFSET 0x0408 /* Status indicating that HFCLKSTART task has been triggered */
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#define NRF53_CLOCK_HFCLKSTAT_OFFSET 0x040c /* HFCLK status */
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#define NRF53_CLOCK_LFCLKRUN_OFFSET 0x0414 /* Status indicating that LFCLKSTART task has been triggered */
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#define NRF53_CLOCK_LFCLKSTAT_OFFSET 0x0418 /* LFCLK status */
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#define NRF53_CLOCK_LFCLKSRCCOPY_OFFSET 0x041c /* Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
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/* TODO: */
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#define NRF53_CLOCK_LFCLKSRC_OFFSET 0x0518 /* Clock source for the LFCLK */
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/* TODO */
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/* Register definitions *****************************************************/
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#define NRF53_CLOCK_TASKS_HFCLKSTART (NRF53_CLOCK_BASE + NRF53_CLOCK_TASKS_HFCLKSTART_OFFSET)
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#define NRF53_CLOCK_TASKS_HFCLKSTOP (NRF53_CLOCK_BASE + NRF53_CLOCK_TASKS_HFCLKSTOP_OFFSET)
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#define NRF53_CLOCK_TASKS_LFCLKSTART (NRF53_CLOCK_BASE + NRF53_CLOCK_TASKS_LFCLKSTART_OFFSET)
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#define NRF53_CLOCK_TASKS_LFCLKSTOP (NRF53_CLOCK_BASE + NRF53_CLOCK_TASKS_LFCLKSTOP_OFFSET)
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#define NRF53_CLOCK_TASKS_CAL (NRF53_CLOCK_BASE + NRF53_CLOCK_TASKS_CAL_OFFSET)
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/* TODO */
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#define NRF53_CLOCK_EVENTS_HFCLKSTARTED (NRF53_CLOCK_BASE + NRF53_CLOCK_EVENTS_HFCLKSTARTED_OFFSET)
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#define NRF53_CLOCK_EVENTS_LFCLKSTARTED (NRF53_CLOCK_BASE + NRF53_CLOCK_EVENTS_LFCLKSTARTED_OFFSET)
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#define NRF53_CLOCK_EVENTS_DONE (NRF53_CLOCK_BASE + NRF53_CLOCK_EVENTS_DONE_OFFSET)
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/* TODO */
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#define NRF53_CLOCK_INTENSET (NRF53_CLOCK_BASE + NRF53_CLOCK_INTENSET_OFFSET)
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#define NRF53_CLOCK_INTENCLR (NRF53_CLOCK_BASE + NRF53_CLOCK_INTENCLR_OFFSET)
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/* TODO */
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#define NRF53_CLOCK_HFCLKRUN (NRF53_CLOCK_BASE + NRF53_CLOCK_HFCLKRUN_OFFSET)
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#define NRF53_CLOCK_HFCLKSTAT (NRF53_CLOCK_BASE + NRF53_CLOCK_HFCLKSTAT_OFFSET)
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#define NRF53_CLOCK_LFCLKRUN (NRF53_CLOCK_BASE + NRF53_CLOCK_LFCLKRUN_OFFSET)
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#define NRF53_CLOCK_LFCLKSTAT (NRF53_CLOCK_BASE + NRF53_CLOCK_LFCLKSTAT_OFFSET)
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#define NRF53_CLOCK_LFCLKSRCCOPY (NRF53_CLOCK_BASE + NRF53_CLOCK_LFCLKSRCCOPY_OFFSET)
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/* TODO */
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#define NRF53_CLOCK_LFCLKSRC (NRF53_CLOCK_BASE + NRF53_CLOCK_LFCLKSRC_OFFSET)
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/* TODO */
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/* Register bit definitions *************************************************/
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/* HFCLKRUN Register */
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#define CLOCK_HFCLKRUN_STATUS (1 << 0) /* Bit 0: HFCLSTART task triggered status */
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/* HFCLKSTAT Register */
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#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */
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#define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT)
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# define CLOCK_HFCLKSTAT_SRC_HFINT (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 128 MHz internal oscillator (HFINT) */
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# define CLOCK_HFCLKSTAT_SRC_HFXO (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscilator (HFXO) */
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#define CLOCK_HFCLKSTAT_ALWAYSRUNNING (1 << 4) /* Bit 4: Oscillator is always running */
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#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */
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/* LFCLKRUN Register */
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#define CLOCK_LFCLKRUN_STATUS (1 << 0) /* Bit 0: LFCLKSTART task triggered status */
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/* LFCLKSTAT Register */
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#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */
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#define CLOCK_LFCLKSTAT_SRC_MASK (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
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# define CLOCK_LFCLKSTAT_SRC_LFRC (1 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b0: 32.768 kHz RC oscillator (LFRC) */
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# define CLOCK_LFCLKSTAT_SRC_LFXO (2 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b1: 32.768 kHz crystal oscillator (LFXO) */
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# define CLOCK_LFCLKSTAT_SRC_LFSYNT (3 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b2: 32.768 kHz synthesized from HFCLK (LFSYNT) */
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#define CLOCK_LFCLKSTAT_ALWAYSRUNNING (1 << 4) /* Bit 4: Oscillator is always running */
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#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */
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/* LFCLKSRC Register */
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#define CLOCK_LFCLKSRC_SRC_SHIFT (0) /* Bits 0-1: LFRC clock source */
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#define CLOCK_LFCLKSRC_SRC_MASK (3 << CLOCK_LFCLKSRC_SRC_SHIFT)
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# define CLOCK_LFCLKSRC_SRC_LFRC (1 << CLOCK_LFCLKSTAT_SRC_SHIFT)
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# define CLOCK_LFCLKSRC_SRC_LFXO (2 << CLOCK_LFCLKSTAT_SRC_SHIFT)
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# define CLOCK_LFCLKSRC_SRC_LFSYNT (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_CLOCK_H */
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36
arch/arm/src/nrf53/hardware/nrf53_ficr.h
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36
arch/arm/src/nrf53/hardware/nrf53_ficr.h
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@ -0,0 +1,36 @@
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/***************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_ficr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_H
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/***************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_NRF53_APPCORE
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# include "hardware/nrf53_ficr_cpuapp.h"
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#else
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# include "hardware/nrf53_ficr_cpunet.h"
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#endif
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_H */
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54
arch/arm/src/nrf53/hardware/nrf53_ficr_cpuapp.h
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54
arch/arm/src/nrf53/hardware/nrf53_ficr_cpuapp.h
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@ -0,0 +1,54 @@
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/***************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_ficr_cpuapp.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_CPUAPP_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_CPUAPP_H
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/***************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf53_memorymap.h"
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/***************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* FICR Register Offsets ***************************************************/
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#define NRF53_FICR_INFO_CONFIGID_OFFSET 0x200 /* Configuration identifier */
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#define NRF53_FICR_INFO_DEVICEID0_OFFSET 0x204 /* Device identifier */
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#define NRF53_FICR_INFO_DEVICEID1_OFFSET 0x208 /* Device identifier */
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#define NRF53_FICR_INFO_PART_OFFSET 0x20c /* Part code */
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#define NRF53_FICR_INFO_VARIANT_OFFSET 0x210 /* Part Variant, Hardware version and Production configuration */
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#define NRF53_FICR_INFO_PACKAGE_OFFSET 0x214 /* Package option */
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#define NRF53_FICR_INFO_RAM_OFFSET 0x218 /* RAM variant */
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#define NRF53_FICR_INFO_FLASH_OFFSET 0x21c /* Flash variant */
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#define NRF53_FICR_INFO_CODEPAGESIZE_OFFSET 0x220 /* Code memory page size in bytes */
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#define NRF53_FICR_INFO_CODESIZE_OFFSET 0x224 /* Code memory size */
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#define NRF53_FICR_INFO_DEVICETYPE_OFFSET 0x228 /* Device type */
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/* TODO */
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/* FICR Register Addresses *************************************************/
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/* TODO */
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_CPUAPP_H */
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64
arch/arm/src/nrf53/hardware/nrf53_ficr_cpunet.h
Normal file
64
arch/arm/src/nrf53/hardware/nrf53_ficr_cpunet.h
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@ -0,0 +1,64 @@
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/***************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_ficr_cpunet.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_NET_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_NET_H
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/***************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf53_memorymap.h"
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/***************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* FICR Register Offsets ***************************************************/
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#define NRF53_FICR_INFO_CONFIGID_OFFSET 0x200 /* Configuration identifier */
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#define NRF53_FICR_INFO_DEVICEID0_OFFSET 0x204 /* Device identifier */
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#define NRF53_FICR_INFO_DEVICEID1_OFFSET 0x208 /* Device identifier */
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#define NRF53_FICR_INFO_PART_OFFSET 0x20c /* Part code */
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#define NRF53_FICR_INFO_VARIANT_OFFSET 0x210 /* Part Variant, Hardware version and Production configuration */
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#define NRF53_FICR_INFO_PACKAGE_OFFSET 0x214 /* Package option */
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#define NRF53_FICR_INFO_RAM_OFFSET 0x218 /* RAM variant */
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#define NRF53_FICR_INFO_FLASH_OFFSET 0x21c /* Flash variant */
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#define NRF53_FICR_INFO_CODEPAGESIZE_OFFSET 0x220 /* Code memory page size in bytes */
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#define NRF53_FICR_INFO_CODESIZE_OFFSET 0x224 /* Code memory size */
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#define NRF53_FICR_INFO_DEVICETYPE_OFFSET 0x228 /* Device type */
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#define NRF52_FICR_ER0_OFFSET 0x280 /* Encryption Root, word 0 */
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#define NRF52_FICR_ER1_OFFSET 0x284 /* Encryption Root, word 1 */
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#define NRF52_FICR_ER2_OFFSET 0x288 /* Encryption Root, word 2 */
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#define NRF52_FICR_ER3_OFFSET 0x28c /* Encryption Root, word 3 */
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#define NRF52_FICR_IR0_OFFSET 0x290 /* Identity Root, word 0 */
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#define NRF52_FICR_IR1_OFFSET 0x294 /* Identity Root, word 1 */
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#define NRF52_FICR_IR2_OFFSET 0x298 /* Identity Root, word 2 */
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#define NRF52_FICR_IR3_OFFSET 0x29c /* Identity Root, word 3 */
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#define NRF52_FICR_DEVICEADDRTYPE_OFFSET 0x2a0 /* Device address type */
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#define NRF52_FICR_DEVICEADDR0_OFFSET 0x2a4 /* Device address 0 */
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#define NRF52_FICR_DEVICEADDR1_OFFSET 0x2a8 /* Device address 1 */
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/* FICR Register Addresses *************************************************/
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/* TODO */
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_FICR_NET_H */
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56
arch/arm/src/nrf53/hardware/nrf53_osc.h
Normal file
56
arch/arm/src/nrf53/hardware/nrf53_osc.h
Normal file
@ -0,0 +1,56 @@
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/****************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_osc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_OSC_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_OSC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "nrf53_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define NRF53_OSC_XOSC32MCAPS_OFFSET 0x5C4 /* Programmable capacitance of XC1 and XC2 */
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#define NRF53_OSC_XOSC32KI_BYPASS_OFFSET 0x6C0 /* Enable or disable bypass of LFCLK crystal oscillator with external clock source */
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#define NRF53_OSC_XOSC32KI_INTCAP_OFFSET 0x6D0 /* Control usage of internal load capacitors */
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/* Register definitions *****************************************************/
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#define NRF53_OSC_XOSC32MCAPS (NRF53_OSCILLATORS_BASE + NRF53_OSC_XOSC32MCAPS_OFFSET)
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#define NRF53_OSC_XOSC32KI_BYPASS (NRF53_OSCILLATORS_BASE + NRF53_OSC_XOSC32KI_BYPASS_OFFSET)
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#define NRF53_OSC_XOSC32KI_INTCAP (NRF53_OSCILLATORS_BASE + NRF53_OSC_XOSC32KI_INTCAP_OFFSET)
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/* Register bit definitions *************************************************/
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#define OSC_XOSC32KI_INTCAP_SHIFT (0)
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#define OSC_XOSC32KI_INTCAP_MASK (0x3 << OSC_XOSC32KI_INTCAP_SHIFT)
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# define OSC_XOSC32KI_INTCAP_EXT (0x0 << OSC_XOSC32KI_INTCAP_SHIFT)
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# define OSC_XOSC32KI_INTCAP_C6PF (0x1 << OSC_XOSC32KI_INTCAP_SHIFT)
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# define OSC_XOSC32KI_INTCAP_C7PF (0x2 << OSC_XOSC32KI_INTCAP_SHIFT)
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# define OSC_XOSC32KI_INTCAP_C9PF (0x3 << OSC_XOSC32KI_INTCAP_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_OSC_H */
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91
arch/arm/src/nrf53/hardware/nrf53_spu.h
Normal file
91
arch/arm/src/nrf53/hardware/nrf53_spu.h
Normal file
@ -0,0 +1,91 @@
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/****************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_spu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPU_H
|
||||
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "nrf53_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define NRF53_SPU_EVENTS_RAMACCERR_OFFSET 0x100 /* A security violation has been detected for the RAM memory space */
|
||||
#define NRF53_SPU_EVENTS_FLASHACCERR_OFFSET 0x104 /* A security violation has been detected for the FLASH memory space */
|
||||
#define NRF53_SPU_EVENTS_PERIPHACCERR_OFFSET 0x108 /* A security violation has been detected on one or several peripherals */
|
||||
#define NRF53_SPU_PUBLISH_RAMACCERR_OFFSET 0x180 /* Publish configuration for event RAMACCERR */
|
||||
#define NRF53_SPU_PUBLISH_FLASHACCERR_OFFSET 0x184 /* Publish configuration for event FLASHACCERR */
|
||||
#define NRF53_SPU_PUBLISH_PERIPHACCERR_OFFSET 0x188 /* Publish configuration for event PERIPHACCERR */
|
||||
#define NRF53_SPU_INTEN_OFFSET 0x300 /* Enable or disable interrupt */
|
||||
#define NRF53_SPU_INTSEL_OFFSET 0x304 /* Enable interrupt */
|
||||
#define NRF53_SPU_INTCLR_OFFSET 0x308 /* Disable interrupt */
|
||||
#define NRF53_SPU_CAP_OFFSET 0x400 /* Show implemented features for the current device */
|
||||
#define NRF53_SPU_CPULOCK_OFFSET 0x404 /* Configure bits to lock down CPU features at runtime */
|
||||
#define NRF53_SPU_EXTDOMAIN_OFFSET 0x440 /* Access for bus access generated from the external domain n */
|
||||
#define NRF53_SPU_DPPIPERM_OFFSET 0x480 /* Select between secure and non-secure attribute for the DPPI channels. */
|
||||
#define NRF53_SPU_DPPILOCK_OFFSET 0x484 /* Prevent further modification of the corresponding PERM register */
|
||||
#define NRF53_SPU_GPIOPORTPERM_OFFSET 0x4C0 /* Select between secure and non-secure attribute for pins 0 to 31 of port n. */
|
||||
#define NRF53_SPU_GPIOPORTLOCK_OFFSET 0x4C4 /* Prevent further modification of the corresponding PERM register */
|
||||
#define NRF53_SPU_FLASHNSCREGION_OFFSET 0x500 /* Define which flash region can contain the non-secure callable (NSC) region n */
|
||||
#define NRF53_SPU_FLASHNSCSIZE_OFFSET 0x504 /* Define the size of the non-secure callable (NSC) region n */
|
||||
#define NRF53_SPU_RAMNSCREGION_OFFSET 0x540 /* Define which RAM region can contain the non-secure callable (NSC) region n */
|
||||
#define NRF53_SPU_RAMNSCSIZE_OFFSET 0x544 /* Define the size of the non-secure callable (NSC) region n */
|
||||
#define NRF53_SPU_FLASHREGIONPERM_OFFSET 0x600 /* Access permissions for flash region n */
|
||||
#define NRF53_SPU_RAMREGIONPERM_OFFSET 0x700 /* Access permissions for RAM region n */
|
||||
#define NRF53_SPU_PERIPHIDPERM_OFFSET 0x800 /* List capabilities and access permissions for the peripheral with ID n */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define NRF53_SPU_EVENTS_RAMACCERR (NRF53_SPU_BASE + NRF53_SPU_EVENTS_RAMACCERR_OFFSET)
|
||||
#define NRF53_SPU_EVENTS_FLASHACCERR (NRF53_SPU_BASE + NRF53_SPU_EVENTS_FLASHACCERR_OFFSET)
|
||||
#define NRF53_SPU_EVENTS_PERIPHACCERR (NRF53_SPU_BASE + NRF53_SPU_EVENTS_PERIPHACCERR_OFFSET)
|
||||
#define NRF53_SPU_PUBLISH_RAMACCERR (NRF53_SPU_BASE + NRF53_SPU_PUBLISH_RAMACCERR_OFFSET)
|
||||
#define NRF53_SPU_PUBLISH_FLASHACCERR (NRF53_SPU_BASE + NRF53_SPU_PUBLISH_FLASHACCERR_OFFSET)
|
||||
#define NRF53_SPU_PUBLISH_PERIPHACCERR (NRF53_SPU_BASE + NRF53_SPU_PUBLISH_PERIPHACCERR_OFFSET)
|
||||
#define NRF53_SPU_INTEN (NRF53_SPU_BASE + NRF53_SPU_INTEN_OFFSET)
|
||||
#define NRF53_SPU_INTSEL (NRF53_SPU_BASE + NRF53_SPU_INTSEL_OFFSET)
|
||||
#define NRF53_SPU_INTCLR (NRF53_SPU_BASE + NRF53_SPU_INTCLR_OFFSET)
|
||||
#define NRF53_SPU_CAP (NRF53_SPU_BASE + NRF53_SPU_CAP_OFFSET)
|
||||
#define NRF53_SPU_CPULOCK (NRF53_SPU_BASE + NRF53_SPU_CPULOCK_OFFSET)
|
||||
#define NRF53_SPU_EXTDOMAIN (NRF53_SPU_BASE + NRF53_SPU_EXTDOMAIN_OFFSET)
|
||||
#define NRF53_SPU_DPPIPERM (NRF53_SPU_BASE + NRF53_SPU_DPPIPERM_OFFSET)
|
||||
#define NRF53_SPU_DPPILOCK (NRF53_SPU_BASE + NRF53_SPU_DPPILOCK_OFFSET)
|
||||
#define NRF53_SPU_GPIOPORTPERM (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTPERM_OFFSET)
|
||||
#define NRF53_SPU_GPIOPORTLOCK (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTLOCK_OFFSET)
|
||||
#define NRF53_SPU_FLASHNSCREGION (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCREGION_OFFSET)
|
||||
#define NRF53_SPU_FLASHNSCSIZE (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCSIZE_OFFSET)
|
||||
#define NRF53_SPU_RAMNSCREGION (NRF53_SPU_BASE + NRF53_SPU_RAMNSCREGION_OFFSET)
|
||||
#define NRF53_SPU_RAMNSCSIZE (NRF53_SPU_BASE + NRF53_SPU_RAMNSCSIZE_OFFSET)
|
||||
#define NRF53_SPU_FLASHREGIONPERM (NRF53_SPU_BASE + NRF53_SPU_FLASHREGIONPERM_OFFSET)
|
||||
#define NRF53_SPU_RAMREGIONPERM (NRF53_SPU_BASE + NRF53_SPU_RAMREGIONPERM_OFFSET)
|
||||
#define NRF53_SPU_PERIPHIDPERM (NRF53_SPU_BASE + NRF53_SPU_PERIPHIDPERM_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
/* TODO */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPU_H */
|
||||
@ -26,40 +26,11 @@
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf53_memorymap.h"
|
||||
|
||||
/***************************************************************************
|
||||
* Pre-processor Definitions
|
||||
***************************************************************************/
|
||||
|
||||
/* UICR Register Offsets ***************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT_OFFSET 0x000 /* Access port protection */
|
||||
#define NRF53_UICR_EXTSUPPLY_OFFSET 0x00C /* Enable external circuitry to be supplied from VDD pin. */
|
||||
#define NRF53_UICR_VREGHVOUT_OFFSET 0x010 /* GPIO reference voltage / external output supply voltage in High voltage mode */
|
||||
#define NRF53_UICR_HFXOCNT_OFFSET 0x014 /* HFXO startup counter */
|
||||
#define NRF53_UICR_SECUREAPPROTECT_OFFSET 0x01C /* Secure access port protection */
|
||||
#define NRF53_UICR_ERASEPROTECT_OFFSET 0x020 /* Erase protection */
|
||||
#define NRF53_UICR_TINSTANCE_OFFSET 0x024 /* SW-DP Target instance */
|
||||
#define NRF53_UICR_NFCPINS_OFFSET 0x028 /* Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
|
||||
#define NRF53_UICR_OTP_OFFSET 0x100 /* One time programmable memory */
|
||||
#define NRF53_UICR_KEYSLOTCONFIGDEST_OFFSET 0x400 /* Key slot destination address */
|
||||
#define NRF53_UICR_KEYSLOTCONFIGPERM_OFFSET 0x404 /* Permissions for the key slot */
|
||||
#define NRF53_UICR_KEYSLOTKEYVALUE_OFFSET 0x800 /* Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
|
||||
|
||||
/* UICR Register Addresses *************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT (NRF53_UICR_BASE + NRF53_UICR_APPROTECT_OFFSET)
|
||||
#define NRF53_UICR_EXTSUPPLY (NRF53_UICR_BASE + NRF53_UICR_EXTSUPPLY_OFFSET)
|
||||
#define NRF53_UICR_VREGHVOUT (NRF53_UICR_BASE + NRF53_UICR_VREGHVOUT_OFFSET)
|
||||
#define NRF53_UICR_HFXOCNT (NRF53_UICR_BASE + NRF53_UICR_HFXOCNT_OFFSET)
|
||||
#define NRF53_UICR_SECUREAPPROTECT (NRF53_UICR_BASE + NRF53_UICR_SECUREAPPROTECT_OFFSET)
|
||||
#define NRF53_UICR_ERASEPROTECT (NRF53_UICR_BASE + NRF53_UICR_ERASEPROTECT_OFFSET)
|
||||
#define NRF53_UICR_TINSTANCE (NRF53_UICR_BASE + NRF53_UICR_TINSTANCE_OFFSET)
|
||||
#define NRF53_UICR_NFCPINS (NRF53_UICR_BASE + NRF53_UICR_NFCPINS_OFFSET)
|
||||
#define NRF53_UICR_OTP (NRF53_UICR_BASE + NRF53_UICR_OTP_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTCONFIGDEST (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTCONFIGDEST_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTCONFIGPERM (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTCONFIGPERM_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTKEYVALUE (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTKEYVALUE_OFFSET)
|
||||
#ifdef CONFIG_NRF53_APPCORE
|
||||
# include "hardware/nrf53_uicr_cpuapp.h"
|
||||
#else
|
||||
# include "hardware/nrf53_uicr_cpunet.h"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_H */
|
||||
|
||||
65
arch/arm/src/nrf53/hardware/nrf53_uicr_cpuapp.h
Normal file
65
arch/arm/src/nrf53/hardware/nrf53_uicr_cpuapp.h
Normal file
@ -0,0 +1,65 @@
|
||||
/***************************************************************************
|
||||
* arch/arm/src/nrf53/hardware/nrf53_uicr_cpuapp.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUAPP_H
|
||||
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUAPP_H
|
||||
|
||||
/***************************************************************************
|
||||
* Included Files
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf53_memorymap.h"
|
||||
|
||||
/***************************************************************************
|
||||
* Pre-processor Definitions
|
||||
***************************************************************************/
|
||||
|
||||
/* UICR Register Offsets ***************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT_OFFSET 0x000 /* Access port protection */
|
||||
#define NRF53_UICR_EXTSUPPLY_OFFSET 0x00C /* Enable external circuitry to be supplied from VDD pin. */
|
||||
#define NRF53_UICR_VREGHVOUT_OFFSET 0x010 /* GPIO reference voltage / external output supply voltage in High voltage mode */
|
||||
#define NRF53_UICR_HFXOCNT_OFFSET 0x014 /* HFXO startup counter */
|
||||
#define NRF53_UICR_SECUREAPPROTECT_OFFSET 0x01C /* Secure access port protection */
|
||||
#define NRF53_UICR_ERASEPROTECT_OFFSET 0x020 /* Erase protection */
|
||||
#define NRF53_UICR_TINSTANCE_OFFSET 0x024 /* SW-DP Target instance */
|
||||
#define NRF53_UICR_NFCPINS_OFFSET 0x028 /* Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
|
||||
#define NRF53_UICR_OTP_OFFSET 0x100 /* One time programmable memory */
|
||||
#define NRF53_UICR_KEYSLOTCONFIGDEST_OFFSET 0x400 /* Key slot destination address */
|
||||
#define NRF53_UICR_KEYSLOTCONFIGPERM_OFFSET 0x404 /* Permissions for the key slot */
|
||||
#define NRF53_UICR_KEYSLOTKEYVALUE_OFFSET 0x800 /* Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
|
||||
|
||||
/* UICR Register Addresses *************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT (NRF53_UICR_BASE + NRF53_UICR_APPROTECT_OFFSET)
|
||||
#define NRF53_UICR_EXTSUPPLY (NRF53_UICR_BASE + NRF53_UICR_EXTSUPPLY_OFFSET)
|
||||
#define NRF53_UICR_VREGHVOUT (NRF53_UICR_BASE + NRF53_UICR_VREGHVOUT_OFFSET)
|
||||
#define NRF53_UICR_HFXOCNT (NRF53_UICR_BASE + NRF53_UICR_HFXOCNT_OFFSET)
|
||||
#define NRF53_UICR_SECUREAPPROTECT (NRF53_UICR_BASE + NRF53_UICR_SECUREAPPROTECT_OFFSET)
|
||||
#define NRF53_UICR_ERASEPROTECT (NRF53_UICR_BASE + NRF53_UICR_ERASEPROTECT_OFFSET)
|
||||
#define NRF53_UICR_TINSTANCE (NRF53_UICR_BASE + NRF53_UICR_TINSTANCE_OFFSET)
|
||||
#define NRF53_UICR_NFCPINS (NRF53_UICR_BASE + NRF53_UICR_NFCPINS_OFFSET)
|
||||
#define NRF53_UICR_OTP (NRF53_UICR_BASE + NRF53_UICR_OTP_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTCONFIGDEST (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTCONFIGDEST_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTCONFIGPERM (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTCONFIGPERM_OFFSET)
|
||||
#define NRF53_UICR_KEYSLOTKEYVALUE (NRF53_UICR_BASE + NRF53_UICR_KEYSLOTKEYVALUE_OFFSET)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUAPP_H */
|
||||
49
arch/arm/src/nrf53/hardware/nrf53_uicr_cpunet.h
Normal file
49
arch/arm/src/nrf53/hardware/nrf53_uicr_cpunet.h
Normal file
@ -0,0 +1,49 @@
|
||||
/***************************************************************************
|
||||
* arch/arm/src/nrf53/hardware/nrf53_uicr_cpunet.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUNET_H
|
||||
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUNET_H
|
||||
|
||||
/***************************************************************************
|
||||
* Included Files
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf53_memorymap.h"
|
||||
|
||||
/***************************************************************************
|
||||
* Pre-processor Definitions
|
||||
***************************************************************************/
|
||||
|
||||
/* UICR Register Offsets ***************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT_OFFSET 0x000 /* Access port protection */
|
||||
#define NRF53_UICR_ERASEPROTECT_OFFSET 0x004 /* Erase protection */
|
||||
#define NRF53_UICR_NRFFW_OFFSET 0x200 /* Reserved for Nordic firmware design */
|
||||
#define NRF53_UICR_CUSTOMER_OFFSET 0x300 /* Reserved for customer */
|
||||
|
||||
/* UICR Register Addresses *************************************************/
|
||||
|
||||
#define NRF53_UICR_APPROTECT (NRF53_UICR_BASE + NRF53_UICR_APPROTECT_OFFSET)
|
||||
#define NRF53_UICR_ERASEPROTECT (NRF53_UICR_BASE + NRF53_UICR_ERASEPROTECT_OFFSET)
|
||||
#define NRF53_UICR_NRFFW (NRF53_UICR_BASE + NRF53_UICR_NRFFW_OFFSET)
|
||||
#define NRF53_UICR_CUSTOMER (NRF53_UICR_BASE + NRF53_UICR_CUSTOMER_OFFSET)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UICR_CPUNET_H */
|
||||
Loading…
Reference in New Issue
Block a user