From 15dadd0099c054c7ecf1818754e7eae78b3c513f Mon Sep 17 00:00:00 2001 From: Lucas Saavedra Vaz Date: Tue, 22 Nov 2022 15:20:36 -0300 Subject: [PATCH] arch/xtensa/esp32: Remove redundant RTC registers --- .../xtensa/src/esp32/hardware/esp32_rtccntl.h | 127 ------------------ 1 file changed, 127 deletions(-) diff --git a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h index c36c63bb52..3fd76143d9 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h +++ b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h @@ -3046,19 +3046,6 @@ #define RTC_SLEEP_PD_XTAL BIT(6) -#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) - -/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ - -/* description: select the wakeup source Ó0Ó select - * GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 - */ - -#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001f -#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) -#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1f -#define RTC_IO_EXT_WAKEUP0_SEL_S 27 - /* RTC_CNTL_WDT_STGX : */ /* description: stage action selection values */ @@ -3083,118 +3070,4 @@ #define RTC_CNTL_DBIAS_1V20 6 #define RTC_CNTL_DBIAS_1V25 7 -#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) - -/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ - -/* description: Power up 32kHz crystal oscillator */ - -#define RTC_IO_XPD_XTAL_32K (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_V 0x1 -#define RTC_IO_XPD_XTAL_32K_S 19 - -/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ - -/* description: Ò1Ó select the digital function Ó0Óslection - * the rtc function - */ - -#define RTC_IO_X32N_MUX_SEL (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_V 0x1 -#define RTC_IO_X32N_MUX_SEL_S 18 - -/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ - -/* description: Ò1Ó select the digital function Ó0Óslection - * the rtc function - */ - -#define RTC_IO_X32P_MUX_SEL (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_V 0x1 -#define RTC_IO_X32P_MUX_SEL_S 17 - -/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ - -/* description: the pull down enable of the pad */ - -#define RTC_IO_X32P_RDE (BIT(23)) -#define RTC_IO_X32P_RDE_M (BIT(23)) -#define RTC_IO_X32P_RDE_V 0x1 -#define RTC_IO_X32P_RDE_S 23 - -/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ - -/* description: the pull up enable of the pad */ - -#define RTC_IO_X32P_RUE (BIT(22)) -#define RTC_IO_X32P_RUE_M (BIT(22)) -#define RTC_IO_X32P_RUE_V 0x1 -#define RTC_IO_X32P_RUE_S 22 - -/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ - -/* description: the pull up enable of the pad */ - -#define RTC_IO_X32N_RUE (BIT(27)) -#define RTC_IO_X32N_RUE_M (BIT(27)) -#define RTC_IO_X32N_RUE_V 0x1 -#define RTC_IO_X32N_RUE_S 27 - -/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ - -/* description: the pull down enable of the pad */ - -#define RTC_IO_X32N_RDE (BIT(28)) -#define RTC_IO_X32N_RDE_M (BIT(28)) -#define RTC_IO_X32N_RDE_V 0x1 -#define RTC_IO_X32N_RDE_S 28 - -/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ - -/* description: the input enable of the pad */ - -#define RTC_IO_X32N_FUN_IE (BIT(11)) -#define RTC_IO_X32N_FUN_IE_M (BIT(11)) -#define RTC_IO_X32N_FUN_IE_V 0x1 -#define RTC_IO_X32N_FUN_IE_S 11 - -/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ - -/* description: the input enable of the pad */ - -#define RTC_IO_X32P_FUN_IE (BIT(5)) -#define RTC_IO_X32P_FUN_IE_M (BIT(5)) -#define RTC_IO_X32P_FUN_IE_V 0x1 -#define RTC_IO_X32P_FUN_IE_S 5 - -/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ - -/* description: 32K XTAL bias current DAC. */ - -#define RTC_IO_DAC_XTAL_32K 0x00000003 -#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) -#define RTC_IO_DAC_XTAL_32K_V 0x3 -#define RTC_IO_DAC_XTAL_32K_S 20 - -/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ - -/* description: 32K XTAL resistor bias control. */ - -#define RTC_IO_DRES_XTAL_32K 0x00000003 -#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) -#define RTC_IO_DRES_XTAL_32K_V 0x3 -#define RTC_IO_DRES_XTAL_32K_S 3 - -/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ - -/* description: 32K XTAL self-bias reference control. */ - -#define RTC_IO_DBIAS_XTAL_32K 0x00000003 -#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) -#define RTC_IO_DBIAS_XTAL_32K_V 0x3 -#define RTC_IO_DBIAS_XTAL_32K_S 1 - #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RTCCNTL_H */