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stm32_hrtim: fix capture_get function, add software capture trigger, add software reset trigger, add outputs polarisation configuration

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This commit is contained in:
raiden00pl 2018-03-04 12:23:21 +01:00
parent 987a8298f2
commit 15dc86ddbb
3 changed files with 226 additions and 100 deletions
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101
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
View File

@ -958,75 +958,40 @@
#define HRTIM_TIMCHP_STRTPW_SHIFT 7 /* Bits 7-10: Chopper start pulsewidth */
#define HRTIM_TIMCHP_STRTPW_MASK (15 << HRTIM_TIMCHP_STRTPW_SHIFT)
/* Timer X Capture 1 Control Register */
/* Timer X Capture 12 Control Register */
#define HRTIM_TIMCPT1CR_SWCPT (1 << 0)
#define HRTIM_TIMCPT1CR_UPDCPT (1 << 1)
#define HRTIM_TIMCPT1CR_EXEV1CPT (1 << 2)
#define HRTIM_TIMCPT1CR_EXEV2CPT (1 << 3)
#define HRTIM_TIMCPT1CR_EXEV3CPT (1 << 4)
#define HRTIM_TIMCPT1CR_EXEV4CPT (1 << 5)
#define HRTIM_TIMCPT1CR_EXEV5CPT (1 << 6)
#define HRTIM_TIMCPT1CR_EXEV6CPT (1 << 7)
#define HRTIM_TIMCPT1CR_EXEV7CPT (1 << 8)
#define HRTIM_TIMCPT1CR_EXEV8CPT (1 << 9)
#define HRTIM_TIMCPT1CR_EXEV9CPT (1 << 10)
#define HRTIM_TIMCPT1CR_EXEV10CPT (1 << 11)
#define HRTIM_TIMCPT1CR_TA1SET (1 << 12)
#define HRTIM_TIMCPT1CR_TA1RST (1 << 13)
#define HRTIM_TIMCPT1CR_TACMP1 (1 << 14)
#define HRTIM_TIMCPT1CR_TACMP2 (1 << 15)
#define HRTIM_TIMCPT1CR_TB1SET (1 << 16)
#define HRTIM_TIMCPT1CR_TB1RST (1 << 17)
#define HRTIM_TIMCPT1CR_TBCMP1 (1 << 18)
#define HRTIM_TIMCPT1CR_TBCMP2 (1 << 19)
#define HRTIM_TIMCPT1CR_TC1SET (1 << 20)
#define HRTIM_TIMCPT1CR_TC1RST (1 << 21)
#define HRTIM_TIMCPT1CR_TCCMP1 (1 << 22)
#define HRTIM_TIMCPT1CR_TCCMP2 (1 << 23)
#define HRTIM_TIMCPT1CR_TD1SET (1 << 24)
#define HRTIM_TIMCPT1CR_TD1RST (1 << 25)
#define HRTIM_TIMCPT1CR_TDCMP1 (1 << 26)
#define HRTIM_TIMCPT1CR_TDCMP2 (1 << 27)
#define HRTIM_TIMCPT1CR_TE1SET (1 << 28)
#define HRTIM_TIMCPT1CR_TE1RST (1 << 29)
#define HRTIM_TIMCPT1CR_TECMP1 (1 << 30)
#define HRTIM_TIMCPT1CR_TECMP2 (1 << 31)
/* Timer X Capture 2 Control Register */
#define HRTIM_TIMCPT2CR_SWCPT (1 << 0)
#define HRTIM_TIMCPT2CR_UPDCPT (1 << 1)
#define HRTIM_TIMCPT2CR_EXEV1CPT (1 << 2)
#define HRTIM_TIMCPT2CR_EXEV2CPT (1 << 3)
#define HRTIM_TIMCPT2CR_EXEV3CPT (1 << 4)
#define HRTIM_TIMCPT2CR_EXEV4CPT (1 << 5)
#define HRTIM_TIMCPT2CR_EXEV5CPT (1 << 6)
#define HRTIM_TIMCPT2CR_EXEV6CPT (1 << 7)
#define HRTIM_TIMCPT2CR_EXEV7CPT (1 << 8)
#define HRTIM_TIMCPT2CR_EXEV8CPT (1 << 9)
#define HRTIM_TIMCPT2CR_EXEV9CPT (1 << 10)
#define HRTIM_TIMCPT2CR_EXEV10CPT (1 << 11)
#define HRTIM_TIMCPT2CR_TA1SET (1 << 12)
#define HRTIM_TIMCPT2CR_TA1RST (1 << 13)
#define HRTIM_TIMCPT2CR_TACMP1 (1 << 14)
#define HRTIM_TIMCPT2CR_TACMP2 (1 << 15)
#define HRTIM_TIMCPT2CR_TB1SET (1 << 16)
#define HRTIM_TIMCPT2CR_TB1RST (1 << 17)
#define HRTIM_TIMCPT2CR_TBCMP1 (1 << 18)
#define HRTIM_TIMCPT2CR_TBCMP2 (1 << 19)
#define HRTIM_TIMCPT2CR_TC1SET (1 << 20)
#define HRTIM_TIMCPT2CR_TC1RST (1 << 21)
#define HRTIM_TIMCPT2CR_TCCMP1 (1 << 22)
#define HRTIM_TIMCPT2CR_TCCMP2 (1 << 23)
#define HRTIM_TIMCPT2CR_TD1SET (1 << 24)
#define HRTIM_TIMCPT2CR_TD1RST (1 << 25)
#define HRTIM_TIMCPT2CR_TDCMP1 (1 << 26)
#define HRTIM_TIMCPT2CR_TDCMP2 (1 << 27)
#define HRTIM_TIMCPT2CR_TE1SET (1 << 28)
#define HRTIM_TIMCPT2CR_TE1RST (1 << 29)
#define HRTIM_TIMCPT2CR_TECMP1 (1 << 30)
#define HRTIM_TIMCPT2CR_TECMP2 (1 << 31)
#define HRTIM_TIMCPT12CR_SWCPT (1 << 0)
#define HRTIM_TIMCPT12CR_UPDCPT (1 << 1)
#define HRTIM_TIMCPT12CR_EXEV1CPT (1 << 2)
#define HRTIM_TIMCPT12CR_EXEV2CPT (1 << 3)
#define HRTIM_TIMCPT12CR_EXEV3CPT (1 << 4)
#define HRTIM_TIMCPT12CR_EXEV4CPT (1 << 5)
#define HRTIM_TIMCPT12CR_EXEV5CPT (1 << 6)
#define HRTIM_TIMCPT12CR_EXEV6CPT (1 << 7)
#define HRTIM_TIMCPT12CR_EXEV7CPT (1 << 8)
#define HRTIM_TIMCPT12CR_EXEV8CPT (1 << 9)
#define HRTIM_TIMCPT12CR_EXEV9CPT (1 << 10)
#define HRTIM_TIMCPT12CR_EXEV10CPT (1 << 11)
#define HRTIM_TIMCPT12CR_TA1SET (1 << 12)
#define HRTIM_TIMCPT12CR_TA1RST (1 << 13)
#define HRTIM_TIMCPT12CR_TACMP1 (1 << 14)
#define HRTIM_TIMCPT12CR_TACMP2 (1 << 15)
#define HRTIM_TIMCPT12CR_TB1SET (1 << 16)
#define HRTIM_TIMCPT12CR_TB1RST (1 << 17)
#define HRTIM_TIMCPT12CR_TBCMP1 (1 << 18)
#define HRTIM_TIMCPT12CR_TBCMP2 (1 << 19)
#define HRTIM_TIMCPT12CR_TC1SET (1 << 20)
#define HRTIM_TIMCPT12CR_TC1RST (1 << 21)
#define HRTIM_TIMCPT12CR_TCCMP1 (1 << 22)
#define HRTIM_TIMCPT12CR_TCCMP2 (1 << 23)
#define HRTIM_TIMCPT12CR_TD1SET (1 << 24)
#define HRTIM_TIMCPT12CR_TD1RST (1 << 25)
#define HRTIM_TIMCPT12CR_TDCMP1 (1 << 26)
#define HRTIM_TIMCPT12CR_TDCMP2 (1 << 27)
#define HRTIM_TIMCPT12CR_TE1SET (1 << 28)
#define HRTIM_TIMCPT12CR_TE1RST (1 << 29)
#define HRTIM_TIMCPT12CR_TECMP1 (1 << 30)
#define HRTIM_TIMCPT12CR_TECMP2 (1 << 31)
/* Timer X Output Register */

207
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -307,6 +307,37 @@
# define HRTIM_IRQ_COMMON 0
#endif
#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH1_POL)
# define HRTIM_TIMA_CH1_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH2_POL)
# define HRTIM_TIMA_CH2_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH1_POL)
# define HRTIM_TIMB_CH1_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH2_POL)
# define HRTIM_TIMB_CH2_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH1_POL)
# define HRTIM_TIMC_CH1_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH2_POL)
# define HRTIM_TIMC_CH2_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH1_POL)
# define HRTIM_TIMD_CH1_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH2_POL)
# define HRTIM_TIMD_CH2_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH1_POL)
# define HRTIM_TIME_CH1_POL HRTIM_OUT_POL_POS
#endif
#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH2_POL)
# define HRTIM_TIME_CH2_POL HRTIM_OUT_POL_POS
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@ -318,6 +349,7 @@ struct stm32_hrtim_timout_s
{
uint32_t set; /* Set events*/
uint32_t rst; /* Reset events*/
uint8_t pol:1; /* Output polarisation */
};
/* HRTIM Slave Timer Chopper Configuration */
@ -663,6 +695,8 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv);
static int hrtim_capture_config(FAR struct stm32_hrtim_s *priv);
static uint16_t hrtim_capture_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
static int hrtim_soft_capture(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
#endif
#if defined(CONFIG_STM32_HRTIM_SYNC)
static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv);
@ -736,6 +770,7 @@ static uint16_t hrtim_cmp_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
static uint64_t hrtim_fclk_get(FAR struct hrtim_dev_s *dev, uint8_t timer);
static int hrtim_soft_update(FAR struct hrtim_dev_s *dev, uint8_t timer);
static int hrtim_soft_reset(FAR struct hrtim_dev_s *dev, uint8_t timer);
static int hrtim_tim_freq_set(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
uint64_t freq);
static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
@ -821,14 +856,16 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv =
.ch1 =
{
.set = HRTIM_TIMA_CH1_SET,
.rst = HRTIM_TIMA_CH1_RST
.rst = HRTIM_TIMA_CH1_RST,
.pol = HRTIM_TIMA_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2
.ch2 =
{
.set = HRTIM_TIMA_CH2_SET,
.rst = HRTIM_TIMA_CH2_RST
.rst = HRTIM_TIMA_CH2_RST,
.pol = HRTIM_TIMA_CH2_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMA_BURST
@ -921,14 +958,16 @@ static struct stm32_hrtim_slave_priv_s g_timb_priv =
.ch1 =
{
.set = HRTIM_TIMB_CH1_SET,
.rst = HRTIM_TIMB_CH1_RST
.rst = HRTIM_TIMB_CH1_RST,
.pol = HRTIM_TIMB_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2
.ch2 =
{
.set = HRTIM_TIMB_CH2_SET,
.rst = HRTIM_TIMB_CH2_RST
.rst = HRTIM_TIMB_CH2_RST,
.pol = HRTIM_TIMB_CH2_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB_BURST
@ -1021,14 +1060,16 @@ static struct stm32_hrtim_slave_priv_s g_timc_priv =
.ch1 =
{
.set = HRTIM_TIMC_CH1_SET,
.rst = HRTIM_TIMC_CH1_RST
.rst = HRTIM_TIMC_CH1_RST,
.pol = HRTIM_TIMC_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2
.ch2 =
{
.set = HRTIM_TIMC_CH2_SET,
.rst = HRTIM_TIMC_CH2_RST
.rst = HRTIM_TIMC_CH2_RST,
.pol = HRTIM_TIMC_CH2_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC_BURST
@ -1121,14 +1162,16 @@ static struct stm32_hrtim_slave_priv_s g_timd_priv =
.ch1 =
{
.set = HRTIM_TIMD_CH1_SET,
.rst = HRTIM_TIMD_CH1_RST
.rst = HRTIM_TIMD_CH1_RST,
.pol = HRTIM_TIMD_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2
.ch2 =
{
.set = HRTIM_TIMD_CH2_SET,
.rst = HRTIM_TIMD_CH2_RST
.rst = HRTIM_TIMD_CH2_RST,
.pol = HRTIM_TIMD_CH2_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD_BURST
@ -1221,14 +1264,16 @@ static struct stm32_hrtim_slave_priv_s g_time_priv =
.ch1 =
{
.set = HRTIM_TIME_CH1_SET,
.rst = HRTIM_TIME_CH1_RST
.rst = HRTIM_TIME_CH1_RST,
.pol = HRTIM_TIME_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2
.ch2 =
{
.set = HRTIM_TIME_CH2_SET,
.rst = HRTIM_TIME_CH2_RST
.rst = HRTIM_TIME_CH2_RST,
.pol = HRTIM_TIME_CH1_POL
},
#endif
#ifdef CONFIG_STM32_HRTIM_TIME_BURST
@ -1545,6 +1590,7 @@ static const struct stm32_hrtim_ops_s g_hrtim1ops =
.cmp_get = hrtim_cmp_get,
.fclk_get = hrtim_fclk_get,
.soft_update = hrtim_soft_update,
.soft_reset = hrtim_soft_reset,
.freq_set = hrtim_tim_freq_set,
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
.irq_ack = hrtim_irq_ack,
@ -1573,6 +1619,7 @@ static const struct stm32_hrtim_ops_s g_hrtim1ops =
#endif
#ifdef CONFIG_STM32_HRTIM_CAPTURE
.capture_get = hrtim_capture_get,
.soft_capture = hrtim_soft_capture,
#endif
};
@ -2697,13 +2744,13 @@ static uint16_t hrtim_capture_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
{
case HRTIM_CAPTURE1:
{
offset = STM32_HRTIM_TIM_CPT1CR_OFFSET;
offset = STM32_HRTIM_TIM_CPT1R_OFFSET;
break;
}
case HRTIM_CAPTURE2:
{
offset = STM32_HRTIM_TIM_CPT2CR_OFFSET;
offset = STM32_HRTIM_TIM_CPT2R_OFFSET;
break;
}
@ -2719,6 +2766,57 @@ static uint16_t hrtim_capture_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
errout:
return regval;
}
/****************************************************************************
* Name: hrtim_soft_capture
*
* Description:
* HRTIM Timer software capture tirgger.
*
* Input Parameters:
* dev - HRTIM device structure
* timer - HRTIM Timer indexes
* index - HRTIM capture index
*
* Returned Value:
* 0 on success; a negated errno value on failure
*
****************************************************************************/
static int hrtim_soft_capture(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
uint32_t offset = 0;
switch (index)
{
case HRTIM_CAPTURE1:
{
offset = STM32_HRTIM_TIM_CPT1CR_OFFSET;
break;
}
case HRTIM_CAPTURE2:
{
offset = STM32_HRTIM_TIM_CPT2CR_OFFSET;
break;
}
default:
{
goto errout;
}
}
/* Modify register */
hrtim_tim_modifyreg(priv, timer, offset, 0, HRTIM_TIMCPT12CR_SWCPT);
errout:
return OK;
}
#endif
/****************************************************************************
@ -2793,13 +2891,15 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
regval = slave->pwm.ch2.rst;
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, regval);
/* Now we configure OUT register */
regval = 0;
#ifdef CONFIG_STM32_HRTIM_BURST
/* Configure IDLE state for output 1 */
if (slave->pwm.burst.ch1_en)
{
regval = 0;
/* Set IDLE mode */
regval |= HRTIM_TIMOUT_IDLEM1;
@ -2809,18 +2909,12 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
regval |= ((slave->pwm.burst.ch1_state & HRTIM_IDLE_ACTIVE) ?
HRTIM_TIMOUT_IDLES1 : 0);
/* Write register */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0,
regval);
}
/* Configure IDLE state for output 2 */
if (slave->pwm.burst.ch2_en)
{
regval = 0;
/* Set IDLE mode */
regval |= HRTIM_TIMOUT_IDLEM1;
@ -2829,32 +2923,34 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
regval |= ((slave->pwm.burst.ch2_state & HRTIM_IDLE_ACTIVE) ?
HRTIM_TIMOUT_IDLES1 : 0);
/* Write register */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0,
regval);
}
#endif
#ifdef CONFIG_STM32_HRTIM_DEADTIME
if (slave->pwm.dt.en == 1)
{
regval = 0;
/* Set deadtime enable */
regval |= HRTIM_TIMOUT_DTEN;
/* TODO: deadtime upon burst mode Idle entry */
/* Write register */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0,
regval);
}
#endif
/* Configure Output 1 polarisation */
regval |= ((slave->pwm.ch1.pol & HRTIM_OUT_POL_NEG) ?
HRTIM_TIMOUT_POL1 : 0);
/* Configure Output 2 polarisation */
regval |= ((slave->pwm.ch2.pol & HRTIM_OUT_POL_NEG) ?
HRTIM_TIMOUT_POL2 : 0);
/* Write HRTIM Slave Timer Output register */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, regval);
#ifdef CONFIG_STM32_HRTIM_PUSHPULL
if (slave->pwm.pushpull == 1)
{
@ -5070,6 +5166,53 @@ static int hrtim_soft_update(FAR struct hrtim_dev_s *dev, uint8_t timer)
return OK;
}
/****************************************************************************
* Name: hrtim_soft_reset
*
* Description:
* HRTIM Timer software reset.
* This is bulk operation, so we can update many registers at the same time.
*
* Input Parameters:
* dev - HRTIM device structure
* timer - HRTIM Timer indexes
*
* Returned Value:
* 0 on success; a negated errno value on failure
*
****************************************************************************/
static int hrtim_soft_reset(FAR struct hrtim_dev_s *dev, uint8_t timer)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
uint32_t regval = 0;
regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MRST : 0);
#ifdef CONFIG_STM32_HRTIM_TIMA
regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TARST : 0);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBRST : 0);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCRST : 0);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDRST : 0);
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TERST : 0);
#endif
/* Bits in HRTIM CR2 common register are automatically reset,
* so we can just write to it.
*/
hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval);
return OK;
}
/****************************************************************************
* Name: hrtim_tim_freq_set
*

18
arch/arm/src/stm32/stm32_hrtim.h
View File

@ -218,10 +218,16 @@
(hrtim)->hd_ops->fclk_get(hrtim, tim)
#define HRTIM_IRQ_GET(hrtim, irq) \
(hrtim)->hd_ops->irq_get(hrtim, irq)
#define HRTIM_CAPTURE_GET(hrtim, timer, cap) \
(hrtim)->hd_ops->capture_get(hrtim, timer, cap)
#define HRTIM_IRQ_ACK(hrtim, irq, ack) \
(hrtim)->hd_ops->irq_ack(hrtim, irq, ack)
#define HRTIM_SOFT_UPDATE(hrtim, timer) \
(hrtim)->hd_ops->soft_update(hrtim, timer)
#define HRTIM_SOFT_CAPTURE(hrtim, timer, index) \
(hrtim)->hd_ops->soft_capture(hrtim, timer, index)
#define HRTIM_SOFT_RESET(hrtim, timer) \
(hrtim)->hd_ops->soft_reset(hrtim, timer)
#define HRTIM_FREQ_SET(hrtim, timer,freq) \
(hrtim)->hd_ops->freq_set(hrtim, timer, freq)
#define HRTIM_OUTPUTS_ENABLE(hrtim, outputs, state) \
@ -590,6 +596,14 @@ enum stm32_outputs_e
HRTIM_OUT_TIME_CH2 = (1 << 9)
};
/* HRTIM Output polarisation */
enum stm32_output_polarisation_e
{
HRTIM_OUT_POL_POS = 0,
HRTIM_OUT_POL_NEG = 1
};
/* HRTIM Deadtime sign */
enum stm32_hrtim_deadtime_sign_e
@ -1009,6 +1023,7 @@ struct stm32_hrtim_ops_s
uint8_t index);
uint64_t (*fclk_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
int (*soft_update)(FAR struct hrtim_dev_s *dev, uint8_t timer);
int (*soft_reset)(FAR struct hrtim_dev_s *dev, uint8_t timer);
int (*freq_set)(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
uint64_t freq);
@ -1046,6 +1061,9 @@ struct stm32_hrtim_ops_s
#ifdef CONFIG_STM32_HRTIM_CAPTURE
uint16_t (*capture_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
int (*soft_capture)(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
#endif
};