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Corrections to the Kinetis TSI header file from Alan Carvalho de Assis

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This commit is contained in:
Gregory Nutt 2013-06-18 07:14:05 -06:00
parent 161af4bf33
commit 15e846ad1d
4 changed files with 10 additions and 6 deletions
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3
ChangeLog
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@ -4996,3 +4996,6 @@
96MHz. This might have broken some things? (2013-6-17).
* drivers/mmcsd/mmcsd-spi.c: Driver need to make sure that the SPI mode
and data width are correct (2013-6-17).
* arch/arm/src/kinetis/kinetis_tsi.h: Corrections to the Kinetis
(2013-6-18)

4
arch/arm/src/kinetis/kinetis_tsi.h
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@ -137,7 +137,7 @@
#define TSI_GENCS_OUTRGF (1 << 14) /* Bit 14: Out of Range Flag */
#define TSI_GENCS_EOSF (1 << 15) /* Bit 15: End of scan flag */
#define TSI_GENCS_PS_SHIFT (16) /* Bits 16-18: Electrode oscillator prescaler */
#define TSI_GENCS_PS_MASK (3 << TSI_GENCS_PS_SHIFT)
#define TSI_GENCS_PS_MASK (7 << TSI_GENCS_PS_SHIFT)
# define TSI_GENCS_PS_DIV1 (0 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 1 */
# define TSI_GENCS_PS_DIV2 (1 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 2 */
# define TSI_GENCS_PS_DIV4 (2 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 4 */
@ -148,7 +148,7 @@
# define TSI_GENCS_PS_DIV128 (7 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 128 */
#define TSI_GENCS_NSCN_SHIFT (19) /* Bits 19-23: Number of Consecutive Scans per Electrode */
#define TSI_GENCS_NSCN_MASK (31 << TSI_GENCS_NSCN_SHIFT)
# define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_MASK) /* n times per electrode, n=1..32 */
# define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_SHIFT) /* n times per electrode, n=1..32 */
#define TSI_GENCS_LPSCNITV_SHIFT (24) /* Bits 24-27: TSI Low Power Mode Scan Interval */
#define TSI_GENCS_LPSCNITV_MASK (15 << TSI_GENCS_LPSCNITV_SHIFT)
# define TSI_GENCS_LPSCNITV_1MS (0 << TSI_GENCS_LPSCNITV_SHIFT) /* 1 ms scan interval */

6
arch/arm/src/sam34/chip/sam_spi.h
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@ -111,7 +111,7 @@
#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */
# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
@ -124,7 +124,7 @@
#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */
# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
@ -135,7 +135,7 @@
#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */
# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */

3
arch/arm/src/sam34/sam_spi.c
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@ -368,7 +368,8 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
*
****************************************************************************/
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
{
FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
uint32_t regval;