ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM

arch/arm/src/armv7-a/cache.h

@@ -193,6 +193,26 @@
 
 #ifdef __ASSEMBLY__
 
+/************************************************************************************
+ * Name: cp15_disable_dcache
+ *
+ * Description:
+ *   Disable L1 D Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.macro	cp15_disable_dcache, tmp
+	mrc		p15, 0, \tmp, c1, c0, 0		/* Read SCTLR */
+	bic		\tmp, \tmp, #(0x1 << 2)		/* Disable D cache */
+	mcr		p15, 0, \tmp, c1, c0, 0		/* Updagte the SCTLR */
+	.endm
+
 /************************************************************************************
  * Name: cp15_disable_caches
  *
@@ -207,7 +227,7 @@
  *
  ************************************************************************************/
 
-	.macro	cp15_invalidate_icache_inner_sharable, tmp
+	.macro	cp15_disable_caches, tmp
 	mrc		p15, 0, \tmp, c1, c0, 0		/* Read SCTLR */
 	bic		\tmp, \tmp, #(0x1 << 12)	/* Disable I cache */
 	bic		\tmp, \tmp, #(0x1 << 2)		/* Disable D cache */
@@ -461,6 +481,33 @@
 
 #ifndef __ASSEMBLY__
 
+/************************************************************************************
+ * Name: cp15_disable_dcache
+ *
+ * Description:
+ *   Disable L1 Caches
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+static inline void cp15_disable_dcache(void)
+{
+  __asm__ __volatile__
+    (
+      "\tmrc  p15, 0, r0, c1, c0, 0\n"  /* Read SCTLR */
+      "\tbic  r0, r0, #(1 << 2)\n"      /* Disable D cache */
+      "\tmcr  p15, 0, r0, c1, c0, 0\n"  /* Updagte the SCTLR */
+      :
+      :
+      : "r0", "memory"
+    );
+}
+
 /************************************************************************************
  * Name: cp15_disable_caches
  *
@@ -480,8 +527,8 @@ static inline void cp15_disable_caches(void)
   __asm__ __volatile__
     (
       "\tmrc  p15, 0, r0, c1, c0, 0\n"  /* Read SCTLR */
-      "\tbic  r0, r0, #(0x1 << 12)\n"   /* Disable I cache */
+      "\tbic  r0, r0, #(1 << 12)\n"     /* Disable I cache */
-      "\tbic  r0, r0, #(0x1 << 2)\n"    /* Disable D cache */
+      "\tbic  r0, r0, #(1 << 2)\n"      /* Disable D cache */
       "\tmcr  p15, 0, r0, c1, c0, 0\n"  /* Updagte the SCTLR */
       :
       :

arch/arm/src/sama5/sam_irq.c

@@ -283,11 +283,14 @@ void up_irqinitialize(void)
 
   putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
 
-#ifdef CONFIG_ARCH_LOWVECTORS
+#if defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_SAMA5_BOOT_ISRAM)
-  /* Set remap state 0.  This is done late in the boot sequence.  Any
+  /* Set remap state 0 if we are running from internal SRAM.  If we booted
-   * exceptions taken before this point in time will be handled by the
+   * into NOR FLASH, then the first level bootloader should have already
-   * ROM code, not by the NuttX interrupt since which was, up to this
+   * provided this mapping for us.
-   * point, uninitialized.
+   *
+   * This is done late in the boot sequence.  Any exceptions taken before
+   * this point in time will be handled by the ROM code, not by the NuttX
+   * interrupt since which was, up to this point, uninitialized.
    *
    *   Boot state:    ROM is seen at address 0x00000000
    *   Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave