sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

risc-v/esp32c3: Support ESP32-C3 PM standby and sleep

Browse Source
This commit is contained in:
chenwen 2021-04-28 18:40:56 +08:00 committed by Alan Carvalho de Assis
parent 3156aa7532
commit 16667930cb
22 changed files with 4859 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/risc-v/src/esp32c3/Make.defs
View File

@ -112,6 +112,15 @@ ifeq ($(CONFIG_ESP32C3_DMA),y)
CHIP_CSRCS += esp32c3_dma.c
endif
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp32c3_pminitialize.c
endif
CHIP_CSRCS += esp32c3_pm.c
endif
CHIP_CSRCS += esp32c3_rtc.c
ifeq ($(CONFIG_ESP32C3_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 2b53111

129
arch/risc-v/src/esp32c3/esp32c3_idle.c
View File

@ -28,19 +28,142 @@
#include <nuttx/power/pm.h>
#include "esp32c3.h"
#include "esp32c3_pm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Values for the RTC Alarm to wake up from the PM_STANDBY mode
* (which corresponds to ESP32-C3 stop mode). If this alarm expires,
* the logic in this file will wakeup from PM_STANDBY mode and
* transition to PM_SLEEP mode (ESP32-C3 standby mode).
*/
#ifdef CONFIG_PM
#ifndef CONFIG_PM_ALARM_SEC
# define CONFIG_PM_ALARM_SEC 15
#endif
#ifndef CONFIG_PM_ALARM_NSEC
# define CONFIG_PM_ALARM_NSEC 0
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC
# define CONFIG_PM_SLEEP_WAKEUP_SEC 20
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC
# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = spin_lock_irqsave(NULL);
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
spin_unlock_irqrestore(NULL, flags);
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
{
/* Enter Force-sleep mode */
esp32c3_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
}
break;
case PM_SLEEP:
{
/* Enter Deep-sleep mode */
esp32c3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
}
break;
default:
break;
}
}
else
{
if (oldstate == PM_NORMAL)
{
/* Relax normal operation */
pm_relax(PM_IDLE_DOMAIN, PM_NORMAL);
}
#ifdef CONFIG_WATCHDOG
/* Announce the power management state change to feed watchdog */
pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
#endif
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Name: up_idle
*
@ -69,5 +192,9 @@ void up_idle(void)
asm("WFI");
/* Perform IDLE mode power management */
up_idlepm();
#endif
}

1266
arch/risc-v/src/esp32c3/esp32c3_pm.c Normal file
View File

File diff suppressed because it is too large Load Diff

155
arch/risc-v/src/esp32c3/esp32c3_pm.h Normal file
View File

@ -0,0 +1,155 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H
#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32c3_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp32c3_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32c3_light_sleep_start(void);
/****************************************************************************
* Name: esp32c3_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_pminit(void);
/****************************************************************************
* Name: esp32c3_pmstandby
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_pmstandby(uint64_t time_in_us);
/****************************************************************************
* Name: esp32c3_deep_sleep_start
*
* Description:
* Enter deep sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_deep_sleep_start(void);
/****************************************************************************
* Name: esp32c3_pmsleep
*
* Description:
* Enter deep sleep.
*
* Input Parameters:
* time_in_us - deep sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_pmsleep(uint64_t time_in_us);
#endif /* CONFIG_PM */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H */

55
arch/risc-v/src/esp32c3/esp32c3_pminitialize.c Normal file
View File

@ -0,0 +1,55 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_pminitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/power/pm.h>
#include "esp32c3_pm.h"
#ifdef CONFIG_PM
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_pminitialize
*
* Description:
* Initialize the power management subsystem.
*
****************************************************************************/
void riscv_pminitialize(void)
{
/* Initialize RTC parameters */
esp32c3_pminit();
/* Then initialize the NuttX power management subsystem proper */
pm_initialize();
}
#endif /* CONFIG_PM */

2099
arch/risc-v/src/esp32c3/esp32c3_rtc.c Normal file
View File

File diff suppressed because it is too large Load Diff

437
arch/risc-v/src/esp32c3/esp32c3_rtc.h Normal file
View File

@ -0,0 +1,437 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H
#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/esp32c3_soc.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Cycles for RTC Timer clock source (internal oscillator) calibrate */
#define RTC_CLK_SRC_CAL_CYCLES (10)
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_SLEEP_PD_DIG BIT(0) /* Deep sleep */
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */
/* RTC FAST and SLOW memories are automatically
* powered up and down along with the CPU
*/
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)
#define RTC_SLEEP_PD_VDDSDIO BIT(5) /* Power down VDDSDIO regulator */
#define RTC_SLEEP_PD_WIFI BIT(6) /* Power down Wi-Fi */
#define RTC_SLEEP_PD_BT BIT(7) /* Power down BT */
#define RTC_SLEEP_PD_CPU BIT(8) /* Power down CPU when in light-sleep */
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) /* Power down DIG peripherals */
/****************************************************************************
* Public Types
****************************************************************************/
/* Clock source to be calibrated using rtc_clk_cal function */
enum esp32c3_rtc_cal_sel_e
{
RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */
RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */
RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */
};
/* CPU clock source */
enum esp32c3_rtc_cpu_freq_src_e
{
RTC_CPU_FREQ_SRC_XTAL, /* XTAL */
RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */
RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */
RTC_CPU_FREQ_SRC_APLL /* APLL */
};
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32c3_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_32M = 32,
RTC_XTAL_FREQ_40M = 40,
};
/* RTC SLOW_CLK frequency values */
enum esp32c3_rtc_slow_freq_e
{
RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */
RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */
RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */
};
/* CPU clock configuration structure */
struct esp32c3_cpu_freq_config_s
{
/* The clock from which CPU clock is derived */
enum esp32c3_rtc_cpu_freq_src_e source;
uint32_t source_freq_mhz; /* Source clock frequency */
uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */
uint32_t freq_mhz; /* CPU clock frequency */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32c3_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32c3_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32c3_rtc_xtal_freq_e esp32c3_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32c3_rtc_clk_slow_freq_get
*
* Description:
* Get the RTC_SLOW_CLK source
*
* Input Parameters:
* None
*
* Returned Value:
* Currently selected clock source
* (one of enum esp32c3_rtc_slow_freq_e values)
*
****************************************************************************/
enum esp32c3_rtc_slow_freq_e esp32c3_rtc_clk_slow_freq_get(void);
/****************************************************************************
* Name: esp32c3_rtc_clk_slow_freq_set
*
* Description:
* Select source for RTC_SLOW_CLK
*
* Input Parameters:
* slow_freq - clock source (one of esp32c3_rtc_slow_freq_e values)
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_clk_slow_freq_set(enum esp32c3_rtc_slow_freq_e slow_freq);
/****************************************************************************
* Name: esp32c3_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_clk_set(void);
/****************************************************************************
* Name: esp32c3_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_init(void);
/****************************************************************************
* Name: esp32c3_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32c3_rtc_time_get(void);
/****************************************************************************
* Name: esp32c3_rtc_time_us_to_slowclk
*
* Description:
* Convert time interval from microseconds to RTC_SLOW_CLK cycles.
*
* Input Parameters:
* time_in_us - Time interval in microseconds
* slow_clk_period - Period of slow clock in microseconds
*
* Returned Value:
* number of slow clock cycles
*
****************************************************************************/
uint64_t esp32c3_rtc_time_us_to_slowclk(uint64_t time_in_us,
uint32_t period);
/****************************************************************************
* Name: esp32c3_rtc_cpu_freq_set_xtal
*
* Description:
* Switch CPU clock source to XTAL
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_cpu_freq_set_xtal(void);
/****************************************************************************
* Name: esp32c3_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32c3_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
uint32_t esp32c3_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
uint32_t lslp_mem_inf_fpu);
/****************************************************************************
* Name: esp32c3_rtc_clk_cal
*
* Description:
* Measure RTC slow clock's period, based on main XTAL frequency
*
* Input Parameters:
* cal_clk - clock to be measured
* slowclk_cycles - number of slow clock cycles to average
*
* Returned Value:
* Average slow clock period in microseconds, Q13.19 fixed point format
* or 0 if calibration has timed out
*
****************************************************************************/
uint32_t esp32c3_rtc_clk_cal(enum esp32c3_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
/****************************************************************************
* Name: esp32c3_rtc_time_slowclk_to_us
*
* Description:
* Convert time interval from RTC_SLOW_CLK to microseconds
*
* Input Parameters:
* rtc_cycles - Time interval in RTC_SLOW_CLK cycles
* period - Period of slow clock in microseconds
*
* Returned Value:
* time interval in microseconds
*
****************************************************************************/
uint64_t esp32c3_rtc_time_slowclk_to_us(uint64_t rtc_cycles,
uint32_t period);
/****************************************************************************
* Name: esp32c3_rtc_deep_sleep_start
*
* Description:
* Enter deep sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
uint32_t esp32c3_rtc_deep_sleep_start(uint32_t wakeup_opt,
uint32_t reject_opt);
/****************************************************************************
* Name: esp32c3_rtc_clk_cpu_freq_set_config
*
* Description:
* Set CPU frequency configuration.
*
* Input Parameters:
* config - CPU frequency configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_clk_cpu_freq_set_config(
const struct esp32c3_cpu_freq_config_s *config);
/****************************************************************************
* Name: esp32c3_rtc_sleep_low_init
*
* Description:
* Low level initialize for rtc state machine waiting
* cycles after waking up.
*
* Input Parameters:
* slowclk_period - Re-calibrated slow clock period
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_sleep_low_init(uint32_t slowclk_period);
/****************************************************************************
* Name: esp32c3_rtc_clk_cpu_freq_get_config
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU clock configuration structure
*
****************************************************************************/
void esp32c3_rtc_clk_cpu_freq_get_config(
struct esp32c3_cpu_freq_config_s *out_config);
/****************************************************************************
* Name: esp32c3_rtc_sleep_set_wakeup_time
*
* Description:
* Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source.
*
* Input Parameters:
* t - value of RTC counter at which wakeup from sleep will happen.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32c3_rtc_sleep_set_wakeup_time(uint64_t t);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H */

73
arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h Normal file
View File

@ -0,0 +1,73 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
#define APB_CTRL_SRAM_POWER_UP_V 0xF
#define APB_CTRL_SRAM_POWER_UP_S 2
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
#define APB_CTRL_ROM_POWER_UP 0x00000003
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
#define APB_CTRL_ROM_POWER_UP_V 0x3
#define APB_CTRL_ROM_POWER_UP_S 0
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H_ */

49
arch/risc-v/src/esp32c3/hardware/bb_reg.h Normal file
View File

@ -0,0 +1,49 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/bb_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H_ */

38
arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h
View File

@ -264,5 +264,43 @@
/* Helper to place a value in a field */
#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_SOC_CLK_SEL_XTAL 0
#define DPORT_SOC_CLK_SEL_PLL 1
#define DPORT_SOC_CLK_SEL_8M 2
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H */

21
arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h
View File

@ -2182,4 +2182,25 @@
#define UART_REG_UPDATE_V 0x00000001
#define UART_REG_UPDATE_S 31
/* ESP32-C3 have 2 UART: UART0-1 */
#define ESP32C3_NUARTS 2
/* UART has an extra TX_WAIT_SEND state when the
* FIFO is not empty and XOFF is enabled.
*/
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define UART_FSM_IDLE (0x0)
#define UART_FSM_TX_WAIT_SEND (0xf)
/* Software write 1 would synchronize registers into UART Core clock
* domain and would be cleared by hardware after synchronization is done.
*/
#define UART_UPDATE (BIT(31))
#define UART_UPDATE_M (BIT(31))
#define UART_UPDATE_V 0x1
#define UART_UPDATE_S 31
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H */

57
arch/risc-v/src/esp32c3/hardware/extmem_reg.h Normal file
View File

@ -0,0 +1,57 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/extmem_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC)
#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008)
/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1.
* The bit is used to enable clock gating to save
* power when access mmu memory 0: enable 1: disable
*/
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0))
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0
/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1.
* description: The bit is used to close clock gating of icache tag memory.
* 1: close gating 0: open clock gating.
*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H_ */

50
arch/risc-v/src/esp32c3/hardware/fe_reg.h Normal file
View File

@ -0,0 +1,50 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/fe_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H_ */

52
arch/risc-v/src/esp32c3/hardware/nrx_reg.h Normal file
View File

@ -0,0 +1,52 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/nrx_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Some of the Wi-Fi RX control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
#define NRX_RX_ROT_FORCE_PU (BIT(5))
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
#define NRX_RX_ROT_FORCE_PU_V 1
#define NRX_RX_ROT_FORCE_PU_S 5
#define NRX_VIT_FORCE_PU (BIT(3))
#define NRX_VIT_FORCE_PU_M (BIT(3))
#define NRX_VIT_FORCE_PU_V 1
#define NRX_VIT_FORCE_PU_S 3
#define NRX_DEMAP_FORCE_PU (BIT(1))
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
#define NRX_DEMAP_FORCE_PU_V 1
#define NRX_DEMAP_FORCE_PU_S 1
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H_ */

75
arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h Normal file
View File

@ -0,0 +1,75 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register definitions for digital PLL (BBPLL). This file lists
* register fields of BBPLL, located on an internal configuration bus.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_OC_VCO_DBIAS 9
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H_ */

69
arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h Normal file
View File

@ -0,0 +1,69 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
/* ROM functions which read/write internal control bus */
extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id,
uint8_t reg_add);
extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb);
extern void rom_i2c_writereg(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t data);
extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
/* Convenience macros for the above functions, these use register
* definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/
* regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
rom_i2c_readreg(block, block##_HOSTID, reg_add)
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H_ */

59
arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h Normal file
View File

@ -0,0 +1,59 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register definitions for digital to get rtc voltage & digital voltage
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
*/
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 0
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_EXT_DIG_DREG 6
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_XPD_RTC_REG 13
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
#define I2C_DIG_REG_XPD_DIG_REG 13
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H_ */

40
arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h Normal file
View File

@ -0,0 +1,40 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register definitions for analog to calibrate o_code for getting a more
* precise voltage. This file lists register fields of low power dbais,
* located on an internal configuration bus.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_FORCE_XPD_CK 0
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H_ */

46
arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h Normal file
View File

@ -0,0 +1,46 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC)
/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1.
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
#define SPI_MEM_CLK_EN (BIT(0))
#define SPI_MEM_CLK_EN_M (BIT(0))
#define SPI_MEM_CLK_EN_V 0x1
#define SPI_MEM_CLK_EN_S 0
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H_ */

32
boards/risc-v/esp32c3/esp32c3-devkit/Kconfig
View File

@ -5,6 +5,38 @@
if ARCH_BOARD_ESP32C3_DEVKIT
if PM
config PM_ALARM_SEC
int "PM_STANDBY delay (seconds)"
default 15
depends on PM
---help---
Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
config PM_ALARM_NSEC
int "PM_STANDBY delay (nanoseconds)"
default 0
depends on PM
---help---
Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
config PM_SLEEP_WAKEUP_SEC
int "PM_SLEEP delay (seconds)"
default 20
depends on PM
---help---
Number of seconds to wait in PM_SLEEP.
config PM_SLEEP_WAKEUP_NSEC
int "PM_SLEEP delay (nanoseconds)"
default 0
depends on PM
---help---
Number of additional nanoseconds to wait in PM_SLEEP.
endif # PM
config ESP32C3_DEVKIT_RUN_IRAM
bool "Run from IRAM"
default n

47
boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig Normal file
View File

@ -0,0 +1,47 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="esp32c3-devkit"
CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
CONFIG_ARCH_CHIP="esp32c3"
CONFIG_ARCH_CHIP_ESP32C3=y
CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
CONFIG_ARCH_INTERRUPTSTACK=1536
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=15000
CONFIG_BUILTIN=y
CONFIG_DEV_ZERO=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_MAX_TASKS=8
CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PM=y
CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=y
CONFIG_PM_GOVERNOR_GREEDY=y
CONFIG_PREALLOC_TIMERS=0
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=29
CONFIG_START_MONTH=11
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"

4
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld
View File

@ -1815,9 +1815,9 @@ rom_get_i2c_read_mask = 0x40001948;
rom_get_pwctrl_correct = 0x4000194c;
rom_get_rf_gain_qdb = 0x40001950;
rom_i2c_readreg = 0x40001954;
rom_i2c_readreg_Mask = 0x40001958;
rom_i2c_readreg_mask = 0x40001958;
rom_i2c_writereg = 0x4000195c;
rom_i2c_writereg_Mask = 0x40001960;
rom_i2c_writereg_mask = 0x40001960;
rom_index_to_txbbgain = 0x40001964;
rom_iq_est_disable = 0x40001968;
rom_iq_est_enable = 0x4000196c;